JPH03250750A - Manufacture of soi substrate and semiconductor device - Google Patents

Abstract

PURPOSE:To enable an element formation layer to be fed with an arbitrary potential by a method wherein the element formation layer is isolated in an insular shape and electrically connected to a conductor layer or a conductive substrate. CONSTITUTION:An element formation layer 2 is provided on a conductive layer 4 or a conductive substrate through the intermediary of an insulating film 3. At this time, the element formation layer 2 is isolated in an insular shape and electrically connected to the conductive layer 4 or the conductive substrate. On the other hand, a conductive material (poly-Si) is buried in the gap between a polishing stopper layer (SiO2) 1 and the element formation layer 2 to provide a connection part for electrically connecting the layer 2 to the conductive layer 4 beneath the insulating film 3 to feed said layer 4 with a potential. Through these procedures, the element formation layer 2 can be fed with an arbitrary potential.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Examples Example of Oxidizing a Buried Conductive Film Example of Using Lift-off Selection Example using oxidationExample using etching maskExample using selective epitaxial methodEffects of the inventionFigure 1Figure 2Figure 3Figure 4Figure 5 5ol (Silicon on In5ul) having an element formation layer
ator) substrate and a method for manufacturing a semiconductor device using the same.

The purpose of this invention is to stably and precisely thin the element forming layer, prevent charge amplification of the element forming layer during the manufacturing process, and enable an arbitrary potential to be applied to the element forming layer.

1) Insulating film (3) on conductive layer (4) or conductive substrate
SO [substrate having an element formation layer (2) therebetween, the element formation layer (2) is separated into island shapes, and the conductive layer (
4) Or configured to be electrically connected to a conductive substrate.

2] Insulating film (3) on the conductive layer (4) or conductive substrate
A semiconductor device having an element forming layer (2) separated into island shapes via the conductive layer (
4) Or configured to be electrically connected to a conductive substrate.

3) The element forming layer (2) and the insulating film (3) have a groove reaching the conductive layer (4), the polishing stopper layer (1) or q4 is formed at the bottom of the groove, and the element forming layer (2)
A buried conductive layer (5) for electrically connecting the conductive layer (4) and the element forming layer (2) is provided in the gap between the polishing stopper layer (1) and the polishing stopper layer (1).

4) Forming a groove reaching the conductive layer (4) in the element forming layer (2) and the insulating film (3), and forming a polishing stopper layer (1) or (
14) and forming the element forming layer (2) in the gap between the element forming layer (2) and the polishing stopper layer (1).
) and a step of polishing the element forming layer (2) to a thickness defined by the polishing stopper layer (1). Configure.

[Industrial Field of Application] The present invention relates to a 5ol (Silicon on I
(n5lator) substrate and a method of manufacturing a semiconductor device using the same.

[Prior art] SOI having an element formation layer on a support substrate with an insulating film interposed therebetween
By forming an element using a substrate, it is possible to increase the speed of the element and reduce soft errors caused by radiation in the element.

Furthermore, since each element can be easily electrically isolated, C
It is also possible to prevent latch-up and reduce noise seen in MO5 and the like.

In order to enhance the above effects, it is necessary to make the element forming layer thinner.

Conventionally, as a method for thinning the element forming layer, the surface of the element forming layer has been polished by polishing.

In this case, since the variation in the thickness of the element forming layer becomes large, a groove is formed that reaches from the surface to the bottom of the element forming layer, and a polishing stopper layer of a desired thickness is formed in the groove, and then polishing is performed.

A method is used to increase the accuracy of the thickness of the element forming layer.

Furthermore, in order to obtain a uniform and highly accurate thin film.

After growing a polishing stopper layer in the groove, polishing is performed by filling the inside of the groove with a substance having approximately the same polishing rate as that of the element forming layer.

In addition, in a substrate with a conventional structure, since the element formation layer and the conductive layer or conductive substrate under the insulating film are electrically insulated, especially when the element formation layer becomes thin, when implanting ions into the element formation layer, The element forming layer acts as a charge amplifier, inhibiting injection, and the potential of each layer, which affects the element characteristics, must be applied independently to the element forming layer and the conductive layer under the insulating film. In particular, it has been difficult to apply an arbitrary potential to the element forming layer.

[Problem to be solved by the invention]

The object of the present invention is to stably and precisely thin an element forming layer, to prevent charge-up of the element forming layer during the manufacturing process, and to be able to apply an arbitrary potential to the element forming layer.

[Means for Solving the Problems] The above problems can be solved by using SO having an element formation layer (2) on a conductive layer (4) or a conductive substrate with an insulating film (3) interposed therebetween.
(1) A substrate, in which the element forming layer (2) is separated into islands and electrically connected to the conductive layer (4) or the conductive substrate. Alternatively, the element forming layer (2) is placed on the conductive substrate via the insulating film (3).
), in which the element formation layer (2) is separated into islands and electrically connected to the conductive layer (4) or the conductive substrate; The layer (2) and the insulating film (3) have a groove that reaches the conductive layer (4), and a polishing stopper layer (1) is provided at the bottom of the groove.
) or side is formed, and a buried conductive layer electrically connects the conductive layer (4) and the element formation layer (2) in the gap between the element formation layer (2) and the polishing stopper layer (1). (5
) or the element forming layer (2)
a step of forming a groove reaching the conductive layer (4) in the insulating film (3); a step of forming a polishing stopper layer (1) or (14) having a desired thickness at the bottom of the line groove; The element forming layer (2) and the polishing stopper layer (1)
) of forming a buried conductive layer (5) made of a substance with a polishing rate similar to that of the element forming layer (2);
) is achieved by a method for manufacturing a semiconductor device, which includes a step of polishing to a thickness specified by (a).

The SOI substrate according to claim 1, wherein a structure in which the element formation N (2) is electrically connected to the conductive layer (4) or the conductive substrate is formed at least in a dicing line region, or the polishing 3. The semiconductor device according to claim 2, wherein alignment marks for lithography are formed on the stopper layer (1) or on the polishing stopper layer (1), or by converting the buried conductive layer (5). This can also be achieved by the semiconductor device according to claim 2, which has an insulating film aω formed therein.

[Effect]

In the present invention, a conductive material is buried in the gap between the polishing stopper layer and the element forming layer, and a connection part is provided to electrically connect the element forming layer and the conductive layer under the insulating film. By applying a potential, an arbitrary potential can also be applied to the element formation layer.

As a result, during the manufacturing process, due to the presence of the connection portion, a charge-up phenomenon in the element forming layer during high-dose ion implantation can be prevented even if the element forming layer is made thin.

There is also a polishing stopper layer inside the groove at the same time.

By forming a connection region between the conductive layer under the insulating film and the element formation layer, the process steps can be shortened. Also,
This suppresses a decrease in the area of the element formation region on the support substrate.

In addition, by converting the conductive film in the connection part 5 into an insulating film after polishing, the interface of the element forming layer close to the polishing stopper layer is stabilized, and it is expected that element characteristics such as reduction in element leakage current will be improved. can.

Furthermore, the conductive film at one connection part is oxidized! ! When changing to an edge film, by oxidizing only the periphery of the arbitrary element forming layer, it is also possible to insulate the arbitrary element forming layer from the conductive layer under the insulating film.

Further, by forming the conductive film of the connection part along the dicing line, the polishing stopper layer can be formed widely and uniformly over the substrate surface, so that a more stable connection part can be formed.

In addition, by adding alignment marks used in the photolithography process to the polishing stopper layer, the polishing stopper layer remains even after polishing.
It becomes possible to precisely align the polishing stopper layer and each film formed after polishing.

[Example] Silicon dioxide (SiOz) with a thickness of 1 μm is placed on a conductive layer 4 made of p-type silicon (p-5i) with a resistivity of 10ΩC11l.
A 3 μm thick p-
An example in which the thickness of the element forming layer 2 made of 5i is 3000 layers is shown in FIGS. 1 to 4.

In addition, a conductive layer 4 made of p-Si with a resistivity of 10ΩCIl
On the top side, a substrate on which an element forming layer 2 made of p-3i with a thickness of 3000 nm is formed via an insulating film 3 made of SiO□ with a thickness of 1 μm is formed into an element forming layer using P-type epitaxial Si An example in which the conductive layer 2 and the conductive layer 4 are connected is shown in FIG.

FIGS. 1A to 1B are cross-sectional views of an embodiment in which the buried conductive film 5 at the connection portion is oxidized and the element formation region is surrounded by an insulating layer.

In FIG. 1(a), an element forming layer 2 is formed on a conductive layer 4 with an insulating film 3 interposed therebetween. A groove with a radius of 150 μm is formed to expose the conductive layer 4.

In Fig. 1('b), a 1.3 μm thick S layer was formed as a polishing stopper layer using the chemical vapor deposition (CVD) method.
An iO□ film 1 is grown.

Next, the SiO□ film is left only at the bottom portion away from the side wall of the trench by ordinary lithography and reactive ion etching (RIE) using fluorine-based gas, or wet etching.

Further, the 5iOz film 1 of the polishing stopper layer may be formed by growing polycrystalline silicon (poly-Si) and oxidizing it.

In FIG. 1(C), as a buried conductive film 5 that fills the gap (connection part) between the element forming layer 2 and the polishing stopper layer 1, a P-type poly-Si film with a resistance of Ω/hole is formed on the sheet resistance 1 by the CVO method. It grows to a thickness of about 2 μm.

In FIG. 1(d), Si of the polishing stopper layer is
The element forming layer 2 is polished using the O□ film 1 as a stopper.

As a result, the thickness of the element formation layer 2 is determined by the thickness of the polysingest layer 1 and becomes 3000 layers.

Furthermore, by forming the polishing stopper layer 1 on the dicing line, the polishing stopper layer 1 can be uniformly disposed over the entire surface of the wafer, thereby making it possible to stably and accurately reduce the thickness of the polishing stopper layer 1.

Using the substrate obtained as described above, elements are formed by a normal wafer process.

Here, an element can be formed in a state where the conductive layer 4 and the element formation layer 2 are electrically connected through the buried conductive film 5.

Furthermore, as an example of element formation, a case will be described in which the buried conductive film 5 is oxidized and a part thereof is changed into an insulating film 10 in FIG. 1 (el).

In FIG. 1(e), a MOS FET is formed by two normal MOS FET manufacturing steps.

In the figure, 6 is a gate electrode, which is a poly-Si film, 7 is a gate oxide film, which is a thermally oxidized SiO□ film, 8 is an impurity-introduced layer (source region), 9 is an impurity-introduced layer (drain region), and 10 is an insulating film. This is a film obtained by thermally oxidizing a part of the buried conductive film 5.

Next, part 111D (f )((to) will be used to explain.

By doing so, the potential of each element forming layer can be changed.

For example, when a substrate with such a structure is applied to CMO5, different potentials can be applied to the P channel side and the n channel side, and the threshold voltage of the MOS FET can be changed to n
Channel and n-channel can be controlled independently.

In Fig. 1(d), after the element formation layer 2 is thinned as shown in Fig. 1(d), a layer of S of 1000 layers is deposited on two substrates.
An iN film 17 is grown, and an opening is made using lithography around the element forming layer that is to be insulated from the conductive layer under the insulating film. The etching at this time is carried out by dry etching using fluorine gas.

In FIG. 1, a 5iOz film 18 with a thickness of 6000 nm is formed by thermal oxidation using the SiN film 17 as a mask.

Thereafter, the SiN film 17 is removed by wet etching.

The region covered with the SiN film 17 is not oxidized, and the conductive layer under the insulating film and the element forming layer remain electrically insulated.

Through the above steps, the conductive layer under the insulating film and any element forming layer can be electrically connected.

FIGS. 2(a) to 2(d) are cross-sectional views of an embodiment in which the Bolinsingest flange layer 1 is formed by resist lift-off.

In FIG. 2(a), an element forming layer 2 is formed on a conductive layer 4 via an insulating film 3, and grooves are formed by dry etching using a chlorine-based gas or wet etching by a normal glue-grazing process. Then, the conductive layer 4 is exposed.

In FIG. 2), a resist film 11 is formed by lithography on the entire surface of the substrate, leaving only the groove bottoms. Also,
Instead of the resist film 11, phosphosilicate glass (PSG)
During etching for lifting off the polishing stopper layer 1, a film made of a material having a high selectivity with respect to the Bolinsingest rim layer may be used.

In Fig. 2(C), a 1.3 μm thick Bolinsingest collar layer is formed on the entire surface of the substrate by anisotropic sputtering.
5iOz film is formed.

The formation method may be any method other than anisotropic sputtering as long as the polishing stopper layer is not formed on the sidewalls of the grooves in the element forming layer 2 and the insulating film 3.

Thereafter, the resist film 11 is removed to lift off the bolting guest flange layer on the resist, and the bolting guest flange layer 1 is formed only on the groove bottom.

As a method for removing the resist film, wet processing using an aqueous solution of sulfuric acid can reduce the influence of dust generated by lift-off better than dry processing.

In FIG. 2(d), as a buried conductive film 5 that fills the gap (connection part) between the element forming layer 2 and the polishing stopper layer 1, a P-type Bo'JSi layer with a sheet resistance of IKΩ/hole is formed to a thickness of It grows about 2 μm in height.

Next, the SiO□ film 1 of the Bolinsingest rim layer is
- Polish the element forming layer 2 as a buckwheat polisher.

As a result, the thickness of the element forming N2 is
The number of people is determined by the thickness of the 3,000 people.

Using the substrate formed as described above, for example, FIG.
) Element formation is performed in the same manner.

3(a) to 3(d) are cross-sectional views of an embodiment in which the polishing stopper layer 1 is formed by a selective oxidation method.

In FIG. 3(a), an element forming layer 2 is formed on a conductive layer 4 with an insulating film 3 interposed therebetween, and grooves are formed by dry etching using a chlorine-based gas or wet etching by a normal glue-on-etching process. Then, the conductive layer 4 is exposed.

In Fig. 3(b), a P-type poly-Si film of about 6,500 ohms per ohm is grown on the sheet resistor 3, which will become the buried conductive film 5, by CVD, and then a nitrided film of 1,500 ohms is deposited on top of it. A silicon (SiN) film 13 is grown.

Next, 1. RI using normal lithography and fluorine gas.
The SiN film 13 is removed only from the bottom portion away from the sidewalls of the trench by etching.

Next, the poly-Si film 5 is thermally oxidized to form a SiO□ film with a thickness of 1.3 μm, which will become the Bolinsingest flange layer 1.

In FIG. 3(C), after removing the SiN film 13 with hot phosphoric acid or the like, the gap (connection part) between the element forming layer 2 and the Bolinsingest flange layer 1 is filled, and a sheet resistance 3 of Ω is applied to the entire surface of the substrate. The thickness of the p-type poly-Si film 12 is 1 to 2 μm.
It takes about m.

In FIG. 3(d), the element forming layer 2 is polished using the Bolinsinges layer 1 as a stopper.

As a result, the thickness of the element forming layer 2 is determined by the thickness of the polishing stopper layer 1 and becomes 3000 layers.

Using the substrate formed as described above, for example, FIG.
) Element formation is performed in the same manner.

FIGS. 4(a) to 4(d) are cross-sectional views of an embodiment in which an SiN film 14 is used as a polishing stopper layer and the insulating film 3 is etched using this as a mask.

In FIG. 4(a), an element forming layer 2 is formed on a conductive layer 4 through an insulating film 3, and then the element forming layer 2 is etched by a normal glue-on-glue drying process, dry etching using a chlorine gas, or wet etching. 2 to form a groove and expose the insulating film 3.

In Fig. 4(b), a thickness of 300 mm was obtained by the CVD method.
After growing the SiN film 1, the SiN film 14 is formed only on the bottom part away from the sidewalls of the trench by normal lamination and dry etching using chlorine-based gas or wet etching using phosphoric acid or the like. .

Here, the SiN film 14 functions as a poly/singest rim layer, and also serves as a mask when etching and etching the insulating film 3.

Next, using the SiN film 14 as a mask, the insulating film 3 is etched by dry etching, etching, or wet etching using a fluorine gas to form a groove and expose the conductive layer 4.

In FIG. 4(C), a p-type polyS of Ω/hole is deposited on the sheet resistance 1 which becomes the buried conductive film 5 on the entire surface of the substrate by the CVD method.
An i-film is grown to a thickness of about 2 μm.

In FIG. 4(d), the element forming layer 2 is polished by using the SiN film 14, which will become a single polygonal thin film layer, as a stopper.

As a result, the thickness of the element forming layer 2 is determined by the thickness of the polishing stopper layer 1 and becomes 3000 layers.

Using the substrate formed as described above, for example, as shown in FIG.
) Element formation is performed in the same manner.

Figures 5 (a) and (b) are obtained using the selective epitaxial method.

FIG. 2 is a cross-sectional view of an example in which an element forming layer 2 and a conductive layer 4 are electrically connected.

In FIG. 5(a), an element forming layer 2 and a 5iOz film 16 serving as a growth mask are formed on a conductive layer 4 via an insulating film 3, and then dry etching is performed using a normal adhesive film drying process and a fluorine-based gas. , or the 5iOz film 16 is etched by wet etching, then the element formation layer 2 is etched by dry etching using a fluorine gas or wet etching, and then the insulation is etched by dry etching using a fluorine gas or wet etching. The film 3 is etched to form a groove and the conductive layer 4 is etched.
expose.

In FIG. 5(b), an epitaxial Si layer 15 with a thickness of 3000 μm and a sheet resistance of IKΩ/hole is grown in the trench by selective epitaxial method as a buried conductive film in the connection portion, and then fluorine-based wet etching is performed. By giO□
Remove membrane 16.

Using the substrate formed as described above, for example, as shown in FIG.
) Element formation is performed in the same manner.

In the example, a SiO□ film was used as the polishing stopper layer,
Although the SiN film is used, any material may be used as long as it has a high polishing selectivity with respect to the element forming layer 2. For example, PSG film,
A TiO film may also be used.

Further, in the embodiment, a poly S1 film was used as the buried conductive film, but a material having a polishing rate similar to that of Si and having conductivity may also be used. For example, single crystal Si, sputtered Si, or SiC may be used.

[Effects of the Invention] As explained above, the present invention has the following effects.

■ By applying a potential to the conductive layer under the insulating film.

A potential can also be applied to the element formation layer.

(2) Even when a potential is applied to the element formation layer, the reduction in the element formation area relative to the substrate area can be suppressed.

(2) By forming the connection region between the conductive layer under the insulating film and the element forming layer at the same time as the polishing stopper layer, the process can be shortened.

■ Even if the element formation layer is made thinner, charge-up during high-dose ion implantation can be prevented.

■ Z By converting the buried conductive film formed in the gap between the polishing stopper layer and the element formation layer into an insulating film after polishing, the interface between the element formation layer near the polishing stopper layer is stabilized, and the leakage current of the element is reduced. It can be expected that the characteristics will be improved, such as the reduction of

(2) When converting the buried conductive film into an insulating film by oxidizing it after polishing, by oxidizing only the periphery of a given element forming layer, it is possible to insulate the given element forming layer from the conductive layer under the insulating film.

(2) By forming the buried conductive film at the connection part along the dicing line, a polishing stopper layer can be formed widely and uniformly on the substrate surface, making it possible to form a more stable electrical connection.

■ By placing alignment marks used in the photolithography process on the polishing stopper layer, the polishing stopper layer remains after polishing, making it possible to accurately align the polishing stopper layer with each layer formed after polishing. .

[Brief explanation of drawings]

Figures 1(a) to (dark) are cross-sectional views of an embodiment in which the buried conductive film 5 at the connection portion is oxidized and the element formation area is surrounded by an insulating layer. Figures 2(a) to (d) are polishing stoppers. 3(a) to 3(d) are sectional views of an embodiment in which the layer 1 is formed by resist lift-off. d) is a cross-sectional view of an embodiment in which the SiN film 14 is used as a polishing stopper layer and the insulating film 3 is etched using this as a mask; FIGS. 5(a) and 5(b) are by selective epitaxial method. 2 is a cross-sectional view of an embodiment in which 2 and a conductive layer 4 are electrically connected. In the figure, 1 is a polishing stopper layer, the SiO2 film 2 is an element forming layer, 3 is an insulating film 4 is a conductive layer, and 5 is a connecting portion. The buried conductive film is a poly-Si film. 6 is the gate electrode, which is a poly-Si film. 7 is the gate oxide film, thermally oxidized 5i (14 film 8 is an impurity-introduced layer (source region), 9 is an impurity-introduced layer (drain region). 10 Insulating film II is a resist film obtained by thermally oxidizing a part of the buried conductive film. 12 is a poly-Si film. 13 is an oxidation-resistant mask and SiN film. 14 is a polishing stopper layer, and SiN film 15 is a buried conductive film at the connection part Epitaxial Si layer in the film. 16 is the growth mask and the l! 1-2) Cross-sectional view of Fu collaboration (2) Figure 2 First view of Daigu example (3) Figure 1 upper 41 Pano (Ma layer (Sin) Dai example @) ,') llt'Fi ′ side view

Claims (1)

[Scope of Claims] [1] An insulating film (3) on a conductive layer (4) or a conductive substrate
), the element forming layer (2) is separated into islands and is electrically connected to the conductive layer (4) or the conductive substrate. An SOI substrate characterized by: [2] Insulating film (3) on the conductive layer (4) or conductive substrate
), wherein the element forming layer (2) is separated into island shapes and electrically connected to the conductive layer (4) or the conductive substrate. A semiconductor device characterized by: [3] The element formation layer (2) and the insulating film (3) have a groove that reaches the conductive layer (4), the polishing stopper layer (1) or (14) is formed at the bottom of the groove, and the element In the gap between the forming layer (2) and the polishing stopper layer (1),
A semiconductor device characterized by having a buried conductive layer (5) electrically connecting the conductive layer (4) and the element formation layer (2). [4] Forming a groove reaching the conductive layer (4) in the element forming layer (2) and the insulating film (3), and forming a polishing stopper layer (1) having a desired thickness at the bottom of the groove; or (14), and a buried conductive layer (5) made of a material having a polishing rate similar to that of the element forming layer (2) in the gap between the element forming layer (2) and the polishing stopper layer (1). a step of forming the element forming layer (2) into the polishing stopper layer (1);
1. A method for manufacturing a semiconductor device, comprising the step of polishing to a thickness defined by . [5] The SOI according to claim 1, wherein a structure in which the element forming layer (2) is electrically connected to the conductive layer (4) or the conductive substrate is formed at least in a dicing line region. substrate. [6] The semiconductor device according to claim 2, wherein alignment marks for lithography are formed in or on the polishing stopper layer (1). [7] Insulating film formed by converting the buried conductive layer (5)
10). The semiconductor device according to claim 2, further comprising: 10).