JPH03250628A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03250628A JPH03250628A JP2045389A JP4538990A JPH03250628A JP H03250628 A JPH03250628 A JP H03250628A JP 2045389 A JP2045389 A JP 2045389A JP 4538990 A JP4538990 A JP 4538990A JP H03250628 A JPH03250628 A JP H03250628A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- base
- interconnection
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical class [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 abstract description 9
- 230000001070 adhesive effect Effects 0.000 abstract description 6
- 238000009792 diffusion process Methods 0.000 abstract description 6
- 239000000853 adhesive Substances 0.000 abstract description 5
- 239000000463 material Substances 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 239000010931 gold Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 229910052745 lead Inorganic materials 0.000 description 3
- 229910052718 tin Inorganic materials 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- XZXYQEHISUMZAT-UHFFFAOYSA-N 2-[(2-hydroxy-5-methylphenyl)methyl]-4-methylphenol Chemical compound CC1=CC=C(O)C(CC=2C(=CC=C(C)C=2)O)=C1 XZXYQEHISUMZAT-UHFFFAOYSA-N 0.000 description 1
- ZCYVEMRRCGMTRW-UHFFFAOYSA-N 7553-56-2 Chemical compound [I] ZCYVEMRRCGMTRW-UHFFFAOYSA-N 0.000 description 1
- 241001319955 Unda Species 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229940107816 ammonium iodide Drugs 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 235000009508 confectionery Nutrition 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052740 iodine Inorganic materials 0.000 description 1
- 239000011630 iodine Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
不発明は半導体装置、特に、その突起電極の電極下地に
関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device, and particularly to an electrode base of a protruding electrode thereof.
フリップチップ方式やテープキャリア方式などの接続方
式において、半導体チップとセラミック基板や樹脂基板
などの配線基板などとのボンディングに、その接続端子
として突起電極が使用される。In connection methods such as the flip chip method and the tape carrier method, protruding electrodes are used as connection terminals for bonding a semiconductor chip and a wiring board such as a ceramic substrate or a resin substrate.
当該突起電極の形成プロセスの一例は、内部配線を形成
したウェハに、電気絶縁膜を被債し、ホトレジスト技術
でIEf!jL用窓を開孔し、多層金属で電極下地を形
成し、七の[ffl下地の上に、ハンダバンプなとより
なる突起電極を形成する。An example of the process for forming the protruding electrodes is to apply an electrical insulating film to a wafer on which internal wiring has been formed, and to apply IEf! using photoresist technology. A window for jL is opened, an electrode base is formed using a multilayer metal, and a protruding electrode such as a solder bump is formed on the seventh [ffl base].
この突起電極を有するチップは、コンドロールドコラッ
プス・ボンディング(CCB )として知られている。A chip having this protruding electrode is known as chondral collapse bonding (CCB).
丁なわち、この突起!fflの形成に際しては、電極下
地を介在させて設置するようになっており、一般に、前
述のように当該電極下地には多層金属が用いられている
。Ding, that is, this protrusion! When ffl is formed, it is installed with an electrode base interposed therebetween, and generally, as described above, a multilayer metal is used for the electrode base.
このバンプの下地金mli(BLM)には各種の組合せ
が使用されてし・る。Cr/Cu/Au。Various combinations are used for the base metal mli (BLM) of this bump. Cr/Cu/Au.
T i /Cu /A uなどの組合せが例示される。Examples include combinations such as T i /Cu /Au.
尚、突起*極やその電極下地につ(・て述べた文献の例
としては、(株)工業調査会1980年1月15日発行
rIC化実装技術J pi 75及びp84が挙げられ
る。Incidentally, an example of a document that describes protrusions*poles and their electrode bases is RIC Mounting Technology J pi 75 and p 84 published by Kogyo Kenkyukai Co., Ltd. on January 15, 1980.
しかるに、従来の多層金属による電極下地例えばCr
/ Cu / A uよりなる電極下地では、そのBL
Mの最下層のCr膜は、前述型気絶l#膜および内部配
線と接して、当該内部配線とCu、Au。However, conventional multilayer metal electrode bases such as Cr
/Cu/Au, the BL
The lowermost Cr film of M is in contact with the above-mentioned type stunned l# film and the internal wiring, and is in contact with the internal wiring and Cu, Au.
ハンダバンプとの間の拡散を防止するいわゆるバリヤメ
タルとしての掲能並びに電気e縁膜に対する接着用金属
としての機能な果丁べきところ、そのバリヤメタル、接
着層としての効果を必すしも元分果たしているとはいえ
ず、電気的接続の信頼性確保という面では未だ問題があ
る。特に、ウェハ基板表面が高段差構造となってし・る
場合には、当該最下層の金属膜の段差抜機性(カバレジ
)が劣イヒし、バリヤー性、接着性の点で増々問題を犬
きくしている。It functions as a so-called barrier metal to prevent diffusion between the solder bumps and as an adhesive metal for the electrical film, and it is believed that the barrier metal and adhesive layer must play a major role. However, there are still problems in ensuring the reliability of electrical connections. In particular, when the wafer substrate surface has a high-step structure, the step-cutting ability (coverage) of the metal film at the bottom layer becomes poor, and problems with barrier properties and adhesion are increasingly caused. ing.
本発明はかかる従来技術の有する欠点を解消することの
できる技術を提供するごとを目的としたものである。It is an object of the present invention to provide a technique that can eliminate the drawbacks of the prior art.
本発明の前記ならびにそのほかの目的と新規な特徴は、
不明細書の記述および添付図面からおきろかになるであ
ろう。The above and other objects and novel features of the present invention include:
This can be determined from the description in the unknown specification and the attached drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明丁れば、下記のとおりである。A brief summary of typical inventions disclosed in this application is as follows.
本発明ではYLI下地に窒化チタン(TiN)膜を用(
・、特に、電気kb縁膜と内部配線に接するその最下層
に、しかも、化学的気相成長法(CVD法)により成膜
したTiNjdを用(・た。In the present invention, a titanium nitride (TiN) film is used as the YLI base (
In particular, TiNjd, which was formed by chemical vapor deposition (CVD), was used in the lowermost layer in contact with the electrical kb edge film and the internal wiring.
上記TiN膜は、従来の最下j−金金属して使用されて
いるCrなどに比して、内部配線とノ・ンダバンブなど
との拡散防止作用に優i−1,、牙だ、電気絶縁膜や内
部配線との接着性にも優i1てし・るので。The TiN film mentioned above has a superior effect of preventing diffusion between internal wiring and non-conducting metals, compared to Cr, which is used as the conventional lowermost gold metal. It also has excellent adhesion to membranes and internal wiring.
突起電極の電気的接続寿命が向上し、半導体装置の信頼
性を向上させることができる。The electrical connection life of the protruding electrode is improved, and the reliability of the semiconductor device can be improved.
また、TiN膜の形成をCVD法により行うことにより
1段差液種性にも優れ、上記バリヤー性や接着性を増々
優れたものにすることができる。Furthermore, by forming the TiN film by the CVD method, it has excellent one-step liquid type properties, and the barrier properties and adhesive properties described above can be further improved.
以下1本発明の一実施例を第1図により説明する。同図
では1回路素子(図示せず)を倉む半導体基板10上に
S iO,から成る絶縁膜20を介してアルミニウム導
体配線路(内部配線)30が形成され、さらに表面保護
絶縁層(電気絶縁層)40が形成されている。これらは
辰知の半導体製造技術により作成されたものである。さ
らに、該絶縁層40にコンタクト孔([極窓)を設け、
次り・でTiNg51を厚さ0.1 μm、 CuP
X52を厚さ1μm、Au膜53を厚さ0.2μm順次
積層した構造から成る積層下地層50を堆積、加工した
後。An embodiment of the present invention will be described below with reference to FIG. In the figure, an aluminum conductor wiring path (internal wiring) 30 is formed on a semiconductor substrate 10 holding one circuit element (not shown) through an insulating film 20 made of SiO, and a surface protective insulating layer (electrical An insulating layer) 40 is formed. These were created using Tatsuchi's semiconductor manufacturing technology. Furthermore, a contact hole ([polar window]) is provided in the insulating layer 40,
Next, TiNg51 with a thickness of 0.1 μm and CuP
After depositing and processing a laminated base layer 50 having a structure in which X52 is laminated to a thickness of 1 μm and an Au film 53 is laminated to a thickness of 0.2 μm.
Pb61と5n62とから成る高さ80μmのハンダバ
ンプ60を設けるつ積層下地層50およびハンダバンプ
60は以下のように形成した。即ち。The laminated base layer 50 and the solder bumps 60 were formed as follows, while providing the solder bumps 60 made of Pb61 and 5n62 and having a height of 80 μm. That is.
先ず、絶縁膜40にコンタクト孔を設けた半導体基板1
0上にTiN膜51を化学的気相成長法により堆積した
つこのTiN膜51は、基板温度400℃でT + C
l t (108CCM )とNH,(700scch
i+を反応ガスとして0.3〜0.4 To r r
に保ちプラズマ放電中で堆積さセたもσ)でおる。First, a semiconductor substrate 1 with contact holes provided in an insulating film 40 is prepared.
The TiN film 51, which is deposited on top of the substrate by chemical vapor deposition, is T + C at a substrate temperature of 400°C.
lt (108CCM) and NH, (700scch
0.3 to 0.4 Tor r with i+ as the reaction gas
The particles deposited in the plasma discharge are kept at σ).
Cu膜52およびA Ll膜53は周知の抵抗加熱蒸着
法により堆積させた。こrら積層下地1−の加工は、通
常のホトレジスト処理によりレジストマスクを設けた後
、最上層のAll膜53および中間層のCu膜52を、
ヨワ素とヨウ化アンモン混合液による化学エツチングに
より加工した5甘た。The Cu film 52 and the ALl film 53 were deposited by a well-known resistance heating vapor deposition method. In processing the laminated base 1-, after providing a resist mask by ordinary photoresist processing, the uppermost Al film 53 and the intermediate Cu film 52 are processed.
5 Sweets processed by chemical etching with a mixture of iodine and ammonium iodide.
TiN膜はCF、プラズマエツチングに加工した。The TiN film was processed by CF and plasma etching.
さらに、ハンダバンプ60はリフトオフ法により形成し
た。これは、バンブな設置したい領綾を開孔したレジス
ト膜を形成し、た後、抵抗加熱蒸着法によりPbとSn
を順次堆積し、その債、レジスト溶解液中に浸漬し、レ
ジストおよびレジスト−にのハンダを除去することによ
り、ノ・ンダを形成したものであろっ
なお2通常は第1図に示す基飯をその後PbとSnの融
点以上の聾度に加熱し、PbとSni溶解させる。Furthermore, the solder bumps 60 were formed by a lift-off method. This is done by forming a resist film with holes in the areas where bumpy installation is desired, and then using a resistance heating evaporation method to deposit Pb and Sn.
The solder is formed by sequentially depositing the bond, immersing it in a resist solution, and removing the resist and the solder on the resist. is then heated to a level above the melting points of Pb and Sn to dissolve Pb and Sn.
本実施例によれば、丁1N膜51を採用したことにより
、内部配線30および電気絶縁層40などの下地材料と
の接着力が強く、かつ、内部配線:うOとハンダバンブ
60、Cu膜52.Au膜53などとの相互拡散の少な
い突起x′f!iL、 *愼下地が実現でき、電気的接
続の信頼性向上の効果があり、また、TiN膜51の形
成をCVD法により行ったので、段差Wt覆性に優れ、
より−1−上記接着力を向上させ、かつ、相互拡散防止
上有利とすることができた。According to this embodiment, by employing the 1N film 51, the adhesion to the internal wiring 30 and the underlying material such as the electrical insulating layer 40 is strong, and the internal wiring: the solder bump 60, the Cu film 52 .. Protrusions x′f with little interdiffusion with the Au film 53, etc.! iL, *It is possible to realize a solid base, which has the effect of improving the reliability of electrical connection, and since the formation of the TiN film 51 was carried out by the CVD method, it has excellent step Wt covering properties,
-1- It was possible to improve the above-mentioned adhesive force and to make it advantageous in terms of preventing mutual diffusion.
以上本発明者によってなされγこ発明を実施例にもとづ
き具体的に説明したが1本発明は上記実施例に限定され
るものではなく、その要旨を逸脱しなし・範囲で種々f
更oJ能であることはいうプでもな(・。Although the present invention made by the present inventor has been specifically explained based on Examples, the present invention is not limited to the above-mentioned Examples, and may be modified in various ways without departing from the gist thereof.
There's no need to say that it's OJ Noh (・.
本発明による突起成極の電極下地は、フリップチップや
テープキャリア用テップなとの各檜分野の突起成極に適
用することができる。The electrode base for protrusion polarization according to the present invention can be applied to protrusion polarization in various fields such as flip chips and tape carrier tips.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明丁れば、下記のとおりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
本発明によれば、下地材料との接着力が強く。According to the present invention, the adhesive force with the base material is strong.
また、下地内部配線との相互拡散が防止され1wi気的
接続寿命が改善され、半導体装置の信頼性を向上させる
ことができる。In addition, mutual diffusion with the underlying internal wiring is prevented, the 1wi connection life is improved, and the reliability of the semiconductor device can be improved.
第1図は本発明の実施例を適用した半導体装置の概略部
分断面図である。
10・・・半導体基数、20・・・絶縁膜、30・・・
内部配繰、40・・・電気絶縁膜(表面保換絶縁膜)、
50・・・下地層、51・・・TiN膜、52・・・C
u膜。
53・・・Au膜、60・・・突起電極()・ンダバン
プ)、fi I −P b%62−8 n0FIG. 1 is a schematic partial sectional view of a semiconductor device to which an embodiment of the present invention is applied. 10... Number of semiconductor bases, 20... Insulating film, 30...
Internal arrangement, 40... electrical insulation film (surface storage insulation film),
50... Base layer, 51... TiN film, 52... C
u membrane. 53...Au film, 60...Protruding electrode ()/unda bump), fi I -P b%62-8 n0
Claims (1)
に突起電極形成用電極窓が孔設され、当該電極窓に、突
起電極の下地となる多層構造の下地層が形成され、当該
多層構造の下地層を介して突起電極を形成してなる半導
体装置において、前記多層構造の下地層の少なくとも1
層が窒化チタン膜により構成されて成ることを特徴とす
る半導体装置。 2、窒化チタン膜が、電気絶縁膜および内部配線と接す
る最下層に位置し、かつ、その膜形成が気相中の化学反
応による膜形成方法である化学的気相成長法により行わ
れる、請求項1に記載の半導体装置。[Scope of Claims] 1. An electrode window for forming a protruding electrode is provided in the electrical insulating film on the surface of the semiconductor substrate on which internal wiring is formed, and a base layer of a multilayer structure serving as a base for the protruding electrode is provided in the electrode window. In a semiconductor device in which a protruding electrode is formed through a base layer of the multilayer structure, at least one of the base layers of the multilayer structure
A semiconductor device characterized in that the layer is composed of a titanium nitride film. 2. A claim in which the titanium nitride film is located at the bottom layer in contact with the electrical insulating film and the internal wiring, and the film is formed by chemical vapor deposition, which is a film formation method using chemical reactions in the gas phase. Item 1. The semiconductor device according to item 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2045389A JPH03250628A (en) | 1990-02-28 | 1990-02-28 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2045389A JPH03250628A (en) | 1990-02-28 | 1990-02-28 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03250628A true JPH03250628A (en) | 1991-11-08 |
Family
ID=12717915
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2045389A Pending JPH03250628A (en) | 1990-02-28 | 1990-02-28 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03250628A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5834844A (en) * | 1995-03-24 | 1998-11-10 | Shinko Electric Industries Co., Ltd. | Semiconductor device having an element with circuit pattern thereon |
US5903058A (en) * | 1996-07-17 | 1999-05-11 | Micron Technology, Inc. | Conductive bumps on die for flip chip application |
US6008543A (en) * | 1995-03-09 | 1999-12-28 | Sony Corporation | Conductive bumps on pads for flip chip application |
US6400018B2 (en) * | 1998-08-27 | 2002-06-04 | 3M Innovative Properties Company | Via plug adapter |
-
1990
- 1990-02-28 JP JP2045389A patent/JPH03250628A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6008543A (en) * | 1995-03-09 | 1999-12-28 | Sony Corporation | Conductive bumps on pads for flip chip application |
US5834844A (en) * | 1995-03-24 | 1998-11-10 | Shinko Electric Industries Co., Ltd. | Semiconductor device having an element with circuit pattern thereon |
US5960308A (en) * | 1995-03-24 | 1999-09-28 | Shinko Electric Industries Co. Ltd. | Process for making a chip sized semiconductor device |
US5903058A (en) * | 1996-07-17 | 1999-05-11 | Micron Technology, Inc. | Conductive bumps on die for flip chip application |
US6400018B2 (en) * | 1998-08-27 | 2002-06-04 | 3M Innovative Properties Company | Via plug adapter |
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