JPH03248527A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03248527A JPH03248527A JP4880390A JP4880390A JPH03248527A JP H03248527 A JPH03248527 A JP H03248527A JP 4880390 A JP4880390 A JP 4880390A JP 4880390 A JP4880390 A JP 4880390A JP H03248527 A JPH03248527 A JP H03248527A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- insulating film
- metal
- film
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 78
- 239000002184 metal Substances 0.000 claims abstract description 78
- 238000000034 method Methods 0.000 claims abstract description 48
- 238000005530 etching Methods 0.000 claims abstract description 13
- 150000002739 metals Chemical class 0.000 claims abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 9
- 239000011229 interlayer Substances 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 6
- 230000008961 swelling Effects 0.000 claims description 3
- 239000007769 metal material Substances 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 17
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置における多層配線の形成に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to the formation of multilayer wiring in semiconductor devices.
多くの素子を持つＩＣ等の半導体装置は、素子間の配線
数が多いので、配線を多層化する必要がある。この多層
配線構造は、第２図に示すように、素子（１）が形成さ
れ、表面に薄い酸化絶縁膜（２）が形成された半導体基
板（３）に対して、この酸化絶縁膜（２）の素子対応位
置を窓開けした後、アルミ等の金属配線（４）と絶縁層
（５）を交互に積層したもので、各層の金属配線（４）
は絶縁層（５）の所定位置に設けたスルーホール（６）
により必要なもの同士で上下に接続されている。2. Description of the Related Art Semiconductor devices such as ICs having many elements have a large number of interconnects between the elements, so it is necessary to have multiple layers of interconnects. As shown in FIG. 2, this multilayer wiring structure consists of a semiconductor substrate (3) on which an element (1) is formed and a thin oxide insulating film (2) formed on the surface thereof. ) after opening a window at the element corresponding position, metal wiring (4) such as aluminum and insulation layer (5) are laminated alternately, and the metal wiring (4) of each layer is
is a through hole (6) provided at a predetermined position in the insulating layer (5)
The necessary items are connected vertically.
この多層配線の形成方法を、より具体的に説明する。初
めに第３図（ａ）に示すように、薄い酸化絶縁膜（２）
が窓開けされた半導体基板（３）に対して金属膜（４ａ
）を全面被着した後、金属配線（４）として必要な部分
にフォトレジスト膜（７）を形成してエツチングを行い
、不要な金属膜（４ａ）を取り除く。次に、第３図ら）
に示すように絶縁膜（５）を全面被着し、さらに絶縁膜
（５）の所定部分にスルーホール（６）を窓開けして、
この上に形成される金属配線（４）が下側の金属配線（
４）に接続されるようにする。以後金属配線（４）と絶
縁膜（５）の形成を繰り返す。The method for forming this multilayer wiring will be explained in more detail. First, as shown in Figure 3(a), a thin oxide insulating film (2) is
The metal film (4a
) is deposited on the entire surface, a photoresist film (7) is formed on the part required as the metal wiring (4) and etched to remove unnecessary metal film (4a). Next, Figure 3 et al.)
As shown in the figure, an insulating film (5) is deposited on the entire surface, and through holes (6) are opened in predetermined parts of the insulating film (5).
The metal wiring (4) formed on this is the lower metal wiring (
4). Thereafter, the formation of metal wiring (4) and insulating film (5) is repeated.
上記従来の多層配線構造では、突出した形状の金属配線
（４）の上に絶縁膜形成材を気相成長して絶縁膜（５）
を形成し、その上に金属配線（４）を形成しているので
、絶縁膜（５）の角にこの金属配線形成材が着き難く、
金属配線（４）のこの部分が薄くなり、ここで切れてし
まうこともある、このような段切れ（ステップカバレッ
ジ）は、金属配線（４）の多層化が進む程に、高低差が
大きくなって発生し易く、製品の歩留まり並びに信鯨性
を低下させていた。このため、気相成長で各絶縁膜（５
）を形成後、泥しよう状の絶縁膜形成材をスピンナ塗布
して、段差の解消を図っているが、作業に手間がかかる
。In the conventional multilayer wiring structure described above, an insulating film forming material is vapor-phase grown on the protruding metal wiring (4) to form an insulating film (5).
is formed, and the metal wiring (4) is formed thereon, so that this metal wiring forming material is difficult to adhere to the corners of the insulating film (5).
This part of the metal wiring (4) becomes thinner and may break at this point.This kind of step coverage (step coverage) occurs as the height difference becomes larger as the metal wiring (4) becomes more multi-layered. This tends to occur, reducing product yield and reliability. For this reason, each insulating film (5
), a slurry-like insulating film-forming material is applied using a spinner to eliminate the level difference, but this process is time-consuming.
また上記従来の多層配線方法では、各層の金属配線（４
）を形成する毎に、その周囲の不要金属膜（４ａ）をエ
ツチング除去する必要がある。このため、エツチングの
困難な金属は、特性が優れていても使用できず、配線に
使用できる金属の種類が制限されるという問題もあった
。Furthermore, in the conventional multilayer wiring method described above, each layer of metal wiring (4
) is formed, it is necessary to remove the unnecessary metal film (4a) around it by etching. For this reason, metals that are difficult to etch cannot be used even if they have excellent properties, and there is a problem in that the types of metals that can be used for wiring are limited.
そこで、本発明は金属配線の段切れがなく、金属配線を
エツチングによらないで形成できる半導体装置の製造方
法を提供することを目的とする。SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a method for manufacturing a semiconductor device in which there is no step break in the metal wiring and the metal wiring can be formed without using etching.
本発明が提供する半導体装置の製造方法は、素子が形成
された半導体基板の上に絶縁膜を形成し、これを平坦化
処理した後に、
フォトレジスト膜を被着形成し、所定部分を窓開けする
工程、この窓を通してエツチングを行い絶縁膜に貫通孔
を形成する工程、金属膜を前記絶縁膜の貫通孔を埋める
厚さで全面に被着形成する工程、このフォトレジスト膜
を薬剤により膨潤させてその上に被着した金属膜ととも
に剥離する工程からなるリフトオフ法によって、
上記平坦な絶縁膜の貫通孔内に、金属膜の一部を埋め残
して下端が素子電極に接続された上下接続金属を形成す
る第１の配線処理を行い、配線間絶縁膜を全面被着した
後に、この配線間絶縁膜に形成した貫通孔内に、リフト
オフ法によって、金属膜の一部を埋め残して下面の一部
が上下接続金属に接続された金属配線を形成する第２の
配線処理を行い、
次に、層間絶縁膜を全面被着した後に、この層間絶縁膜
に形成した貫通孔内に、リフトオフ法によって、金属膜
の一部を埋め残して下端が配線に接続された上下接続金
属を形成する第３の配線処理を行い、
この後、上記第２の配線処理と第３の配線処理を交互に
繰り返して、上層と下層の金属配線が上下接続金属によ
って接続された多層配線を形成することを特徴とする。The method of manufacturing a semiconductor device provided by the present invention includes forming an insulating film on a semiconductor substrate on which an element is formed, flattening the insulating film, depositing a photoresist film, and opening a window in a predetermined portion. a step of etching through this window to form a through hole in the insulating film; a step of depositing a metal film on the entire surface to a thickness that fills the through hole of the insulating film; and a step of swelling this photoresist film with a chemical. By using the lift-off method, which involves peeling off the metal film along with the metal film deposited on the flat insulating film, a part of the metal film is left buried in the through hole of the flat insulating film, and the upper and lower connecting metals are connected to the element electrodes at the lower ends. After performing a first wiring process to form a metal film and depositing an inter-wiring insulating film on the entire surface, a lift-off method is used to leave a part of the metal film unfilled in the through-hole formed in the inter-wiring insulating film and deposit the metal film on the bottom surface. A second wiring process is performed to form a metal wiring part of which is connected to the upper and lower connection metals, and then an interlayer insulating film is deposited on the entire surface, and then a lift-off method is applied to the through hole formed in the interlayer insulating film. A third wiring process is performed to form upper and lower connection metals whose lower ends are connected to the wiring by leaving a part of the metal film unfilled. After this, the second wiring process and the third wiring process are alternately performed. The method is characterized in that a multilayer wiring is formed in which upper and lower layer metal wirings are connected by upper and lower connection metals by repeating the process.
上記半導体装置の製造方法によれば、初めに最下層の絶
縁膜の平坦化を行った後に、上下接続金属と金属配線を
、これと同一高さの絶縁膜の貫通孔に埋めながら積層し
て多層配線を形成するので、各層が全て平坦になり段切
れの恐れがなくなる。According to the above method for manufacturing a semiconductor device, the bottom layer of the insulating film is first planarized, and then the upper and lower connection metals and metal wiring are stacked while being buried in the through holes of the insulating film at the same height. Since multilayer wiring is formed, each layer is all flat and there is no fear of disconnection.
また、不要な金属膜の除去をリフトオフ法により行い、
エツチングをしないから、配線に使用する金属のエツチ
ング性を問題にする必要がなく、金属材料の選択範囲が
広がる。In addition, unnecessary metal films are removed using the lift-off method.
Since no etching is required, there is no need to worry about the etching properties of the metal used for wiring, which widens the range of metal materials to choose from.
本発明方法は、半導体基板の素子とのコンタクトを形成
する第１の配線処理、半導体基板の面方向に延びる金属
配線を一層ずつ形成する第２の配線処理、上下層の金属
配線を接続する上下接続金属を形成する第３の配線処理
を組合せたもので、第１の配線処理を行った後、第２の
配線処理と第３の配線処理を交互に繰り返し行って多層
配線を形成するものである。The method of the present invention includes a first wiring process to form a contact with an element on a semiconductor substrate, a second wiring process to form metal wiring layer by layer extending in the surface direction of the semiconductor substrate, and a top and bottom wiring process to connect upper and lower metal wiring layers. This is a combination of a third wiring process that forms connection metal, and after performing the first wiring process, the second wiring process and third wiring process are alternately repeated to form a multilayer wiring. be.
まず、第１の配線処理について説明する。First, the first wiring process will be explained.
初めに第１図（ａ）に示すように、半導体基板（１０）
の上に平坦化した絶縁膜（１１）を形成する。半導体基
板（１０）の表面には、素子（９）を形成するための拡
散工程で形成された薄い熱酸化膜（ＳｉＯｚ）（１２）
が不均一に被着しているので、全面にガラス系絶縁膜（
ＳＯＧ 、、ＰＳＧ 、 ＢＰＳＧ） （１３）をス
ピナー塗布法により厚く被着形成後焼成したり、厚膜Ｃ
ＶＤ及びエツチングを行って表層部分を取り除き、平坦
化された絶縁膜（１１）を形成する。First, as shown in FIG. 1(a), a semiconductor substrate (10)
A flattened insulating film (11) is formed thereon. On the surface of the semiconductor substrate (10) is a thin thermal oxide film (SiOz) (12) formed in a diffusion process to form the element (9).
is deposited unevenly, so a glass-based insulating film (
SOG, PSG, BPSG) (13) is deposited thickly using a spinner coating method and then baked, or a thick film C
The surface layer portion is removed by VD and etching to form a flattened insulating film (11).
次に第１図Φ）に示すように平坦化された絶縁膜（１１
）の上にコンタクト形成用のフォトレジスト膜（１４）
を形成する。これはフォトレジストを全面に被着形成し
た後、フォトリソグラフィにより、素子の電極対応部分
の窓開けを行って得られる。Next, as shown in Fig. 1 Φ), a flattened insulating film (11
) is covered with a photoresist film (14) for contact formation.
form. This is obtained by depositing a photoresist on the entire surface and then opening a window in a portion of the element corresponding to an electrode using photolithography.
次に、第１図（Ｃ）に示すように、窓開けされたフォト
レジスト膜（１４）を利用し、エツチングにより絶縁膜
（１１）に貫通孔（ｌｌａ）を形成する。このエツチン
グは、初めに絶縁膜（１１）の上層のガラス系絶縁膜（
１３）をプラズマを用いたドライエツチングにより除去
し、次に下層の酸化膜（１２）を所定のエツチング液を
用いたウェットエツチングにより除去して行う。このよ
うにエツチングを二段階に分けるのは、ドライエツチン
グで下層の酸化層（１２）まで除去すると、半導体基板
（１ｏ）の素子（９）に損傷を与える恐れがあるからで
ある。Next, as shown in FIG. 1C, a through hole (lla) is formed in the insulating film (11) by etching using the photoresist film (14) with the window opened. This etching first removes the glass-based insulating film (11) that is the upper layer of the insulating film (11).
13) is removed by dry etching using plasma, and then the underlying oxide film (12) is removed by wet etching using a predetermined etching solution. The reason why the etching is divided into two stages is that if the underlying oxide layer (12) is removed by dry etching, there is a risk of damaging the element (9) of the semiconductor substrate (1o).
次に、このフォトレジスト膜（１４）の剥離性を高める
ため０２プラズマ処理を行う、この処理によりフォトレ
ジスト膜（１４）は脆（なり後のリフトオフを容易とす
るが、この処理のために、フォトレジスト膜（１４）の
分解物質が半導体基板上に被着され、次工程の配線層の
形成の妨げになるので、続いて弗酸液による洗浄処理を
行い除去する。Next, 02 plasma treatment is performed to improve the releasability of this photoresist film (14).This treatment makes the photoresist film (14) brittle (easy to lift off after it becomes brittle), but due to this treatment, Since the decomposed substances of the photoresist film (14) adhere to the semiconductor substrate and interfere with the formation of a wiring layer in the next step, a cleaning treatment with a hydrofluoric acid solution is subsequently performed to remove them.
次に、第１図（６）に示すようにスパッタリング又は金
属蒸着により金属膜（１５）を全面に被着形成する。こ
の厚さは絶縁膜（１１）に形成された貫通孔（ｌｌａ）
を埋める程度であり、この貫通孔（ｌｌａ）から金属膜
（１５）が、少しだけ盛り上がるのが、上層の金属配線
との接続性を高めるため好ましい。Next, as shown in FIG. 1(6), a metal film (15) is formed over the entire surface by sputtering or metal vapor deposition. This thickness corresponds to the through hole (lla) formed in the insulating film (11).
It is preferable that the metal film (15) rises slightly from the through hole (lla) in order to improve connectivity with the metal wiring in the upper layer.
次にリフトオフ法によりフォトレジスト膜（１４）の上
に被着した金属膜（１５）を除去し、絶縁膜（１１）の
貫通孔内に埋め残された金属膜（１５）を残して上下接
続金属（１５ａ）とする。これは所定の薬剤でフォトレ
ジスト膜（１４）を膨潤させ、その上に被着した金属膜
（１５）とともに別離・除去するもので、ここまでが第
１の配線処理である。Next, the metal film (15) deposited on the photoresist film (14) is removed by a lift-off method, leaving the metal film (15) buried in the through hole of the insulating film (11) for upper and lower connections. It is made of metal (15a). In this process, the photoresist film (14) is swollen with a predetermined chemical, and then separated and removed together with the metal film (15) deposited thereon.This is the first wiring process.
第２の配線処理について説明する。The second wiring process will be explained.
まず第１図（ｅ）に示すように、上下接続金属（１５ａ
）が埋込み形成された絶縁膜（１１）の上に、配線間絶
縁膜（１６）を全面被着する。First, as shown in FIG. 1(e), the upper and lower connecting metals (15a
) is entirely covered with an inter-wiring insulating film (16) on the insulating film (11) in which the insulating film (11) is embedded.
次に第１図（ｆ）に示すように、配線間絶縁膜（工６）
の上に、第１層の金属配線を形成するためのフォトレジ
スト処理を行う、これは全面にフォトレジスト膜（１７
）を被着形成した後、フォトリソグラフィにより配線予
定部分を取り除くものである。Next, as shown in FIG. 1(f), an inter-wiring insulation film (step 6) is formed.
On top of this, a photoresist process is performed to form the first layer of metal wiring, which is a photoresist film (17
) is deposited and formed, and then the planned wiring portion is removed by photolithography.
次に第１図（６）に示すように、フォトレジスト膜（１
７）の窓明は部分を通して配線間絶縁膜（１６）にガス
プラズマによるドライエツチングを行って貫通孔（１６
ａ）を形成する。そして０２プラズマ処理を行ってフォ
トレジスト膜（１７）の剥離性を向上し、さらに弗酸液
により処理する。Next, as shown in FIG. 1 (6), a photoresist film (1
The window 7) is made by dry etching the inter-wiring insulating film (16) through the part using gas plasma to form the through hole (16).
Form a). Then, 02 plasma treatment is performed to improve the releasability of the photoresist film (17), and further treatment is performed with a hydrofluoric acid solution.
次に第１図（ハ）に示すように、金属膜（１８）を全面
被着し、貫通孔（１６ａ）をこの金属膜（１８）で埋め
る。Next, as shown in FIG. 1(c), a metal film (18) is deposited on the entire surface, and the through hole (16a) is filled with this metal film (18).
次にフォトレジスト膜（１７）を薬剤で膨潤させること
により不要な金属膜（１８）の除去を行って、配線間絶
縁膜（１６）の貫通孔（１６ａ）の内部に金属配線（１
８ａ）を埋め残す、ここまでが第２の配線処理である。Next, the unnecessary metal film (18) is removed by swelling the photoresist film (17) with a chemical, and the metal wiring (18) is inserted into the through hole (16a) of the inter-wiring insulating film (16).
The process up to this point in which 8a) is left unfilled is the second wiring process.
次に第３の配線処理を行う。Next, a third wiring process is performed.
まず、第１図（１）に示すように、層間絶縁膜（１９）
の全面被着、所定部分が窓開けされたフォトレジスト膜
（２０）の形成をし、この窓を通したエツチングにより
層間絶縁膜（１９）に貫通孔（１９ａ）の形成を行う。First, as shown in FIG. 1 (1), an interlayer insulating film (19) is formed.
A photoresist film (20) with a window opened at a predetermined portion is formed, and a through hole (19a) is formed in the interlayer insulating film (19) by etching through the window.
この後、第１図（ｄ）で説明したのと同様に金属膜の全
面被着、フォトレジスト膜（２０）の薬剤によるリフト
オフにより不要な金属膜を除去することによって、第１
図（ｊ）のように、層間絶縁膜（１９）の貫通孔（１９
ａ）内に上下接続金属（２１）を形成する。ここまでが
第３の配線処理である。After that, as described in FIG. 1(d), the unnecessary metal film is removed by depositing the metal film on the entire surface and lifting off the photoresist film (20) with a chemical.
As shown in figure (j), the through hole (19) of the interlayer insulating film (19)
Form upper and lower connection metals (21) in a). This is the third wiring process.
この後、上記第２の配線処理と第３の配線処理を繰り返
して行えば、各層が平坦化された多層配線を形成するこ
とができる。Thereafter, by repeating the second wiring process and the third wiring process, it is possible to form a multilayer wiring in which each layer is planarized.
本発明によれば、各層の配線が完全に平坦化された状態
で行われるので、金属配線の段切れのおそれがな（半導
体装置の歩留まり向上、並びに信頼性の向上が図れる。According to the present invention, since wiring in each layer is performed in a completely flattened state, there is no fear of disconnection of metal wiring (improvement in yield and reliability of semiconductor devices can be achieved).
また金属膜に工・ンチング処理をしないので、配線用の
金属材料の選択範囲を広げることができる。Furthermore, since the metal film is not processed or etched, the selection range of metal materials for wiring can be expanded.
第１図（ａ）〜（ｊ）は本発明方法を工程順にしたがっ
て示す半導体装置の断面図である。
第２図は従来の多層配線構造を示す半導体装置の断面図
、第３図（ａ）＠は夫々従来の多層配線を作る工程を示
す半導体装置の断面図である。
（１０）−半導体基板、
（１１） −ｍ−平坦化された絶縁膜、（１４） （
１７） （２ＯＬ−−−フォトレジスト膜、（１５ａ
） （２１） −一−−上下接続金属、（１６）
−−一配線間絶縁膜、
（１８ａ）−・−金属配線、
（１９）−層間絶縁膜。FIGS. 1(a) to 1(j) are cross-sectional views of a semiconductor device showing the method of the present invention in the order of steps. FIG. 2 is a sectional view of a semiconductor device showing a conventional multilayer wiring structure, and FIG. 3(a) is a sectional view of a semiconductor device showing a process of making a conventional multilayer wiring. (10)-Semiconductor substrate, (11)-m-Planarized insulating film, (14) (
17) (2OL---Photoresist film, (15a
) (21) -1-- Upper and lower connection metal, (16)
--One wiring insulating film, (18a)--metal wiring, (19)-interlayer insulating film.
Claims (1)
れを平坦化処理した後に、 フォトレジスト膜を被着形成し所定部分を窓開けする工
程、この窓を通してエッチングを行い絶縁膜に貫通孔を
形成する工程、金属膜を前記絶縁膜の貫通孔を埋める厚
さで全面に被着形成する工程、このフォトレジスト膜を
薬剤により膨潤させてその上に被着した金属膜とともに
剥離する工程からなるリフトオフ法によって、 上記平坦な絶縁膜の貫通孔内に、金属膜の一部を埋め残
して下端が素子電極に接続された上下接続金属を形成す
る第１の配線処理を行い、 配線間絶縁膜を全面被着した後に、この配線間絶縁膜に
形成した貫通孔内に、リフトオフ法によって、金属膜の
一部を埋め残して下面の一部が上下接続金属に接続され
た金属配線を形成する第２の配線処理を行い、 次に、層間絶縁膜を全面被着した後に、この層間絶縁膜
に形成した貫通孔内に、リフトオフ法によって、金属膜
の一部を埋め残して下端が配線に接続された上下接続金
属を形成する第３の配線処理を行い、 この後、上記第２の配線処理と第３の配線処理を交互に
繰り返して、上層と下層の金属配線が上下接続金属によ
って接続された多層配線を形成することを特徴とする半
導体装置の製造方法。[Claims] A step of forming an insulating film on a semiconductor substrate on which an element is formed, and then planarizing the insulating film, depositing a photoresist film, opening a window in a predetermined portion, and etching through the window. a step of forming a through hole in the insulating film, a step of depositing a metal film on the entire surface to a thickness that fills the through hole of the insulating film, and a step of swelling this photoresist film with a chemical and depositing it on top of the metal film. A first wiring is formed in the through-hole of the flat insulating film by a lift-off method, which involves peeling off the metal film together with a part of the metal film, to form upper and lower connection metals whose lower ends are connected to the element electrodes. After processing and depositing the inter-wiring insulating film over the entire surface, a lift-off method is used to fill in a portion of the metal film in the through-hole formed in the inter-wiring insulating film so that part of the bottom surface becomes the upper and lower connection metal. A second wiring process is performed to form connected metal wiring, and then, after an interlayer insulating film is deposited on the entire surface, a part of the metal film is deposited into the through hole formed in the interlayer insulating film by a lift-off method. A third wiring process is performed to form upper and lower connection metals whose lower ends are connected to the wiring by leaving the area unfilled. After this, the second wiring process and the third wiring process are alternately repeated to form upper and lower A method for manufacturing a semiconductor device, comprising forming a multilayer wiring in which metal wirings are connected by upper and lower connecting metals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4880390A JPH03248527A (en) | 1990-02-27 | 1990-02-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4880390A JPH03248527A (en) | 1990-02-27 | 1990-02-27 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03248527A true JPH03248527A (en) | 1991-11-06 |
Family
ID=12813372
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4880390A Pending JPH03248527A (en) | 1990-02-27 | 1990-02-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03248527A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7291278B2 (en) | 2003-09-17 | 2007-11-06 | Seiko Epson Corporation | Electrode forming method |
-
1990
- 1990-02-27 JP JP4880390A patent/JPH03248527A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7291278B2 (en) | 2003-09-17 | 2007-11-06 | Seiko Epson Corporation | Electrode forming method |
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