JPH03248450A - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- JPH03248450A JPH03248450A JP2046129A JP4612990A JPH03248450A JP H03248450 A JPH03248450 A JP H03248450A JP 2046129 A JP2046129 A JP 2046129A JP 4612990 A JP4612990 A JP 4612990A JP H03248450 A JPH03248450 A JP H03248450A
- Authority
- JP
- Japan
- Prior art keywords
- leg
- conductor circuit
- electrode
- substrate
- heat spreader
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000004020 conductor Substances 0.000 abstract description 17
- 239000000463 material Substances 0.000 abstract description 9
- 229910000679 solder Inorganic materials 0.000 abstract description 6
- 230000000694 effects Effects 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Cooling Or The Like Of Electrical Apparatus (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、電子装置等に使用される半導体パッケージに
関し、特に大電力ＩＣの微細なピッチの表面実装に用い
る半導体パッケージに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor package used for electronic devices and the like, and particularly to a semiconductor package used for fine pitch surface mounting of high power ICs.
第４図はこの種の従来の半導体パッケージの実装例を示
す斜視図である。同図においてリード１２を有するＩＣ
ｌ３がヒートシンク７に取り付けられ、ヒートシンク７
の脚８が基板９上の導体回路１１に半田付は等で接続さ
れ、リード１２を導体回路１０に半田付けや熱圧着法等
で接続している。FIG. 4 is a perspective view showing an example of mounting a conventional semiconductor package of this type. In the figure, an IC with leads 12
l3 is attached to the heat sink 7, and the heat sink 7
The legs 8 are connected to the conductor circuit 11 on the board 9 by soldering or the like, and the leads 12 are connected to the conductor circuit 10 by soldering, thermocompression bonding, or the like.
上記のヒートシンク７はＩＣｌ３の熱を効率よく、放射
させることができるが、ＩＣのり−ド１２と基板上の導
体回路１０との位置あわせには特別の工夫はなされてい
ない、これはＩＣのり−ド１２がある程度の自由度を持
って導体回路１゜に対して位置を合せることができるか
らである。Although the heat sink 7 described above can efficiently radiate the heat of the ICl 3, no special measures have been taken to align the IC glue 12 and the conductor circuit 10 on the board. This is because the lead 12 can be positioned with respect to the conductor circuit 1° with a certain degree of freedom.
また、リド１２のピッチも比較大きく、それほど厳密な
位置合せが必要ない。Furthermore, the pitch of the lids 12 is relatively large, and so strict alignment is not required.
しかしながら接続端子数の増加に伴いリード１２を微細
化する必要があり、リード１２のピッチが１００μ以下
になるとリードの形成が困難になると共に、脚８の取付
けやリード１２の接続の熱でリードの変形や導体回路に
対する位１ずれを起こす欠点がある。However, as the number of connection terminals increases, it is necessary to miniaturize the leads 12, and if the pitch of the leads 12 becomes less than 100μ, it becomes difficult to form the leads, and the heat of attaching the legs 8 and connecting the leads 12 causes the leads to become smaller. It has the drawback of causing deformation and displacement with respect to the conductor circuit.
本発明は上記欠点に鑑み、リードを無くした接続を行い
、微細で多くの端子接続を可能にし、放射性能の優れた
実装を可能にした半導体パッケージを提供することを目
的とする。SUMMARY OF THE INVENTION In view of the above drawbacks, it is an object of the present invention to provide a semiconductor package in which connections are made without leads, allowing fine and numerous terminal connections, and packaging with excellent radiation performance.
また、従来の半導体パッケージのヒートシンク７はＬＳ
Ｉと固着しているため、材質として熱膨張係数がＬＳＩ
材料と一致する必要がある。がっ、ヒートシンクとして
の役目から熱伝導性が良く、フィン状に加工することか
ら加工性の良いものが必要であり、さらに価格的に安い
ものが好ましい。しかしながら、このようなすべての条
件を満足する材料は少なく、どれかの特性を犠牲にして
いた。In addition, the heat sink 7 of the conventional semiconductor package is LS
Since it is fixed with I, the coefficient of thermal expansion of the material is LSI.
Must match the material. However, since it serves as a heat sink, it needs to have good thermal conductivity, and since it can be processed into a fin shape, it needs to be easy to work with, and it is also preferable to use something that is cheap. However, there are few materials that satisfy all of these conditions, and some of the properties are sacrificed.
また、フリップチップ構造の半導体パッケージでは、Ｉ
Ｃ上の電極と基板上の導体回路の位置あわせは、例えば
ＩＣの外形を基準にしておこなっていた。しかしながら
、ＩＣの裏面の外形はチッピング等がおこりやすく、正
確な位１あわせがしにくいという問題があった。In addition, in a semiconductor package with a flip-chip structure, I
The positioning of the electrodes on the C and the conductor circuits on the substrate has been done based on, for example, the outer shape of the IC. However, there is a problem in that the outer shape of the back surface of the IC is prone to chipping, etc., and it is difficult to perform accurate alignment.
本発明の半導体パッケージは、基板への取り付けに用い
られる脚を有するヒートスプレッダ−と、前記脚で囲ま
れる側のヒートスプレッダ−に取り付けられた少なくと
も１つのＩＣとを備え、前記脚の長さが前記ＩＣの高さ
より長く、前記ヒートスプレッダ−と前記ＩＣ上の電極
の位１があらかじめ定められた位ＷｒＲ係を保持するよ
うにして構成される。The semiconductor package of the present invention includes a heat spreader having legs used for attachment to a substrate, and at least one IC attached to the heat spreader on a side surrounded by the legs, and the length of the legs is the same as that of the IC. The heat spreader and the electrodes on the IC are configured to maintain a predetermined WrR relationship.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）および（ｂ）は本発明の一実施例を示す斜
視図及び縦断面図である。同図において半導体パッケー
ジは脚１を四隅に設けたヒートスプレッダ−２にＩＣ３
が半田、例えばＡ ｕ ／Ｓ ｕ （８０／ ２０ｗｔ
％〉等の接合材で取り付けられ、ＩＣＢ上には電極５が
半田で形成されている。ＩＣ３の高さに対して脚１の長
さを６寸法だけ長くする。ＩＣ３の位置は脚１に対して
ａ、ｂ寸法にする。FIGS. 1(a) and 1(b) are a perspective view and a longitudinal sectional view showing an embodiment of the present invention. In the same figure, the semiconductor package has legs 1 installed on the four corners of the heat spreader 2, and the IC3
is solder, for example A u /S u (80/20wt
%> or the like, and electrodes 5 are formed on the ICB with solder. The length of leg 1 is increased by 6 dimensions relative to the height of IC3. The position of IC3 is set at dimensions a and b with respect to leg 1.
第２図は上記の半導体パッケージの実装例を示す側面図
である。同図を参照すると脚１を基板９の導体回路１１
に半田付けすると共に半田の電極５を基板９上の導体回
路６に接続する。この時、ＩＣ３の高さに対して脚ｌの
長さは６寸法だけ長いので、電極５は球体からつづみ形
状に変わる。FIG. 2 is a side view showing an example of mounting the above semiconductor package. Referring to the figure, the leg 1 is connected to the conductor circuit 11 of the board 9.
At the same time, the solder electrode 5 is connected to the conductive circuit 6 on the substrate 9. At this time, the length of the leg 1 is longer by 6 dimensions than the height of the IC 3, so the electrode 5 changes from a spherical shape to a string shape.
この形状が接続信頼性上で最も適していて、脚が無い場
合は第３図に示すように太鼓形状になり、周囲の接続部
に大きな応力がかかりやすい。This shape is most suitable in terms of connection reliability, and when there are no legs, the shape becomes a drum shape as shown in FIG. 3, and large stress is likely to be applied to the surrounding connection parts.
また、予め導体回路１１と導体回路６と位置寸法ａ’
、ｂ’寸法をａ、ｂ寸法と同じにしておくことにより脚
１を基板９の導体回路１１に位１合わせすれば導体回路
６と電極５との位置合せも同時に実現できる。すなわち
、ＩＣ上の電極とヒートスプレッダ−の脚の位置関係（
寸法ａ、ｂ）を正確に合せることにより、基板との位置
合せをヒートスプレッダ−とおこなうことによって自動
的に基板とＩＣ電極との位置合せができる。In addition, in advance, the conductor circuit 11, the conductor circuit 6, and the positional dimension a'
, b' dimensions are made the same as a and b dimensions so that the leg 1 can be aligned with the conductor circuit 11 of the substrate 9, and the conductor circuit 6 and the electrode 5 can be aligned at the same time. In other words, the positional relationship between the electrodes on the IC and the legs of the heat spreader (
By accurately matching the dimensions a and b), the substrate and the IC electrode can be automatically aligned by aligning the substrate with the heat spreader.
ヒートスプレッダ−２はＩＣ３で発生する熱を裏面へ広
げて伝え、ヒートスプレッダ−上に付けられるヒートシ
ンク（図示せず）等で冷却する。The heat spreader 2 spreads and transmits the heat generated by the IC 3 to the back surface, and is cooled by a heat sink (not shown) or the like attached to the heat spreader.
ヒートスプレッダ−の材質としてはＣｕ ／ Ｗ複合材
、ＡＩＮ、ＳｉＣ等の熱伝導率が良く、熱膨張係数がＬ
ＳＩ材料（本実施例ではシリコン）にあっているものを
用いる。すなわち、ヒートシンクとしてＡＩやＣｕなど
のように価格が安く、加工性の良いものを用いることが
できる。さらに、空冷などのヒートシンクのみならず液
冷タイプのコールドプレート等を圧接して冷却しなり、
絶縁性液体に深漬して冷却したりすることができる。The material for the heat spreader is Cu/W composite material, AIN, SiC, etc., which have good thermal conductivity and a coefficient of thermal expansion of L.
A material suitable for SI material (silicon in this example) is used. That is, materials such as AI and Cu, which are inexpensive and have good workability, can be used as the heat sink. Furthermore, in addition to air-cooled heat sinks, liquid-cooled cold plates can be used for cooling.
It can be cooled by deep immersion in an insulating liquid.
本発明の半導体パッケージはヒートスプレッダ−の脚を
寸法合せに利用しているので、基板実装が容易で接続の
信頼性が高い微細な多端子を可能にし、さらに放射性お
よび加工性の良い半導体パッケージを提供することがで
きる効果がある。Since the semiconductor package of the present invention uses the legs of the heat spreader for dimension adjustment, it is easy to mount on the board, enables fine multi-terminals with high connection reliability, and provides a semiconductor package with good radiation and processability. There is an effect that can be done.
第１図（ａ）および（ｂ）は本発明は一実施例を示す斜
視図及び縦断面図、第２図は本発明の半導体パッケージ
の実装例を示す側面図、第３図は不良のｔ極接合を示す
説明図、第４図は従来例を示す斜視図である。
１・・・・・・脚、２・・・・・・ヒートスプレッダ−
３・・・・・・ＩＣ，４・・・・・・接合材、５・・・
・・・電極、６・・・・・・導体回路、９・・・・・・
基板。1(a) and (b) are perspective views and vertical sectional views showing one embodiment of the present invention, FIG. 2 is a side view showing an example of mounting the semiconductor package of the present invention, and FIG. 3 is a defective t FIG. 4 is a perspective view showing a conventional example. 1... Legs, 2... Heat spreader
3...IC, 4...Joining material, 5...
...Electrode, 6...Conductor circuit, 9...
substrate.
Claims (1)
レッダーと、前記脚で囲まれる側のヒートスプレッダー
に取り付けられた少なくとも１つのＩＣとを備え、前記
脚の長さが前記ＩＣの高さより長く、前記ヒートスプレ
ッダーと前記ＩＣ上の電極の位置があらかじめ定められ
た位置関係を保持することを特徴とする半導体パッケー
ジ。a heat spreader having legs used for attachment to a substrate; and at least one IC attached to the heat spreader on a side surrounded by the legs, the legs being longer than the height of the IC, and the heat spreader having legs that are used for attachment to a substrate; A semiconductor package characterized in that a spreader and an electrode on the IC maintain a predetermined positional relationship.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2046129A JPH03248450A (en) | 1990-02-26 | 1990-02-26 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2046129A JPH03248450A (en) | 1990-02-26 | 1990-02-26 | Semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03248450A true JPH03248450A (en) | 1991-11-06 |
Family
ID=12738377
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2046129A Pending JPH03248450A (en) | 1990-02-26 | 1990-02-26 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03248450A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020093258A (en) * | 2001-06-07 | 2002-12-16 | 주식회사 하이닉스반도체 | ball grid array type package and method of fabricating the same |
| GB2493820B (en) * | 2011-08-18 | 2016-05-11 | Dy 4 Systems Inc | Manufacturing process and heat dissipating device for forming interface for electronic component |
-
1990
- 1990-02-26 JP JP2046129A patent/JPH03248450A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020093258A (en) * | 2001-06-07 | 2002-12-16 | 주식회사 하이닉스반도체 | ball grid array type package and method of fabricating the same |
| GB2493820B (en) * | 2011-08-18 | 2016-05-11 | Dy 4 Systems Inc | Manufacturing process and heat dissipating device for forming interface for electronic component |
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