JPH0430545A - Mounting structure of semiconductor device - Google Patents
Mounting structure of semiconductor deviceInfo
- Publication number
- JPH0430545A JPH0430545A JP2137766A JP13776690A JPH0430545A JP H0430545 A JPH0430545 A JP H0430545A JP 2137766 A JP2137766 A JP 2137766A JP 13776690 A JP13776690 A JP 13776690A JP H0430545 A JPH0430545 A JP H0430545A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- substrate
- mounting
- lead
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 82
- 239000000758 substrate Substances 0.000 claims description 34
- 239000004020 conductor Substances 0.000 claims description 13
- 229910000679 solder Inorganic materials 0.000 abstract description 10
- 239000011347 resin Substances 0.000 abstract description 5
- 229920005989 resin Polymers 0.000 abstract description 5
- 239000004593 Epoxy Substances 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 6
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の実装構造に間するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to a mounting structure for a semiconductor device.
第８図は、半導体装置の従来の実装構造を示すもので、
半導体装置１が、基板２上の導体リード３と、半田４等
により接続されたリードをフィルム５上に有するフィル
ムリード５ａに、突起状電極バンプ６を介在させてフェ
ースダウンボンディング実装されたもので、いわゆるＴ
ＡＢ方式と言われる実装構造を示すものである。FIG. 8 shows a conventional mounting structure of a semiconductor device.
A semiconductor device 1 is face-down bonded to a film lead 5a having conductor leads 3 on a substrate 2 and leads connected by solder 4 or the like on a film 5, with protruding electrode bumps 6 interposed therebetween. , the so-called T
This shows a mounting structure called the AB method.
半導体装置１は、ウェハーをグイシングして製造される
ため、その形状は高さに対して縦、横がはるかに大きい
チップ状の形状を有しており、基板２に対してその半導
体装置１が横向き（縦、横で定まる面を基板２に対向さ
せた方向）となるように実装されている。半導体装ｉｌ
ｌとフィルムリード５ａの間で、フィルムリード５ａの
半導体装置側先端には、電極であるバンプ６が設けられ
、これを介して半導体装置ｌとフィルムリード５ａの電
気的接続が採られる。このバンプ６は、半田又は金等の
無機材料で構成され、フリップチップに見られるように
半導体装置１自体に設けられたものや、半導体装１１に
転写して形成する転写バンプ及び、フィルムリード５ａ
上に設けられるメサバンプ等の種々のものがあり、加熱
又は加重されることにより、半導体装置１とフィルムリ
ード５３間）接続する構成となっている。また、フェ−
スダウンボンディング実装の方法としては、ギヤング（
−括）ポンディングやシングルポイントポンディング等
の方法が採られる。Since the semiconductor device 1 is manufactured by wafer dicing, it has a chip-like shape that is much larger in length and width than its height, and the semiconductor device 1 is placed on the substrate 2. It is mounted so as to be oriented horizontally (the direction in which the surface defined by the vertical and horizontal directions faces the substrate 2). semiconductor equipment il
A bump 6, which is an electrode, is provided at the tip of the film lead 5a on the semiconductor device side between the semiconductor device l and the film lead 5a, and the semiconductor device l and the film lead 5a are electrically connected through this. The bumps 6 are made of an inorganic material such as solder or gold, and may be provided on the semiconductor device 1 itself as seen in a flip chip, transfer bumps formed by transferring to the semiconductor device 11, or film leads 5a.
There are various things such as mesa bumps provided on the semiconductor device 1 and the film lead 53 by heating or applying weight. In addition,
Gui Young (
Methods such as bonding and single point bonding are used.
第９図は、半導体装置の実装構造の別の従来例を示すも
ので、半導体装置１が、基板２上の導体リード３の先端
に設けられたバンブ６に、加熱接合されたものである。FIG. 9 shows another conventional example of a semiconductor device mounting structure, in which a semiconductor device 1 is thermally bonded to a bump 6 provided at the tip of a conductor lead 3 on a substrate 2.
前記第１の従来例と同様に半導体装置１は、基板２に対
してその半導体装置１が横向きとなるように実装されて
おり、バンブ６は半田バンブで、高融点半田（Ｓｎ ／
Ｐｂ ５〜ｌＯ％）、共晶半田（Ｓｎ 、、”ｐｂ ６
０〜７０％）、低融点半田（Ｉｎ系、Ｂｉ系合金）等に
より構成され、ＩＲコンベヤ、■ＰＳ又は雰囲気ガス炉
等により製作される。なお、実装方法としては前記従来
例と同様にフェースダウンポンディング法等が採られる
。Similar to the first conventional example, the semiconductor device 1 is mounted so that the semiconductor device 1 is placed horizontally on the substrate 2, and the bumps 6 are solder bumps made of high melting point solder (Sn/
Pb 5~1O%), eutectic solder (Sn, ``pb 6
0 to 70%), low melting point solder (In-based, Bi-based alloy), etc., and manufactured using an IR conveyor, PS, atmospheric gas furnace, etc. Incidentally, as a mounting method, a face-down bonding method or the like is adopted as in the conventional example.
〔発明が解決しようとする課題］
ところで、第８図に示すＴＡＢ方式と呼ばれる従来の実
装構造においては、半導体装置ｌが基板２に対して横向
きに実装されており、フィルムリード５ａが半導体装置
１よりも外側のアウターリード５ｂを有しているため、
半導体装置１を基板２に実装する際の実装面積は、半導
体装Ｗ１の縦、横で定まる面の面積（平面方向の面積と
表現）とアウターリード５ｂの面積を加えたものよりも
小さくならず、大きな実装面積を必要とするという問題
点があった。[Problem to be Solved by the Invention] Incidentally, in a conventional mounting structure called the TAB method shown in FIG. Since the outer lead 5b is located on the outer side of the outer lead 5b,
The mounting area when mounting the semiconductor device 1 on the substrate 2 is not smaller than the sum of the area of the surface determined by the length and width of the semiconductor device W1 (expressed as the area in the planar direction) and the area of the outer lead 5b. However, there was a problem in that it required a large mounting area.
また、第９図に示す従来の別の実装構造においても前記
第１の従来例と同様に、半導体装置１が基板２に対して
横向きに実装されているため、この半導体装置１を基板
２に実装する際の実装面積は、少なくとも前記平面方向
の面積が必要で、前記第１の従来例よりは低減できても
なお、大きな実装面積を必要とするという問題点があっ
た。Furthermore, in another conventional mounting structure shown in FIG. 9, the semiconductor device 1 is mounted horizontally with respect to the substrate 2, as in the first conventional example. The mounting area for mounting requires at least the area in the plane direction, and even if the mounting area can be reduced compared to the first conventional example, there is still a problem in that a large mounting area is required.
本発明は、前記前景に鑑みてなされたものであり、その
目的とするところは、半導体装置を基板に実装する際の
実装専有面積を低減させた半導体装置の実装構造を提供
することにある。The present invention has been made in view of the foregoing, and an object of the present invention is to provide a mounting structure for a semiconductor device that reduces the mounting area occupied when the semiconductor device is mounted on a substrate.
上記課題を解決するため本発明は、半導体装置１が実装
される基板２に、孔又は凹状の半導体装！保持部２ａを
設けると共に、該半導体装置保持部２ａに、半導体装置
１を基板２に対して略垂直になるように挿入し、該半導
体装置１と基板２上の導体リード３を略り字形に成形さ
れたフィルムリード５ａにより接続したことを特徴とす
るものである。In order to solve the above problems, the present invention provides a semiconductor device having a hole or a concave shape in a substrate 2 on which a semiconductor device 1 is mounted! A holding portion 2a is provided, and the semiconductor device 1 is inserted into the semiconductor device holding portion 2a so as to be substantially perpendicular to the substrate 2, and the semiconductor device 1 and the conductor leads 3 on the substrate 2 are arranged in an abbreviated shape. It is characterized in that it is connected by a molded film lead 5a.
上記のように本発明の実装構造においては、半導体装置
ｌを基板２に対して縦向きに実装し、半導体装置１の平
面方向の面積よりもはるかに小さい面積を有する側面を
基板２に対向させているため、基板２上の半導体装置ｌ
の実装専有面積は非常に小さくなる。また、基板２に設
けた孔又は凹状の半導体装置保持部２ａに、半導体装置
１を挿入することにより、その実装高さも低くなる。As described above, in the mounting structure of the present invention, the semiconductor device 1 is mounted vertically on the substrate 2, and the side surface having a much smaller area than the planar area of the semiconductor device 1 faces the substrate 2. Therefore, the semiconductor device l on the substrate 2
The mounting area will be very small. In addition, by inserting the semiconductor device 1 into the hole provided in the substrate 2 or the recessed semiconductor device holding portion 2a, the mounting height thereof is also reduced.
〔実施例］
第１図及び第２図は、本発明の第１の実施例を示すもの
である。半導体装置ｌが実装される基板２は、半導体装
置１が１個のみ搭載可能なものや、他の電子部品等の搭
載の可能ないわゆるプリント配線基板等であり、その一
部に貫通した礼状の半導体保持部２ａを有し、半導体装
置１は、ハンプ６を介在して、略り字形の形状をしたフ
ィルム５上にリードを有するフィルムリード５ａにフェ
ースダウンポンディングされ、基板２と略垂直になるよ
うに、前記礼状の半導体保持部２ａに挿入されている。[Embodiment] FIGS. 1 and 2 show a first embodiment of the present invention. The board 2 on which the semiconductor device 1 is mounted is a so-called printed wiring board, etc. that can mount only one semiconductor device 1 or that can mount other electronic components, etc. The semiconductor device 1 has a semiconductor holding portion 2a, and the semiconductor device 1 is face-down bonded to a film lead 5a having a lead on a film 5 having an abbreviated letter shape through a hump 6, and is mounted substantially perpendicularly to the substrate 2. It is inserted into the semiconductor holding portion 2a of the thank you note.
フィルムリード５ａは、折り曲げが可能な材料で構成さ
れ、有機材料からなるフィルム上に、導体リード（導電
性金属材料；Ｃｕ、ＡｕＦ ｅ−Ｎ ｉ、その他合金等
よりなる）が形成されたもので、略り字形に曲げられ、
その−片が、インナーリード５ｃとして半導体装置１と
の電気的接続に利用され、他片が、アウターリード５ｂ
として電子回路基板２に略平行に引き出される。このア
ウターリード５ｂは、電子回路基板２上の回路パターン
である導体リード３と、半田４又は導電性接着剤等によ
り接続されている。このように基板２に搭載された半導
体装置１は、エポキシ又はシリコン系等の樹脂７により
封止されて固定されている。The film lead 5a is made of a bendable material, and a conductor lead (made of a conductive metal material; Cu, AuFe-Ni, other alloys, etc.) is formed on a film made of an organic material. , bent into an abbreviated form,
The - piece is used as the inner lead 5c for electrical connection with the semiconductor device 1, and the other piece is used as the outer lead 5b.
It is pulled out substantially parallel to the electronic circuit board 2. The outer lead 5b is connected to a conductor lead 3, which is a circuit pattern on the electronic circuit board 2, by solder 4, a conductive adhesive, or the like. The semiconductor device 1 mounted on the substrate 2 in this manner is sealed and fixed with a resin 7 such as epoxy or silicone.
第２図は、本実施例の製造方法を示すもので、まず、一
端にバンプ６を有するフィルムリード５ａ（同図（ａ）
参照）に、半導体装置１をフェースダウンボンディング
し、加熱又は加重によりパン１６部分を接合させて電気
的接続を採る（同図Φ）参照）０次に、フィルムリード
５ａを半導体装Ｎ１と反対側に略垂直に折り曲げてアウ
ターリード５ｂとしく同図（Ｃ）参照）、この半導体装
置ｌを基板２の礼状の半導体保持部２ａに挿入しく同図
（ｄ）参照）、アウターリード５ｂと基板２上の導体リ
ード３を半田４又は導電性樹脂等により接続しく同図（
ｅ）参照）、最後に、半導体装ＩＦＩをエポキシ又はシ
リコン系等の樹脂７で封止して固定する（同図（ｆ）参
照）という方法により製造される。FIG. 2 shows the manufacturing method of this embodiment. First, a film lead 5a having a bump 6 at one end (as shown in FIG.
(see Φ in the same figure) Next, the film lead 5a is bonded face-down to the semiconductor device 1 on the side opposite to the semiconductor device N1. The semiconductor device 1 is bent approximately perpendicularly to form the outer lead 5b (see figure (C)), and the semiconductor device 1 is inserted into the semiconductor holding portion 2a of the substrate 2 (see figure (d)). Connect the upper conductor lead 3 with solder 4 or conductive resin, etc.
(see e)), and finally, the semiconductor device IFI is sealed and fixed with a resin 7 such as epoxy or silicone (see (f) in the same figure).
なお、フィルムリード５ａを略垂直に折り曲げてアウタ
ーリード５ｂとする工程は半導体装置１と搭載する前に
行っても良い。Note that the step of bending the film lead 5a substantially vertically to form the outer lead 5b may be performed before mounting the semiconductor device 1.
このように構成したことにより、半導体装置１を基板２
に対して縦向きに実装し、半導体装置１の平面方向の面
積よりもはるかに小さい面積を有する側面を基板２に対
向させているため、基板２上の半導体装置１の実装専有
面積は非常に小さくなり、部品の実装密度が向上する。With this configuration, the semiconductor device 1 is connected to the substrate 2.
Since the semiconductor device 1 is mounted vertically on the substrate 2 and the side surface having a much smaller area than the planar area of the semiconductor device 1 faces the substrate 2, the area occupied by the semiconductor device 1 on the substrate 2 is extremely large. It becomes smaller and the mounting density of components improves.
また、基板２に設けた孔又は凹状の半導体装置保持部２
ａに、半導体装置１を挿入することにより、その実装高
さも低くなり、スペースが有効に利用できる。このため
、半導体装置１を実装する基板２の面積を小さくするこ
とができ、さらには、その基板２の内蔵された製品の小
型化が図れる。さらには、半導体装置１を可とう性のあ
るフィルムリード５ａを用いているため、半導体装置１
と導体リード３との接合部等の熱応力による剥離やクラ
ック等が防げる。In addition, a hole provided in the substrate 2 or a concave semiconductor device holding portion 2 may be used.
By inserting the semiconductor device 1 into a, the mounting height thereof can be reduced, and space can be used effectively. Therefore, the area of the substrate 2 on which the semiconductor device 1 is mounted can be reduced, and furthermore, the size of the product incorporating the substrate 2 can be reduced. Furthermore, since the semiconductor device 1 uses the flexible film lead 5a, the semiconductor device 1
Peeling, cracking, etc. due to thermal stress at the joint between the conductor lead 3 and the like can be prevented.
第３図は、本発明の第２の実施例を示すもので、前記第
１′の実施例と異なる点は、半導体保持部２ａとフィル
ムリード５ａであり、基板２に設けられた半導体保持部
２ａは、貫通孔ではなく有底で凹状に形成されたもので
ある。また、フィルムリード５ａは略り字形のフィルム
リード５ａを２本用いて、それらのアウターリード５ｂ
を絶縁性接着剤８で貼り合わせ、そのアウターリード５
ｂを基板２上の導体リード３に接続するものである。こ
こで、絶縁性の接着剤で貼り合わされた同図における上
下２本のアウターリード５ｂは、それぞれ対応した導体
リード３と接続されている。なお、本実施例をも含めて
以下の実施例の製法は、前記第１の実施例の製法と略同
じである。FIG. 3 shows a second embodiment of the present invention, which differs from the first embodiment in that it includes a semiconductor holding part 2a and a film lead 5a, and a semiconductor holding part provided on the substrate 2. 2a is not a through hole but is formed in a concave shape with a bottom. In addition, the film lead 5a uses two abbreviated film leads 5a, and their outer leads 5b
are bonded together with an insulating adhesive 8, and the outer lead 5
b is connected to the conductor lead 3 on the substrate 2. Here, the two upper and lower outer leads 5b in the figure, which are bonded together with an insulating adhesive, are connected to the corresponding conductor leads 3, respectively. The manufacturing methods of the following examples, including this example, are substantially the same as the manufacturing method of the first example.
このような構成においても、前記第１の実施例と同様の
効果を奏する。Even in such a configuration, the same effects as in the first embodiment can be achieved.
第４図は、本発明の第３の実施例を示すもので、前記第
１の実施例と異なる点は、フィルムリード５ａのみであ
り、他は前記第２の実施例と同じである。FIG. 4 shows a third embodiment of the present invention, which differs from the first embodiment only in the film lead 5a, and is otherwise the same as the second embodiment.
フィルムリード５ａは、前記第１及び第２の実施例にお
ける略り字形フィルムリード５ａに、平面状のフィルム
リード５ｄを半導体装置１に面した側に導電性材料９（
半田、樹脂ペースト）を用いて貼り合わせて構成された
ものであり、平面状のフィルムリード５ｄと略り字形フ
ィルムリード５ａのインナーリード５ｃの一部が、それ
ぞれが異なるバンプ６を介して半導体装置ｌと接続され
たものである。このように構成しても、前記第１の実施
例と同様の効果を奏する。The film lead 5a has a flat film lead 5d attached to the abbreviated film lead 5a in the first and second embodiments, and a conductive material 9 (
The planar film lead 5d and a part of the inner lead 5c of the abbreviated film lead 5a are connected to the semiconductor device through different bumps 6, respectively. It is connected to l. Even with this configuration, the same effects as in the first embodiment can be achieved.
第５図は、本発明の第４の実施例を示すもので、前記第
３の実施例において、平面状のフィルムリード５ｄを、
半導体装置Ｉの画電極バンプ６と接続させたもので、前
記平面状のフィルムリード５ｄを、略り字形フィルムリ
ードの半導体装置１に面した側に導電性材料９（半田、
導電性接着剤等）を用いて貼り合わせて構成されたもの
である。本構成においても、前記第１の実施例と同様の
効果を奏する。FIG. 5 shows a fourth embodiment of the present invention. In the third embodiment, a planar film lead 5d is
The planar film lead 5d is connected to the picture electrode bump 6 of the semiconductor device I, and a conductive material 9 (solder,
It is constructed by bonding them together using a conductive adhesive (such as a conductive adhesive). This configuration also provides the same effects as the first embodiment.
第６図は、本発明の第５の実施例を示すもので、前記第
１の実施例と異なる点は、フィルムリード５ａのみであ
り、他は前記第２の実施例と同じである。FIG. 6 shows a fifth embodiment of the present invention, which differs from the first embodiment only in the film lead 5a, and is otherwise the same as the second embodiment.
フィルムリード５ａは、一端で略折り返され、その後、
さらに略垂直に曲げられて略丁字形の形状とされたもの
で、半導体装置１を基板２より突出させる際に用いられ
る０本構成においても、前記第１の実施例と同様の効果
を奏する。The film lead 5a is approximately folded back at one end, and then
Furthermore, even in a configuration in which the semiconductor device 1 is bent approximately vertically to have a substantially T-shape and there is no structure used when the semiconductor device 1 is made to protrude from the substrate 2, the same effects as in the first embodiment can be obtained.
第７図は、本発明による半導体装置１を、電子部品等の
搭載される基板であるプリント配線基板２に実装した一
例を示すものである。FIG. 7 shows an example in which the semiconductor device 1 according to the present invention is mounted on a printed wiring board 2, which is a board on which electronic components and the like are mounted.
なお、上記各実施例において、半導体装置１を封止する
際に、実装された半導体装置１の外側や、フィルムリー
ド５ａの外側に放熱板を接着して封止し、放熱を良くし
たものであっても良い。In each of the above embodiments, when sealing the semiconductor device 1, a heat sink is bonded to the outside of the mounted semiconductor device 1 and the outside of the film lead 5a to improve heat radiation. It's okay to have one.
（発明の効果〕
本発明の実装構造によれば、半導体装置を基板に対して
縦向きに実装し、半導体装置の縦、横で定まる面の面積
よりもはるかに小さい面積を有する側面を基板に対向さ
せているため、基板上の半導体装置の実装専有面積は非
常に小さくなり、部品の実装回度が向上する。また、基
板に設けた孔又は凹状の半導体装置保持部に、半導体装
置を挿入することにより、その実装高さも低くなる。こ
のため、半導体装置を実装する基板の面積を小さくする
ことができ、さらには、その基板を内蔵した製品の小型
化が図れる。(Effects of the Invention) According to the mounting structure of the present invention, a semiconductor device is mounted vertically on a substrate, and a side surface having a much smaller area than the surface area determined by the length and width of the semiconductor device is mounted on the substrate. Because they are placed facing each other, the area occupied by the semiconductor device on the board for mounting becomes extremely small, increasing the number of times components can be mounted.In addition, the semiconductor device is inserted into the hole provided in the board or the recessed semiconductor device holding part. By doing so, the mounting height is also reduced.Therefore, the area of the board on which the semiconductor device is mounted can be reduced, and furthermore, the product incorporating the board can be made smaller.
第１図は本発明の第１の実施例を示す一部断面側面図、
第２図（ａ）〜（ｆ）は同上の製造方法を示すもので、
（ａ）は平面図、Φ）〜（ｆ）は一部断面側面図、第３
図は本発明の第２の実施例を示す一部断面側面図、第４
図は本発明の第３の実施例を示す一部断面側面図、第５
図は本発明の第４の実施例を示す一部断面側面図、第６
図は本発明の第５の実施例を示す一部断面側面図、第７
図は本発明の半導体装置の実装例の斜視図、第８図は半
導体装置の従来の実装構造を示す一部断面側面図、第９
図は従来の別の実装構造を示す一部断面側面図である。
１−半導体装Ｉ ２一基板
２ａ−一半導体装置保持部 ３−導体リード５ａ−フィ
ルムリードFIG. 1 is a partially sectional side view showing a first embodiment of the present invention;
Figures 2 (a) to (f) show the same manufacturing method as above,
(a) is a plan view, Φ) to (f) are partially sectional side views,
The figure is a partially sectional side view showing the second embodiment of the present invention;
The figure is a partially sectional side view showing the third embodiment of the present invention, and the fifth figure is a side view showing a third embodiment of the present invention.
The figure is a partially sectional side view showing a fourth embodiment of the present invention, and a sixth embodiment.
The figures are a partially sectional side view showing a fifth embodiment of the present invention, and a seventh embodiment.
9 is a perspective view of a mounting example of a semiconductor device according to the present invention, FIG. 8 is a partially sectional side view showing a conventional mounting structure of a semiconductor device, and FIG.
The figure is a partially sectional side view showing another conventional mounting structure. 1-Semiconductor device I 2-Substrate 2a-1 Semiconductor device holding part 3-Conductor lead 5a-Film lead
Claims (1)
導体装置保持部を設けると共に、該半導体保持部に、半
導体装置を基板に対して略垂直になるように挿入し、該
半導体装置と基板上の導体リードを略Ｌ字形に成形され
たフィルムリードにより接続したことを特徴とする半導
体装置の実装構造。(1) A hole or concave semiconductor device holding portion is provided in the substrate on which the semiconductor device is mounted, and the semiconductor device is inserted into the semiconductor holding portion so as to be substantially perpendicular to the substrate. A mounting structure for a semiconductor device, characterized in that conductor leads on a substrate are connected by film leads formed into a substantially L-shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2137766A JP2705281B2 (en) | 1990-05-28 | 1990-05-28 | Semiconductor device mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2137766A JP2705281B2 (en) | 1990-05-28 | 1990-05-28 | Semiconductor device mounting structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0430545A true JPH0430545A (en) | 1992-02-03 |
| JP2705281B2 JP2705281B2 (en) | 1998-01-28 |
Family
ID=15206332
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2137766A Expired - Lifetime JP2705281B2 (en) | 1990-05-28 | 1990-05-28 | Semiconductor device mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2705281B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001094227A (en) * | 1999-09-20 | 2001-04-06 | Shinko Electric Ind Co Ltd | Semiconductor chip mounting wiring board and semiconductor chip mounting method using the board |
| US6409705B1 (en) | 1997-08-07 | 2002-06-25 | Noboro Hakozaki | Needle protecting cap and needle disposal instrument |
-
1990
- 1990-05-28 JP JP2137766A patent/JP2705281B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6409705B1 (en) | 1997-08-07 | 2002-06-25 | Noboro Hakozaki | Needle protecting cap and needle disposal instrument |
| JP2001094227A (en) * | 1999-09-20 | 2001-04-06 | Shinko Electric Ind Co Ltd | Semiconductor chip mounting wiring board and semiconductor chip mounting method using the board |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2705281B2 (en) | 1998-01-28 |
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