CN109755197A - Encapsulating structure and forming method thereof - Google Patents
Encapsulating structure and forming method thereof Download PDFInfo
- Publication number
- CN109755197A CN109755197A CN201910031762.0A CN201910031762A CN109755197A CN 109755197 A CN109755197 A CN 109755197A CN 201910031762 A CN201910031762 A CN 201910031762A CN 109755197 A CN109755197 A CN 109755197A
- Authority
- CN
- China
- Prior art keywords
- face
- chip
- radiating part
- substrate
- loading end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
Abstract
A kind of encapsulating structure and forming method thereof, wherein encapsulating structure includes: substrate, and the substrate includes loading end, and the loading end surface of the substrate is fixed with several passive devices；It is fixed at least one chip on the loading end surface of the substrate, the chip and passive device are mutually discrete, and the chip includes opposite the first face and the second face, first face and base plate carrying face contact；It is fixed on the solder layer in the second face of chip；The radiator structure being fixed in substrate, the radiator structure includes the second radiating part positioned at loading end surface and the first radiating part at the top of the second radiating part, the first radiating part of part is contacted with solder layer, for second radiating part between chip and passive device, second radiating part surrounds at least one chip.The better performances of the encapsulating structure.
Description
Technical field
The present invention relates to semiconductor fields more particularly to a kind of encapsulating structure and forming method thereof.
Background technique
With the continuous development of integrated circuit technique, electronic product is increasingly to miniaturization, intelligence, high-performance and height
Reliability direction is developed.And integrated antenna package not only directly affects the performance of integrated circuit, electronic module or even complete machine, and
And also restrict miniaturization, low cost and the reliability of entire electronic system.It gradually reduces, integrates in IC wafers size
In the case that degree is continuously improved, electronics industry proposes increasingly higher demands to integrated antenna package technology.
However, the performance of existing encapsulating structure is poor.
Summary of the invention
The technical problem to be solved by the present invention is to provide a kind of encapsulating structures and forming method thereof, to improve the property of encapsulating structure
Energy.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of forming method of encapsulating structure, comprising: provide base
Plate, the substrate include loading end, and the loading end surface of the substrate is fixed with several passive devices；In holding for the substrate
At least one chip is fixed on section surface, and the chip and passive device are mutually discrete, and the chip includes the first opposite face
With the second face, first face and base plate carrying face contact；In the fixed solder layer in the second face of chip；In the carrying of the substrate
Radiator structure is fixed on face, the radiator structure includes positioned at second radiating part on loading end surface and positioned at the second radiating part top
First radiating part on portion surface, part first radiating part are contacted with solder layer, and second radiating part surrounds at least one
The chip, and second radiating part is between chip and passive device；The fixed heat dissipation on the loading end of the substrate
After structure, melt process is carried out to solder layer.
Optionally, the material of the solder layer is metal；The material of the solder layer includes tin-lead, silver or copper.
Optionally, the first face of the chip has salient point；After the loading end surface fixed chip of the substrate, institute
State salient point and base plate carrying face contact；The forming method of the encapsulating structure further include: formed after the salient point, form solder
Before layer, bottom filler is formed in the chip first side, the bottom filler surrounds the salient point.
Optionally, second radiating part bottom and base plate carrying face are by pasting glue connection.
Optionally, the passive device includes: one of resistance, capacitor, inductance or multiple combinations.
Optionally, the material of first radiating part includes copper；The material of second radiating part includes copper.
Optionally, the substrate further includes the non-bearing face opposite with loading end；There is electric interconnection structure in the substrate,
The electric interconnection structure includes first end face and second end face, and the loading end exposes first end face, the first end face with
Bump contacts, the non-bearing face expose second end face.
Optionally, further includes: form soldered ball on the surface in the non-bearing face, the soldered ball is contacted with second end face.
Correspondingly, the present invention also provides a kind of encapsulating structures, comprising: substrate, the substrate include loading end, the substrate
Loading end surface be fixed with several passive devices；It is fixed at least one chip on base plate carrying face surface, it is described
Chip is mutually discrete with passive device, and the chip includes opposite the first face and the second face, first face and base plate carrying
Face contact；It is fixed on the solder layer in second face of chip；The radiator structure being fixed on base plate carrying face, the radiator structure
The second radiating part including being located at loading end surface and the first radiating part at the top of the second radiating part, the first radiating part of part
It is contacted with solder layer, second radiating part is between chip and passive device, and second radiating part surrounds a core
Piece.
Optionally, projection of shape of second radiating part on base plate carrying face surface includes: round, rectangle or just
It is rectangular.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that
In the encapsulating structure that technical solution of the present invention provides, the radiator structure is used to discharge the heat generated in chip
It goes out.The radiator structure includes the first heat dissipation positioned at second radiating part on loading end surface and at the top of the second radiating part
Portion.Since second radiating part is between chip and passive device, when subsequent melt solder layer, described second dissipates
Hot portion can prevent the solder layer sputtering of materials of melting to be therefore beneficial to prevent solder layer to passive device and passive device is sent out
Raw bridge joint is beneficial to prevent chip and short circuit occurs, improves the performance of encapsulating structure.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of encapsulating structure；
Fig. 2 to Fig. 6 is the structural schematic diagram of each step of one embodiment of forming method of encapsulating structure of the present invention.
Specific embodiment
As described in background, the performance of encapsulating structure is poor.
Fig. 1 is a kind of structural schematic diagram of encapsulating structure.
Referring to FIG. 1, providing substrate 100, the substrate 100 includes loading end (not marking in figure), the loading end
Surface is fixed with passive device 102；Chip 101, the chip 101 and passive device 102 are formed on the surface of the loading end
Mutually discrete, the chip 101 includes opposite the first face 1 and the second face 2, and the first face 1 of the chip 101 has salient point
105, the salient point 105 and carrying face contact；In the fixed solder layer 103 in 101 second face 2 of chip；The fixed solder layer
After 103, the radiator structure 104 for surrounding the passive device 102 and chip 101, part institute are formed on the loading end surface
Radiator structure 104 is stated to contact with solder layer 103；It is formed after the radiator structure 104, the solder layer 103 is melted
Processing.
In above-mentioned encapsulating structure, due to without hindrance block material between the chip 101 and passive device 102, then to solder layer 103
Carry out melt process when, the material of solder layer 103 easily splashes to passive device 102, make solder layer 103 easily with passive device 102
It bridges, then short circuit easily occurs for chip 101, is unfavorable for improving the performance of encapsulating structure.
In order to solve the above technical problems, technical solution of the present invention provides a kind of encapsulating structure, comprising: the substrate includes holding
Section, the loading end surface are fixed with several passive devices；It is fixed at least one core on base plate carrying face surface
Piece, the chip and passive device are mutually discrete, and the chip includes opposite the first face and the second face, and the first of the chip
Face and base plate carrying face contact；Solder layer positioned at second face of chip；Radiator structure on substrate, the heat dissipation knot
Structure includes the first radiating part and the second radiating part positioned at the first radiating part surface, and the first radiating part of part is contacted with solder layer,
Second radiating part is between chip and passive device, and second radiating part surrounds chip.What the method was formed
The better performances of encapsulating structure.
It is understandable to enable above-mentioned purpose of the invention, feature and beneficial effect to become apparent, with reference to the accompanying drawing to this
The specific embodiment of invention is described in detail.
Fig. 2 to Fig. 6 is the structural schematic diagram of each step of one embodiment of forming method of encapsulating structure of the present invention.
Referring to FIG. 2, providing substrate 200, the substrate 200 includes loading end 13,200 loading end of substrate, 13 surface
It is fixed with several passive devices 250.
The substrate 200 further includes the non-bearing face 14 opposite with loading end 13；Have in the substrate 200 and knot is electrically interconnected
Structure (does not mark) in figure, and the electric interconnection structure includes first end face (not marking in figure) and second end face (not marking in figure),
The loading end 13 exposes first end face, the bump contacts of the first end face and subsequent chip first side, the non-bearing
Face 14 exposes second end face.
The electric interconnection structure includes: the first insulating layer (not marking in figure), the first wiring in the first insulating layer
Layer 201, first insulating layer exposing go out the top surface of the first wiring layer of part 201, what first insulating layer exposing went out
The top surface of first wiring layer 201 is first end face；The electric interconnection structure further include second insulating layer and be located at second
The second wiring layer 202 in insulating layer, the top surface for the second wiring layer 202 that the second insulating layer exposes are second end
Face；The electric interconnection structure further includes the plug (not marking in figure) for connecting the first wiring layer 201 and the second wiring layer 202.
The bump contacts of the first end face and subsequent chip first side.The second end face is connect with soldered ball 203.
The material of first wiring layer 201 is metal, and the material of first wiring layer 201 includes copper.Described first
The bump contacts of wiring layer 201 and chip first side are conducive to substrate 200 and are electrically connected with the realization of subsequent chip.
The material of second wiring layer 202 is metal, and the material of second wiring layer 202 includes copper.Described second
Wiring layer 202 and soldered ball 203 are conducive to the electric signal output in substrate 200.
The material of the plug is metal, and the plug is for making the first wiring layer 201 and 202 electricity of the second wiring layer mutually
Even.
The loading end 13 of the substrate 200 is for fixing passive device 250 and subsequent chip.The passive device 250
It include: one of resistance, capacitor, inductance or multiple combinations.
Referring to FIG. 3, fixing at least one chip 204, the chip on the surface of the loading end 13 of the substrate 200
204 is mutually discrete with passive device 250, and the chip 204 includes opposite the first face 11 and the second face 12, first face 11
It is contacted with the loading end 13 of substrate 200.
First face 11 of the chip 204 also has salient point 205, and the salient point 205 is contacted with first end face, is conducive to core
Piece 204 is electrically connected with the realization of substrate 200.
It is formed after the salient point 205, further includes: bottom filler 206 is formed in the first face 11 of the chip 204, it is described
Bottom filler 20 surrounds salient point 205, and exposes the top surface of salient point 205, is conducive to subsequent salient point 205 and is electrically connected with first end face
It connects.Shear stress caused by the bottom filler 206 is used to alleviate between chip 204 and substrate 200 because of coefficient of thermal expansion differences.
Second face 12 of the chip 204 is for fixing subsequent solder layer.
The chip 201 is also easy to produce heat in the process of work, the heat by subsequent radiator structure discharge to
It is extraneous.
Referring to FIG. 4, in the fixed solder layer 207 in the second face 12 of the chip 204.
The solder layer 207 is metal.In the present embodiment, the material of the solder layer 207 is tin-lead.In other implementations
In example, the material of the solder layer includes silver or copper.
It is subsequent that melt process is carried out to the solder layer 207, it is fused together chip 204 and radiator structure, so that institute
The heat for stating the generation of chip 204 can be discharged by radiator structure, be conducive to the reliability for improving encapsulating structure.
Fig. 5 and Fig. 6 are please referred to, Fig. 6 is the schematic diagram of the section structure of the Fig. 5 along X-X1, and Fig. 5 is section knot of the Fig. 6 along Y-Y1
Structure schematic diagram forms radiator structure (not marking in figure) on the loading end 13, and the radiator structure includes being located at loading end
The second radiating part 208b on 13 surfaces and the first radiating part 208a at the top of the second radiating part 208b, the first radiating part of part
208a is contacted with solder layer 207, and the second radiating part 208b surrounds at least one chip 204, and second radiating part
208b is between chip 204 and passive device 250.
The material of the first radiating part 208a includes: copper, and the first radiating part 208a passes through solder layer 207 and chip
204 connections are conducive to radiator structure for the heat release in chip 204 to the external world.Also, the first radiating part 208a and the external world
Contact area it is larger so that the first radiating part 208a is stronger to the heat-sinking capability of chip 204.
The material of the second radiating part 208b includes: copper.The second radiating part 208b is located at chip 204 and passive list
Between member 250, and the second radiating part 208b surrounds chip 204, then when subsequent progress melt process, although the solder layer
207 easily splash, still, since the second radiating part 208b is between chip 204 and passive unit 250, so that splash
Solder layer 207 is not easy to splash to passive unit 250, therefore, is beneficial to prevent between solder layer 207 and passive unit 250 and occurs
Bridge joint, prevents chip 204 from short circuit occurs, and is conducive to the performance for improving encapsulating structure.
In the present embodiment, the second radiating part 208b is projected as circle on substrate 200.In other embodiments
In, second radiating part is projected as rectangle, square or polygon on substrate.
The forming method of the encapsulating structure further include: form glue between the second radiating part 208b and substrate 200
260。
The glue 260 for realizing the second radiating part 208b and substrate 200 connection.
It is formed after the radiator structure, further includes: melt process is carried out to solder layer 207.
After carrying out melt process to the solder layer 207, the first radiating part 208a is fused together with solder layer 207,
Be conducive to the first radiating part 208a to discharge the heat that chip 204 generates.Also, the first radiating part 208a and the external world
Contact area it is larger, be conducive to improve radiator structure it is stronger to the releasability of heat in chip 204.
Also, during the fusion weld bed of material 207, although solder layer 207 easily splashes, due to second dissipate
Hot portion 208b is between chip 204 and passive device 250, and the second radiating part 208b surrounds chip 204, so that splashing
Solder layer 207 be difficult to splash to passive device 250, therefore, be beneficial to prevent between solder layer 207 and passive device 250 and send out
Raw bridge joint, prevents chip 204 from short circuit occurs, improves the performance of encapsulating structure.
Correspondingly, the present invention also provides a kind of encapsulating structures, referring to FIG. 5, including:
Substrate 200, the substrate 200 include loading end 13, and the surface of the loading end 13 of the substrate 200 is fixed with several
A passive device 250；It is fixed at least one chip 204 on 200 loading end of substrate, 13 surface, the chip 204 and quilt
Dynamic element 250 is mutually discrete, and the chip 204 includes opposite the first face 11 and the second face 12, first face 11 and substrate
200 loading end 13 contacts；
It is fixed on the solder layer 207 in 204 second face 12 of chip；
It is fixed on the radiator structure on 200 loading end of substrate, 13 surface, the radiator structure includes being located at 13 surface of loading end
The second radiating part 208b and the first radiating part 208a at the top of the second radiating part 208b, part the first radiating part 208a with
Solder layer 207 contacts, and the second radiating part 208b is between chip 204 and passive device 250, and second radiating part
208b surrounds at least one chip 204.
Projection of shape of the second radiating part 208b on base plate carrying face surface includes: round, rectangle or pros
Shape.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (10)
1. a kind of forming method of encapsulating structure characterized by comprising
Substrate is provided, the substrate includes loading end, and the loading end surface of the substrate is fixed with several passive devices；
At least one chip is fixed on the loading end surface of the substrate, the chip and the passive device are mutually discrete, institute
Stating chip includes opposite the first face and the second face, first face and base plate carrying face contact；
In the fixed solder layer in the second face of chip；
Radiator structure is fixed on the loading end of the substrate, the radiator structure includes the second heat dissipation positioned at loading end surface
Portion and the first radiating part positioned at the second radiating part top surface, part first radiating part is contacted with solder layer, described
Second radiating part surrounds at least one described chip, and second radiating part is between chip and passive device；
After fixing radiator structure on the loading end of the substrate, melt process is carried out to solder layer.
2. the forming method of encapsulating structure as described in claim 1, which is characterized in that the material of the solder layer is metal；
The material of the solder layer includes tin-lead, silver or copper.
3. the forming method of encapsulating structure as described in claim 1, which is characterized in that the first face of the chip has convex
Point；After the loading end surface fixed chip of the substrate, the salient point and base plate carrying face contact；The shape of the encapsulating structure
At method further include: it is formed after the salient point, is formed before solder layer, form bottom filler in the chip first side, it is described
Bottom filler surrounds the salient point.
4. the forming method of encapsulating structure as described in claim 1, which is characterized in that second radiating part and base plate carrying
Face is by pasting glue connection.
5. the forming method of encapsulating structure as described in claim 1, which is characterized in that the passive device includes: resistance, electricity
One of appearance, inductance or multiple combinations.
6. the forming method of encapsulating structure as described in claim 1, which is characterized in that the material of first radiating part includes
Copper；The material of second radiating part includes copper.
7. the forming method of encapsulating structure as claimed in claim 3, which is characterized in that the substrate further includes and loading end phase
Pair non-bearing face；There is electric interconnection structure, the electric interconnection structure includes first end face and second end face, institute in the substrate
It states loading end and exposes first end face, the first end face and bump contacts, the non-bearing face exposes second end face.
8. the forming method of encapsulating structure as claimed in claim 7, which is characterized in that further include: in the non-bearing face
Surface forms soldered ball, and the soldered ball is contacted with second end face.
9. a kind of encapsulating structure formed such as any one of claim 1 to claim 8 method characterized by comprising
Substrate, the substrate include loading end, and the loading end surface of the substrate is fixed with several passive devices；
It is fixed at least one chip on base plate carrying face surface, the chip and passive device are mutually discrete, the core
Piece includes opposite the first face and the second face, the first face and the base plate carrying face contact of the chip；
It is fixed on the solder layer in second face of chip；
The radiator structure being fixed on base plate carrying face, the radiator structure include positioned at loading end surface the second radiating part with
And the first radiating part at the top of the second radiating part, the first radiating part of part are contacted with solder layer, second heat dissipation position
Between chip and passive device, and second radiating part surrounds at least one chip.
10. encapsulating structure as claimed in claim 9, which is characterized in that second radiating part is on base plate carrying face surface
Projection of shape includes: round, rectangle or square.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910031762.0A CN109755197A (en) | 2019-01-14 | 2019-01-14 | Encapsulating structure and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910031762.0A CN109755197A (en) | 2019-01-14 | 2019-01-14 | Encapsulating structure and forming method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109755197A true CN109755197A (en) | 2019-05-14 |
Family
ID=66405612
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910031762.0A Pending CN109755197A (en) | 2019-01-14 | 2019-01-14 | Encapsulating structure and forming method thereof |
Country Status (1)
| Country | Link |
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| CN (1) | CN109755197A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110416097A (en) * | 2019-06-12 | 2019-11-05 | 苏州通富超威半导体有限公司 | The encapsulating structure and packaging method for preventing indium metal from overflowing |
| CN110854083A (en) * | 2019-11-22 | 2020-02-28 | 海光信息技术有限公司 | Packaging structure of semiconductor chip and packaging process thereof |
| CN112271170A (en) * | 2020-10-27 | 2021-01-26 | 苏州通富超威半导体有限公司 | Packaging substrate, flip chip packaging structure and manufacturing method thereof |
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| US20080296755A1 (en) * | 2006-02-24 | 2008-12-04 | Fujitsu Limited | Semiconductor device |
| EP2278615A2 (en) * | 2009-07-21 | 2011-01-26 | STMicroelectronics Asia Pacific Pte Ltd. | Semiconductor package with a stiffening member supporting a thermal heat spreader |
| US20110149537A1 (en) * | 2009-12-22 | 2011-06-23 | Shinko Electric Industries Co., Ltd. | Heat-radiating component and electronic component device |
| CN103137574A (en) * | 2011-11-25 | 2013-06-05 | 富士通半导体股份有限公司 | Semiconductor device and method for fabricating the same |
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| CN1901150A (en) * | 2005-07-22 | 2007-01-24 | 国家淀粉及化学投资控股公司 | Process for exposing solder bumps on an underfill coated semiconductor |
| US20080296755A1 (en) * | 2006-02-24 | 2008-12-04 | Fujitsu Limited | Semiconductor device |
| EP2278615A2 (en) * | 2009-07-21 | 2011-01-26 | STMicroelectronics Asia Pacific Pte Ltd. | Semiconductor package with a stiffening member supporting a thermal heat spreader |
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| CN110416097A (en) * | 2019-06-12 | 2019-11-05 | 苏州通富超威半导体有限公司 | The encapsulating structure and packaging method for preventing indium metal from overflowing |
| CN110416097B (en) * | 2019-06-12 | 2021-05-11 | 苏州通富超威半导体有限公司 | Packaging structure and packaging method for preventing indium metal from overflowing |
| CN110854083A (en) * | 2019-11-22 | 2020-02-28 | 海光信息技术有限公司 | Packaging structure of semiconductor chip and packaging process thereof |
| CN110854083B (en) * | 2019-11-22 | 2021-03-23 | 海光信息技术股份有限公司 | Packaging structure of semiconductor chip and packaging process thereof |
| CN112271170A (en) * | 2020-10-27 | 2021-01-26 | 苏州通富超威半导体有限公司 | Packaging substrate, flip chip packaging structure and manufacturing method thereof |
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Application publication date: 20190514 |