CN110854083B - Packaging structure of semiconductor chip and packaging process thereof - Google Patents
Packaging structure of semiconductor chip and packaging process thereof Download PDFInfo
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- CN110854083B CN110854083B CN201911154516.0A CN201911154516A CN110854083B CN 110854083 B CN110854083 B CN 110854083B CN 201911154516 A CN201911154516 A CN 201911154516A CN 110854083 B CN110854083 B CN 110854083B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
- H01L2924/16153—Cap enclosing a plurality of side-by-side cavities [e.g. E-shaped cap]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention provides a semiconductor chip packaging structure and a packaging process thereof. The partition plate is provided with the vent holes, the vent holes in the partition plate correspond to the vent holes formed at the positions where the sealing layer material is not formed below the first heat dissipation structure, and gas generated during the reflow soldering process of the soldering flux can be easily exhausted. Meanwhile, the connected partition plates can fix the packaging substrate, so that the deformation of the large-size substrate in a cold and hot alternating environment is effectively reduced, and the reliability of the packaging structure is improved. The packaging structure and the packaging process can solve the risk of short circuit in the prior art and improve the yield of mass production.
Description
Technical Field
The invention relates to a packaging structure of a semiconductor chip and a packaging process thereof, in particular to a packaging structure of a heat dissipation structure with a partition plate and a packaging process thereof, which can solve the short circuit risk and improve the yield of mass production.
Background
With the continuous development of integrated circuit technology, electronic products are increasingly developing toward miniaturization, intellectualization, high performance and high reliability. The integrated circuit package not only directly affects the performance of the integrated circuit, the electronic module and even the complete machine, but also restricts the miniaturization, low cost and reliability of the whole electronic system.
Bga (ball grid array) packaging products are an important electronic packaging product. The BGA packaging product comprises the following components: the substrate with the chip is provided with solder balls at the bottom. The substrate with the chip needs to be soldered to the motherboard by solder balls. The BGA package product further comprises a heat dissipation cover, and the heat dissipation cover is used for dissipating heat generated in the working process of the BGA package product to the external environment.
Disclosure of Invention
In view of the above, the present invention provides a semiconductor chip package structure and a semiconductor chip package process, which can completely separate a solder heat dissipation layer material from a component on a chip structure. Meanwhile, the clapboard is provided with the vent hole, and the vent hole on the clapboard corresponds to the vent hole formed at the position where the sealing layer material is not formed below the first heat dissipation structure, so that the gas generated by the soldering flux in the reflow soldering process can be easily exhausted. The short circuit risk can be solved, and the yield of mass production is improved.
The technical scheme provided by the invention is as follows:
a package structure, comprising the following structure:
a chip structure and a component on the first surface of the package substrate; the component is positioned at the periphery of the chip structure;
a heat dissipation structure covering the first surface of the package substrate; the chip structure and the component are arranged in a cavity formed by the heat dissipation structure and the packaging substrate;
and a partition plate for blocking the sputtering materials facing to the direction of the components is arranged between the chip structure and the components.
Further, a second surface of the package substrate is provided with solder balls of the BGA, and the second surface is arranged opposite to the first surface.
Furthermore, the package substrate includes an electrical interconnection structure inside the substrate, and the electrical interconnection structure includes a first conductive end surface exposed from the first surface, a second conductive end surface exposed from the second surface, and a conductive plug electrically connecting the first conductive end surface and the second conductive end surface, and the first end surface is electrically connected to the chip structure, and the second conductive end surface is electrically connected to the solder ball.
Further, the top surface of the chip structure is also provided with a heat dissipation layer.
Further, the heat dissipation structure includes a first heat dissipation structure and a second heat dissipation structure, the first heat dissipation structure is in contact with the first surface of the package substrate, the second heat dissipation structure is located on the top of the first heat dissipation structure, and a portion of the second heat dissipation structure is in contact with the heat dissipation layer.
Further, the material of the heat dissipation layer is indium, indium-silver alloy, silver, tin or tin-silver alloy or tin-lead alloy.
Further, the heat dissipation structure is made of a metal heat conduction material, and the metal heat conduction material is copper, iron, aluminum, stainless steel, tungsten, and molybdenum.
Further, the partition plate and the heat dissipation structure are made of the same material, and the partition plate and the heat dissipation structure are integrally formed through stamping or formed through machining and milling.
Further, the partition plate also comprises a vent hole.
Further, the first heat dissipation structure and the partition plate are in contact with the first surface through a sealing layer material, and a position between the first heat dissipation structure and the first surface corresponding to the vent hole is free of the sealing layer material, and a gap formed between the first heat dissipation structure and the first surface at the position is an exhaust hole.
Further, the partition board includes a first partition board around the chip structure and a second partition board connecting the first partition board and the first heat dissipation structure together, the vent hole is a vent channel between adjacent second partition boards, the vent channel is free of corresponding components, and both the first partition board and the second partition board are in contact with the first surface through the sealing layer material.
Furthermore, the number of the vent holes is one or more, the vent holes are distributed on the periphery of the chip and are distributed according to the position of the central axis.
Meanwhile, the invention also discloses a preparation process of the packaging structure, which comprises the following preparation steps:
step S1: providing a packaging substrate; simultaneously providing a heat dissipation structure, wherein the heat dissipation structure is provided with a cavity and a partition plate is arranged in the cavity;
step S2: forming a component on a first surface of a packaging substrate, and attaching a chip structure to the first surface in an inverted manner;
step S3: arranging the heat dissipation structure and the partition plate cover above the packaging substrate, enabling the chip structure and the component to be located in the cavity, enabling the partition plate to surround the periphery of the chip structure, and enabling the chip structure and the component to be separated by the partition plate;
step S4: and (4) performing reflow soldering on the product obtained in the step (S3) in a vacuum environment, wherein the separator can avoid the risk of short circuit of the components.
Further, the package substrate further includes a second surface opposite to the first surface, and after step S4, the method further includes forming solder balls on the second surface.
Further, the heat dissipation structure comprises a first heat dissipation structure used for being in contact with the first surface of the package substrate and a second heat dissipation structure located on the top of the first heat dissipation structure, and a part of the second heat dissipation structure is used for being in contact with the chip structure to be packaged.
Further, the partition plate is located on the inner side of the first heat dissipation structure, and the partition plate is provided with vent holes.
Further, the following steps are included between step S2 and step S3: coating a flux, a heat dissipation layer and a flux three-layer laminated structure on the surface of the chip structure; and then coating a sealing layer material on the first surface, wherein the position of coating the sealing layer material is determined according to the contact positions of the first heat dissipation structure and the partition board with the first surface, and no sealing layer material is coated at the position between the first heat dissipation structure and the first surface corresponding to the vent hole.
Further, after the reflow process in the step S4, the second heat dissipation structure is in contact with the heat dissipation layer.
Furthermore, the heat dissipation structure is made of metal heat conduction materials; the material of the heat dissipation layer is indium, indium-silver alloy, silver, tin-silver alloy or tin-lead alloy.
Further, the partition plate and the heat dissipation structure are integrally formed through stamping or formed through machining and milling.
Further, the partition board includes a first partition board around the chip structure and a second partition board connecting the first partition board and the first heat dissipation structure together, the vent hole is a vent channel between adjacent second partition boards, the vent channel is free of corresponding components, and both the first partition board and the second partition board are in contact with the first surface through the sealing layer material.
Furthermore, the number of the vent holes is one or more, the vent holes are distributed on the periphery of the chip and are distributed according to the position of the central axis.
According to the scheme provided by the invention, the risk of short circuit of the components can be avoided, the reliability of the packaging structure can be improved, and the yield of mass production can be improved.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1A to 1C respectively correspond to a front view (top view) of a package structure, a side view of the package structure and a cross-sectional view of the package structure according to an embodiment of the invention;
FIGS. 2-6 are cross-sectional views corresponding to an encapsulation process in an embodiment of the invention;
fig. 7A to 7C are front views (top views) of package structures with different vent holes according to the present invention.
Reference numerals: 200: a package substrate; 210: a chip structure; 220: a heat dissipation layer; 221: soldering flux; 230: a second heat dissipation structure; 231: a partition plate; 231-1: a first separator; 231-2: a second separator; 232: a first heat dissipation structure; 233: an exhaust hole; 234: a vent hole; 240: a solder ball; 250: a component; 260: sealing layer material
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present invention, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
In the existing heat dissipation cover packaging scheme adopted by high-performance chip packaging, brazing is used as a connecting material between a heat dissipation cover and a chip, although a good heat dissipation effect can be achieved, during subsequent ball-planting, surface mounting and other reflow soldering processes, because the melting point of the brazing material is low, the brazing material can melt, and meanwhile, a soldering flux can be gasified and infiltrate the metal surface, and because the soldering flux generates gas when being heated, the gas can rapidly escape to drive the molten brazing metal material to sputter away, and can possibly sputter onto passive elements around the chip, so that a circuit is short-circuited.
Alternatively, some solutions add a blocking structure to the heat dissipation cover, but in order to facilitate the discharge of gas generated during reflow soldering of the soldering flux, the space between the partition plate and the substrate cannot be sealed, so that the risk of short circuit caused by the soldering material sputtering onto the component in a molten state cannot be completely avoided.
As described above, when the heat dissipation structure and the heat dissipation layer in the conventional package structure are connected, the soldering flux generates gas when heated, and the gas escapes quickly to drive the molten soldering metal material to sputter out, which may sputter onto the passive components around the chip to cause short circuit, and the gas does not escape easily to cause instability of the package structure. The technical solution of the present invention will be described in detail below.
As shown in fig. 1A to 1C, which are a front view (top view), a side view and a cross-sectional view of the package structure of the present invention, the package structure shown in fig. 1A to 1C includes:
the package substrate 200 includes a first surface (upper surface) for carrying a chip structure 210 and a second surface (lower surface) opposite to the first surface, and the package substrate 200 includes a solder ball 240 of BGA on the second surface of the package substrate 200. The package substrate 200 is a PCB or other suitable substrate material, and includes an electrical interconnection structure inside the substrate, where the electrical interconnection structure includes a first conductive end surface exposed from the first surface, a second conductive end surface exposed from the second surface, and a conductive plug electrically connecting the first conductive end surface and the second conductive end surface, and the first conductive end surface is electrically connected to the chip structure 210, and the second conductive end surface is electrically connected to the solder ball 240, where the first conductive end surface, the second conductive end surface, and the conductive plug are all metal materials with good conductive performance, such as copper or tungsten, which are commonly used in the art.
The chip structure 210 and the component 250 are located on the first surface of the package substrate 200, and the component 250 is located around the periphery of the chip structure, the chip structure 210 is a semiconductor chip structure commonly known in the art, and is electrically connected to the first conductive end face on the first surface through a bump contact on the surface, so as to implement conduction of an electrical signal. The components 250 may be one or more combinations of resistors, capacitors, or inductors, and the components also transmit electrical signals through the conductive interconnect structure.
The surface of the chip structure 210 has a heat dissipation layer 220, which is made of indium, indium-silver alloy, silver, tin-silver alloy, or tin-lead alloy. Because the chip structure is easy to generate heat in the working composition, the generated heat can be released to the outside through the heat dissipation layer and the heat dissipation structure described later, and the chip structure is prevented from being adversely affected due to overhigh temperature. Through the melting treatment of the heat dissipation layer, the chip and the heat dissipation structure are in melting contact, so that the heat generated by the chip structure 210 is conveniently released out through the heat dissipation structure, and the reliability of the packaging structure is improved.
The package structure further includes a heat dissipation structure, the heat dissipation structure includes a first heat dissipation structure 232 contacting the first surface of the package substrate 200 and a second heat dissipation structure 230 located on top of the first heat dissipation structure 232, and a portion of the second heat dissipation structure 230 contacts the heat dissipation layer 220. The heat dissipation structure further includes a partition 231 inside the heat dissipation structure, the partition 231 surrounds the periphery of the chip structure 210, the partition 231 is located between the first heat dissipation structure 232 and the chip structure 210, the partition 231 partitions the chip structure 210 from the component 250, and the partition has a vent 234. Because the chip structure and components and parts are separated to the baffle structure, can prevent that the heat dissipation layer in chip structure top from at the reflow soldering in-process, on a large amount of gas that volatilize can carry fused heat dissipation material to sputter components and parts surface, can prevent the short circuit risk of components and parts structure. And the baffle structure has a vent hole to enable the generated gas to be discharged, the specific structure of which will be further described later.
The partition 231 is made of the same material as the heat dissipation structure, and the partition and the heat dissipation structure are integrally formed by punching or formed by machining and milling, can be changed according to the size and shape of components and chips in the cavity, and can adapt to different types of chips and components. And the heat dissipation structure and the separator are made of metal heat conduction materials, wherein the metal heat conduction materials can be copper, iron, aluminum, stainless steel, tungsten and molybdenum which are commonly used in the field.
As shown in fig. 1C, the first heat dissipation structure 232 and the spacer 231 are both in contact with the first surface through the sealing layer material 260, and compared with a heat dissipation structure without a spacer, the contact area between the heat dissipation structure and the first surface of the package substrate 200 can be increased, so that the bonding firmness between the heat dissipation structure and the package substrate can be increased, the deformation of the package substrate under the condition of temperature change can be effectively reduced, and the reliability of the product can be further improved. As shown in fig. 1A to 1B, the partition 231 includes a first partition 231-1 surrounding the chip structure and a second partition 231-2 connecting the first partition 231-1 and the first heat dissipation structure 232 together, the vent 234 is a vent channel between adjacent second partitions 231-2, the vent channel is not provided with the corresponding component, and both the first partition 231-1 and the second partition 231-2 are in contact with the first surface through the sealing layer material. That is, the baffle structure formed by the first partition 231-1 and the second partition 231-2 can sufficiently separate the component from the chip structure, so that the sputtered conductive material does not cause short circuit of the component. As shown in fig. 7A to 7C, the number of the vent holes on the partition plates may be set to one or more (the vent holes are all the vent channels between the adjacent second partition plates 231-2, and the first partition plate 231-1 is around the chip structure), distributed on the periphery of the chip, and are distributed according to the position of the central axis, and the figures only show the case of two or four vent holes, such as vent holes formed on two opposite sides, or vent holes are arranged on the four sides, or vent holes are arranged on the four corners (or vent holes are arranged on only two corners, not shown), vent holes at different positions are arranged, different product requirements can be met, vent holes can be arranged at different positions according to different product design requirements, and the number and the arrangement mode of the vent holes can meet the requirements of preventing short circuit of components and parts and exhausting. Further, the sealing material 260 is not disposed at the position between the first heat dissipation structure 232 and the first surface corresponding to the position of the vent hole, and the gap between the first heat dissipation structure and the first surface is formed as the vent hole 233, so that the gas generated in the reflow soldering process of the chip structure can be exhausted through the vent hole and then exhausted through the vent hole, and thus the generated gas does not affect the package structure. Because the position of the vent hole corresponds to the position of the exhaust hole, the generated gas can be quickly exhausted, and the packaging structure is prevented from being adversely affected by overlarge pressure of the gas generated in the packaging structure.
The process for fabricating the package structure is described in detail below with reference to fig. 2-6. As shown in fig. 2, a package substrate 200 is first provided, where the package substrate 200 has a first surface (upper surface) for carrying a chip structure 210 and other devices and a second surface (lower surface) opposite to the first surface, and solder balls 240 for BGA are subsequently formed on the second surface of the package substrate 200. The package substrate 200 is a PCB or other suitable substrate material, and includes an electrical interconnection structure inside the substrate, where the electrical interconnection structure includes a first conductive end surface exposed from the first surface, a second conductive end surface exposed from the second surface, and a conductive plug electrically connecting the first conductive end surface and the second conductive end surface, the first conductive end surface is electrically connected to the chip structure 210 formed above the first conductive end surface, the second conductive end surface is electrically connected to the subsequently formed BGA solder ball 240, and the first conductive end surface, the second conductive end surface, and the conductive plug are all metal materials with good electrical conductivity, such as copper or tungsten commonly used in the art.
Meanwhile, a heat dissipation structure (a heat dissipation structure is not separately shown, and is also shown in fig. 4 when the heat dissipation structure and the chip structure are packaged) is provided, the heat dissipation structure includes a first heat dissipation structure 232 for contacting the first surface of the package substrate and a second heat dissipation structure 230 located on the top of the first heat dissipation structure, and a portion of the second heat dissipation structure 230 is used for contacting the heat dissipation layer above the chip structure to be packaged; the heat dissipation structure is internally provided with a partition plate, the partition plate is positioned on the inner side of the first heat dissipation structure, and the partition plate is provided with a vent hole; the partition 231 is made of the same material as the heat dissipation structure, and the partition and the heat dissipation structure are integrally formed by punching or formed by machining and milling, can be changed according to the size and shape of components and chips in the cavity, and can adapt to different types of chips and components. And the heat dissipation structure and the separator are made of metal heat conduction materials, wherein the metal heat conduction materials can be copper, iron, aluminum, stainless steel, tungsten and molybdenum which are commonly used in the field.
Continuing with fig. 2, the chip structure 210 and the component 250 are attached to the package substrate 200, wherein the component 250 may be one or a combination of resistors, capacitors, or inductors, the chip structure 210 is electrically connected to the exposed first conductive end surface of the first surface through bump contacts, and the component 250 also transmits electrical signals through the conductive interconnection structure. The chip structure is attached to the first surface in a flip-chip manner, and the specific attachment manner is not further limited herein.
Then as shown in fig. 3, sequentially coating a flux 221, a heat dissipation layer 220 and a flux 221 on the chip structure 210, wherein the upper and lower layers of flux can make the heat dissipation layer, the chip and the heat dissipation structure formed thereon better melt and connect together, and the material of the heat dissipation layer is indium, indium-silver alloy, silver, tin or tin-silver alloy or tin-lead alloy; the material of the flux is a flux material commonly known in the art, and different flux materials can be selected according to different metal materials of the heat dissipation layer, which is not further limited herein. Then, depending on the first heat dissipation structure and the position of contact of the flange of the separator with the first surface, the sealing layer material 260 is applied on the first surface, and the sealing layer material 260 is not applied at the position of the corresponding vent hole, that is, the corresponding vent hole to be formed later. The sealing layer material used is different for different packaged products, and may be a conductive or insulating material, including but not limited to polymer, rubber, or metal resin glue.
And then, a prepared heat dissipation structure is attached to the structure coated with the soldering flux and the sealing layer material as shown in fig. 3, the heat dissipation structure is attached to the sealing layer material of the packaging substrate, an accurate attachment position and attachment flatness are ensured in the attachment process, and the sealing layer material and the material layer on the chip structure are uniformly combined, so that heat dissipation is facilitated. In the package structure after the bonding, as shown in fig. 4, the spacer 231 is located inside the first heat dissipation structure 232 and surrounds the periphery of the chip structure, and the chip structure 210 and the component 250 are separated by the spacer 231. The first heat dissipation structure 232 has a certain gap with the first surface at a position without the sealing layer material, so as to form an exhaust hole, and rapidly exhaust the gas generated inside (as shown in fig. 1B, an exhaust hole 233 is formed at a position without the sealing layer material below the first heat dissipation structure 232). Meanwhile, due to the existence of the partition plates (the first partition plate and the second partition plate are in bonding contact with the first surface through the sealing layer material), compared with a heat dissipation structure without the partition plates, the contact area between the heat dissipation structure and the first surface of the packaging substrate 200 can be increased, on one hand, the bonding firmness between the heat dissipation structure and the packaging substrate can be increased, on the other hand, the deformation amount of the packaging substrate under the condition of temperature change can be effectively reduced, and the reliability of a product is further improved.
Then, as shown in fig. 5, a high-temperature reflow soldering process is performed on the attached product in a vacuum environment, the soldering flux activates the metal surface to promote soldering, and the heat dissipation layer 220 is soldered to the second heat dissipation structure 230, so that the chip structure 210 and the heat dissipation structure are connected together, and heat generated by the chip structure 210 can be released through the heat dissipation structure, which is beneficial to improving the reliability of the package structure. However, the flux is easily decomposed and releases gas during the high-temperature reflow soldering process, so that bubbles are easily formed in the heat dissipation layer 220, when the bubbles escape outwards, the metal of the heat dissipation layer is sputtered, and the sputtered metal heat dissipation layer is attached to peripheral components, thereby causing short circuit and affecting the performance and reliability of the packaged device. The partition structure provided by the invention is positioned between a component and a chip structure, and can well block a sputtered metal heat dissipation layer, the partition 231 comprises a first partition 231-1 around the chip structure and a second partition 231-2 connecting the first partition 231-1 and the first heat dissipation structure 232 together, the vent 234 is a vent channel between the adjacent second partitions 231-2, and the vent channel is not provided with a corresponding component, so that a sputtered conductive material cannot cause short circuit of the component. Both the first separator 231-1 and the second separator 231-2 are in contact with the first surface through the sealing layer material, so that the contact area of adhesion can be increased. The number of the vent holes on the partition board can be set to one or more (the vent holes are all vent channels between the adjacent second partition boards 231-2, and the first partition boards 231-1 are around the chip structure), and are distributed on the periphery of the chip and distributed according to the position of the central shaft, the figure only shows the situation of two or four vent holes, for example, vent holes are formed on two opposite sides, or vent holes are formed on four corners (or vent holes are formed only on two corners, not shown), the arrangement of vent holes at different positions can meet different product requirements, vent holes can be arranged at different positions according to different product design requirements, and the number and the arrangement mode of the vent holes can meet the requirements of preventing short circuit of components and exhausting.
Because the existence of the vent hole, the gas that produces in the reflow soldering technology can be discharged from around the chip fast, there is not sealing material in the position between first heat radiation structure and the first surface of position department corresponding to the vent hole, be formed with the exhaust hole 233 in this department, can make the gas that produces discharge through the vent hole again after discharging, the gas that produces just so can not produce the influence to packaging structure, because the position of vent hole corresponds with the position of exhaust hole, the gas that produces of can discharging fast, prevent that the inside gaseous pressure intensity of producing of packaging structure from too big produces adverse effect to packaging structure. Meanwhile, as the reflow soldering process is carried out in a vacuum environment, the outside and the inside have pressure difference, and the generated gas is more favorably discharged.
Finally, as shown in fig. 6, solder balls of the BGA are formed on the second surface of the package substrate 200, and the solder balls are electrically connected to the second conductive end surface of the second surface of the package substrate, thereby completing the preparation of the package structure.
The packaging structure provided by the invention is characterized in that in the cavity of the heat dissipation structure, the brazing heat dissipation layer material on the chip structure and the components are completely separated by adding the partition board which is made of the same material as the heat dissipation structure and is connected with the substrate, so that the risk of short circuit caused by sputtering the brazing heat dissipation layer material on the components in the packaging process is avoided, the partition board is provided with the vent holes, the partition board comprises the first partition board around the chip structure and the second partition board which connects the first partition board and the first heat dissipation structure together, the vent holes are vent channels between the adjacent second partition boards, the vent holes on the partition board correspond to the vent holes which are formed at the positions where the sealing layer material is not formed below the first heat dissipation structure, gas generated in the process of flux reflow soldering can be rapidly exhausted, and the reflow soldering process is carried out in a vacuum environment, is beneficial to the discharge of gas. Meanwhile, due to the design of the packaging structure, the partition plate can fix the packaging substrate, the bonding area of the heat dissipation structure and the packaging substrate is increased, the bonding firmness of the heat dissipation structure and the packaging substrate can be increased, the deformation of the packaging substrate under the temperature change condition can be effectively reduced, and the reliability of a product is further improved. Therefore, the packaging structure and the packaging process can solve the risk of short circuit in the prior art and improve the yield of mass production.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (13)
1. A package structure, comprising:
a chip structure and a component on the first surface of the package substrate; the component is positioned at the periphery of the chip structure;
a heat dissipation structure covering the first surface of the package substrate; the chip structure and the component are arranged in a cavity formed by the heat dissipation structure and the packaging substrate;
a partition plate for blocking materials sputtered in the direction towards the component is arranged between the chip structure and the component;
the top surface of the chip structure is also provided with a heat dissipation layer, the heat dissipation structure comprises a first heat dissipation structure and a second heat dissipation structure, the first heat dissipation structure is in contact with the first surface of the package substrate, the second heat dissipation structure is positioned at the top of the first heat dissipation structure, part of the second heat dissipation structure is in contact with the heat dissipation layer, the partition plate further comprises an air vent, the first heat dissipation structure and the partition plate are in contact with the first surface through a sealing layer material, no sealing layer material is arranged at a position between the first heat dissipation structure and the first surface corresponding to the air vent, and a gap formed between the first heat dissipation structure and the first surface at the position is an air vent; the partition board comprises a first partition board around the chip structure and a second partition board connecting the first partition board and the first heat dissipation structure together, the vent hole is a vent channel between the adjacent second partition boards, the vent channel is not provided with the corresponding component, and the first partition board and the second partition board are both in contact with the first surface through the sealing layer material.
2. The package structure of claim 1, wherein a second surface of the package substrate has solder balls of the BGA, the second surface being opposite the first surface.
3. The package structure of claim 2, wherein the package substrate comprises an electrical interconnection structure inside the substrate, and the electrical interconnection structure comprises a first conductive end surface exposed from the first surface, a second conductive end surface exposed from the second surface, and a conductive plug electrically connecting the first conductive end surface and the second conductive end surface, and the first conductive end surface is electrically connected to the chip structure, and the second conductive end surface is electrically connected to the solder ball.
4. The package structure of claim 1, wherein the material of the heat dissipation layer is indium, indium-silver alloy, silver, tin or tin-silver alloy or tin-lead alloy.
5. The package structure according to claim 1, wherein the material of the heat dissipation structure is a metal heat conduction material, and the metal heat conduction material is copper, iron, aluminum, stainless steel, tungsten, or molybdenum.
6. The package structure according to claim 5, wherein the spacer and the heat dissipation structure are made of the same material, and the spacer and the heat dissipation structure are integrally formed by stamping or machining.
7. The package structure of claim 1, wherein the one or more vent holes are distributed around the periphery of the chip and are distributed according to the central axis position.
8. The preparation process of the packaging structure is characterized by comprising the following preparation steps of:
step S1: providing a packaging substrate; simultaneously providing a heat dissipation structure, wherein the heat dissipation structure is provided with a cavity and a partition plate is arranged in the cavity;
step S2: forming a component on a first surface of a packaging substrate, and attaching a chip structure to the first surface in an inverted manner;
step S3: arranging the heat dissipation structure and the partition plate cover above the packaging substrate, enabling the chip structure and the component to be located in the cavity, enabling the partition plate to surround the periphery of the chip structure, and enabling the chip structure and the component to be separated by the partition plate;
step S4: reflow soldering is carried out on the product obtained in the step S3 in a vacuum environment, and the separator can avoid the risk of short circuit of the components;
the heat dissipation structure comprises a first heat dissipation structure used for being in contact with the first surface of the packaging substrate and a second heat dissipation structure located on the top of the first heat dissipation structure, and one part of the second heat dissipation structure is used for being in contact with a chip structure to be packaged; the partition plate is positioned on the inner side of the first heat dissipation structure, and is provided with a vent hole;
the following steps are also included between step S2 and step S3: coating a flux, a heat dissipation layer and a flux three-layer laminated structure on the surface of the chip structure; then coating a sealing layer material on the first surface, wherein the position of coating the sealing layer material is determined according to the contact positions of the first heat dissipation structure and the partition board with the first surface, and no sealing layer material is coated at the position between the first heat dissipation structure and the first surface corresponding to the vent hole;
the partition board comprises a first partition board around the chip structure and a second partition board connecting the first partition board and the first heat dissipation structure together, the vent hole is a vent channel between the adjacent second partition boards, the vent channel is not provided with the corresponding component, and the first partition board and the second partition board are both in contact with the first surface through the sealing layer material.
9. The process for manufacturing a package structure according to claim 8, wherein the package substrate further includes a second surface opposite to the first surface, and further includes forming solder balls on the second surface after step S4.
10. The process of manufacturing a package structure according to claim 8, wherein the second heat dissipation structure is in contact with the heat dissipation layer after the reflow process in step S4.
11. The process for manufacturing the package structure according to claim 8, wherein the heat dissipation structure is made of a metal heat conductive material; the material of the heat dissipation layer is indium, indium-silver alloy, silver, tin-silver alloy or tin-lead alloy.
12. The process for manufacturing a package structure according to claim 8, wherein the spacer and the heat dissipation structure are integrally formed by stamping or machining.
13. The process for preparing a package structure according to claim 8, wherein the one or more vent holes are distributed around the periphery of the chip and are distributed according to the central axis position.
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| CN111584478B (en) * | 2020-05-22 | 2022-02-18 | 甬矽电子(宁波)股份有限公司 | Laminated chip packaging structure and laminated chip packaging method |
| CN111477613A (en) * | 2020-06-04 | 2020-07-31 | 上海新微技术研发中心有限公司 | Three-dimensional chip packaging structure and packaging method |
| CN112216675A (en) * | 2020-09-11 | 2021-01-12 | 中国电子科技集团公司第十三研究所 | Micro-assembly substrate structure and chip micro-assembly method |
| CN113990809B (en) * | 2021-12-17 | 2022-04-29 | 中兴通讯股份有限公司 | Packaging structure, circuit board assembly and electronic equipment |
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| CN108281389A (en) * | 2017-12-29 | 2018-07-13 | 苏州通富超威半导体有限公司 | A kind of chip assembly and preparation method thereof that thermal diffusivity is good |
| CN109755197A (en) * | 2019-01-14 | 2019-05-14 | 苏州通富超威半导体有限公司 | Encapsulating structure and forming method thereof |
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| CN108281389A (en) * | 2017-12-29 | 2018-07-13 | 苏州通富超威半导体有限公司 | A kind of chip assembly and preparation method thereof that thermal diffusivity is good |
| CN109755197A (en) * | 2019-01-14 | 2019-05-14 | 苏州通富超威半导体有限公司 | Encapsulating structure and forming method thereof |
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