JPH04168749A - Semiconductor package - Google Patents

Semiconductor package

Info

Publication number
JPH04168749A
JPH04168749A JP29694590A JP29694590A JPH04168749A JP H04168749 A JPH04168749 A JP H04168749A JP 29694590 A JP29694590 A JP 29694590A JP 29694590 A JP29694590 A JP 29694590A JP H04168749 A JPH04168749 A JP H04168749A
Authority
JP
Japan
Prior art keywords
chip
pins
semiconductor package
heat spreader
aligned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29694590A
Other languages
Japanese (ja)
Inventor
Yukio Yamaguchi
幸雄 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP29694590A priority Critical patent/JPH04168749A/en
Publication of JPH04168749A publication Critical patent/JPH04168749A/en
Pending legal-status Critical Current

Links

Landscapes

  • Mounting Of Printed Circuit Boards And The Like (AREA)

Abstract

PURPOSE:To realize accurate positioning of I/O pins only through connection of a positioning member with a connecting pad by bonding the positioning member to an IC chip in predetermined positional relation with respect to the I/O pins. CONSTITUTION:A semiconductor package comprises a heat spreader 2 having leg parts at four corners and an IC chip 3 bonded to the heat spreader 2. The IC chip 3 is previously provided with a multiplicity of electrodes 5 bonded with a plurality of I/O pins, i.e. micro pins 6, in grid. When (a) and (b) are aligned reliably and a circuit is arranged in same positional relationship on the side of the printed board at the time of bonding of the IC chip 3 and the heat spreader 2, all micro pins can be aligned by simply mounting the IC chip 3 with each leg part being aligned.

Description

【発明の詳細な説明】 技術分野 本発明は゛l’導体パッケージに関し、特に大電力IC
チップを含み、微細なピッチの表面実装に用いる7ト導
体パッケージに関する。
Detailed Description of the Invention Technical Field The present invention relates to a conductor package, particularly for high power ICs.
This invention relates to a 7-conductor package that includes a chip and is used for fine pitch surface mounting.

従来技術 従来、この種の半導体パッケージには、ヒートシンクと
一体になったものがある。
Prior Art Conventionally, some semiconductor packages of this type are integrated with a heat sink.

例えば、従来の半導体パッケージの実装状態を示す第3
図を参照すると、複数本のり−ド〕2を有するICl3
がヒートシンク14に取付けられている。そして、ヒー
トシンク14の脚部15がプリント基板9上の導体回路
11に半田付は等で接続され、リード12が導体回路(
接続用パッド)10に半田付けや熱圧着法等で接続され
ている。
For example, the third image shows the mounting state of a conventional semiconductor package.
Referring to the figure, ICl3 having multiple boards]2
is attached to the heat sink 14. The legs 15 of the heat sink 14 are connected to the conductor circuit 11 on the printed circuit board 9 by soldering or the like, and the leads 12 are connected to the conductor circuit (
It is connected to the connection pad (connection pad) 10 by soldering, thermocompression bonding, or the like.

かかる従来の半導体パッケージをプリント基板9上に実
装する場合、まず最初にヒートシンク14の脚部15を
導体回路11に接続し、その後に各リード12を対応す
る導体回路10に接続するという工程が採られている。
When mounting such a conventional semiconductor package on the printed circuit board 9, a process is adopted in which the legs 15 of the heat sink 14 are first connected to the conductor circuit 11, and then each lead 12 is connected to the corresponding conductor circuit 10. It is being

すなわち、上述した従来の半導体パッケージにおけるヒ
ートシンク14の目的は、ICl3の熱を効率良く放散
させることにあり、ICのリード12と基板上の導体回
路10との位置合せには特別の工夫はされていない。こ
れは、リード12がある程度の自由度を持っており、導
体回路10に対して容易に位置を合せることができるか
らである。また、各リードのピッチも比較的大きく、そ
れほど厳密な位置合せが必要ないからでもある。
That is, the purpose of the heat sink 14 in the conventional semiconductor package described above is to efficiently dissipate the heat of the ICl3, and no special measures are taken to align the IC leads 12 and the conductive circuit 10 on the substrate. do not have. This is because the lead 12 has a certain degree of freedom and can be easily aligned with the conductor circuit 10. Another reason is that the pitch of each lead is relatively large, and so strict alignment is not required.

しかしながら、半導体パッケージにおいては、接続端子
数の増加に伴い、リード12を微細化する必要があり、
従来の半導体パッケージではリードのピッチが100[
μm]以下になると、リードの形成が困難になる。それ
とともに、脚部15の取付けやリード12の接続の際、
熱でリードの変形や導体回路に対する位置ずれが起きる
という欠点がある。
However, in semiconductor packages, as the number of connection terminals increases, it is necessary to miniaturize the leads 12.
In conventional semiconductor packages, the lead pitch is 100 [
μm] or less, it becomes difficult to form leads. At the same time, when attaching the legs 15 and connecting the leads 12,
The drawback is that heat can cause deformation of the leads and misalignment with respect to the conductor circuit.

また、従来の半導体パッケージのヒートシンク7は、L
SIと固着しているため、材質として、熱膨張係数をL
 S I 材料と一致させる必要がある。
Further, the heat sink 7 of the conventional semiconductor package is L
Because it is fixed to SI, the material has a thermal expansion coefficient of L.
Must match S I material.

さらに、ヒートシンクとしての役目から熱伝導性が良く
、フィン状に加−11する必要があることがら加工性の
良い材質か望ましく、かつ、当然のことながら、価格的
に安いものが好ましい。しかしながら、このような全て
の条件を満足する材料は少なく、いずれかの特性を犠牲
にしているという欠点もある。
Further, since it serves as a heat sink, it is desirable that it has good thermal conductivity, and since it is necessary to form it into a fin shape, it is preferably made of a material that is easy to work with, and of course, it is preferably a material that is inexpensive. However, there are few materials that satisfy all of these conditions, and they also have the disadvantage of sacrificing some of the properties.

発明の目的 本発明は上述した従来の欠点を解決するためになされた
ものであり、その11的は微細で多くの端子を有してい
ても容易な実装を可能とする半導体パッケージを提供す
ることである。
OBJECTS OF THE INVENTION The present invention has been made to solve the above-mentioned conventional drawbacks, and its eleventh objective is to provide a semiconductor package that can be easily mounted even if it is minute and has many terminals. It is.

発明の構成 本発明による半導体パッケージは、裏面に複数の入出力
ピンを有するICチップと、位置決め用の脚部を有し、
予め定められた位置関係で前記ICチップの表面と接着
して取イ」けられた位置決め部材とを含み、プリント基
板上に予め設けられた位置決め用パッドに前記脚部を接
続するようにしたことを特徴とする。
Structure of the Invention A semiconductor package according to the present invention has an IC chip having a plurality of input/output pins on the back surface, and legs for positioning,
A positioning member is attached to and removed from the surface of the IC chip in a predetermined positional relationship, and the leg is connected to a positioning pad provided in advance on a printed circuit board. It is characterized by

実施例 次に、本発明について図面を参照して説明する。Example Next, the present invention will be explained with reference to the drawings.

第1図(a)は、本発明による半導体パッケージの一実
施例の裏面の外観を示す斜視図であり、同図(b)は、
その表面を上にした場合の外観を示す側面図である。
FIG. 1(a) is a perspective view showing the appearance of the back side of an embodiment of a semiconductor package according to the present invention, and FIG. 1(b) is a
FIG. 3 is a side view showing the appearance when the surface thereof is facing up.

第1図(a)において、本発明の一実施例による半導体
パッケージは、脚部1が四隅に設けられているヒートス
プレッダ2と、このヒートスプレッダ2に接むされたI
Cチップ3とから構成されている。ICチップ3には多
数の電極5が予め設けられており、この電極5に人出力
ピンたるマイクロピン6が格子状に複数本接着されてい
る。
In FIG. 1(a), a semiconductor package according to an embodiment of the present invention includes a heat spreader 2 with leg portions 1 provided at four corners, and an I.
It is composed of a C chip 3. A large number of electrodes 5 are provided in advance on the IC chip 3, and a plurality of micro pins 6, which are human output pins, are bonded to the electrodes 5 in a grid pattern.

なお、同図(b)に示されているように、各電極5とマ
イクロピン6とは、例えばA u / S n(80/
 20 w t%)等の接合材7て取イ声1け、ヒート
スプレッダ2とICチップ3とは半[11、例えばS 
n / A g (H,5/ 3.5 w t%)等の
接合材4で取付ければ良い。
In addition, as shown in the same figure (b), each electrode 5 and the micro pin 6 are, for example, A u / S n (80/
20wt%), etc., and the heat spreader 2 and IC chip 3 are
It may be attached using a bonding material 4 such as n/Ag (H, 5/3.5 wt%).

また、ICチップ3とマイクロピン6との合旧の長さに
対して脚部]の長さをhたけ長くする。
Furthermore, the length of the leg portion is increased by h compared to the length of the IC chip 3 and the micro pin 6 when they are combined.

このhは、マイクロピン6の長さのバラツキを考慮し、
プリント基板実装時における接続不良の発生を防止する
ため、例えば数百[μm]とすれば良い。なお、各脚部
の底面は正方形とすれば良い。
This h takes into consideration the variation in the length of the micro pin 6,
In order to prevent connection failures during mounting on a printed circuit board, the thickness may be set to several hundreds [μm], for example. Note that the bottom surface of each leg may be square.

さらにまた、第1図(a)を参照すると、格r・状に設
けられた各マイクロピンのうち、四隅に設けられている
ものについては、ヒートスプレッダ2の各脚部からの寸
法が、夫々a、bとなるようにICチップ3が接合材4
で固定されている。この寸法合せについては、顕微鏡等
を用いて作業すれば良い。つまり、本半導体パッケージ
を構成するICチップ3とヒートスプレッダ2とを接着
する際に上述のa、bとなるように確実に位置合せを行
っておき、さらにプリント基板側にも同様の位置関係の
導体回路を配置しておけば、各脚部の位置を合せて実装
するだけで全マイクロピンの位置合せが確実に行えるの
である。なお、導体回路を大きくするほど位置合せが行
いやすいが、あまり大きくすると隣同士との短絡が発生
しやすいので入出力ピン数に応じて適当な大きさにすれ
ば良い。
Furthermore, referring to FIG. 1(a), among the micro pins provided in the shape of a square, the dimensions of the micro pins provided at the four corners from each leg of the heat spreader 2 are a. , b, the IC chip 3 is attached to the bonding material 4.
is fixed. This dimension adjustment may be carried out using a microscope or the like. In other words, when bonding the IC chip 3 and the heat spreader 2 that make up this semiconductor package, ensure that they are aligned as shown in a and b above, and also conductors with the same positional relationship on the printed circuit board side. Once the circuits are placed, all the micropins can be reliably aligned by simply aligning each leg and mounting it. Note that the larger the conductor circuit is, the easier it is to perform alignment, but if it is too large, short circuits between adjacent circuits are likely to occur, so the size may be set appropriately depending on the number of input/output pins.

その実装状態について第2図を用いて説明する。The mounting state will be explained using FIG. 2.

第2図は第1図の半導体パッケージの実装例を示す側面
図である。
2 is a side view showing an example of mounting the semiconductor package of FIG. 1. FIG.

図において、脚部1をプリント基板9上の導体回路]1
に半lJ付けするとともにマイクロピン6をプリント基
板9上の導体回路8に’−1’=m16にて接続する。
In the figure, the leg 1 is a conductor circuit on a printed circuit board 9 ] 1
At the same time, the micro pin 6 is connected to the conductor circuit 8 on the printed circuit board 9 at '-1'=m16.

この場合における’Ii IIIとしては、例えば、S
n/Pb (63/37wt%)を用いれば良い。なお
、上述のように、このl’ III 例は時において、
ICチップ3とマイクロピン6との合旧の長さに対して
脚部1の長さはIJ法りだけ長くなっている。
In this case, 'Ii III is, for example, S
n/Pb (63/37wt%) may be used. Note that, as mentioned above, this l' III example is sometimes
The length of the leg portion 1 is longer by the IJ dimension than the length of the mating between the IC chip 3 and the micro pin 6.

また、予め導体回路11と導体回路8との位置寸法を上
述の寸法a、bと同一にしておくことにより、脚部1を
プリント基板9上の導体回路11に位置を合せて実装す
ることにより、導体回路8とマイクロピン6との位置合
わせが行えるのである。
Furthermore, by making the positional dimensions of the conductive circuit 11 and the conductive circuit 8 the same as the above-mentioned dimensions a and b in advance, the leg portion 1 can be mounted in alignment with the conductive circuit 11 on the printed circuit board 9. , the conductor circuit 8 and the micro pin 6 can be aligned.

このようなチップ実装構造においては、従来IC上の電
極とプリント基板上の導体回路との位置合せは、例えば
、ICチップの外形を基準にして行っていた。しかしな
がら、ICチップの裏面の外形は切断時に欠損が起こり
やすく、正確な位置合せが困難であった。これに対し、
本発明では、予め、ICチップ上のマイクロピンとヒー
トスプレッダの脚部との位置関係、すなわち上述の寸法
a、bを正確に合せておくことにより、位置決め部材と
して作用するヒートスプレッダの各脚部と導体回路1]
との位置合せを行えば、自動的にプリント基板とIC電
極との位置合せができるのである。
In such a chip mounting structure, conventionally the electrodes on the IC and the conductor circuit on the printed circuit board are aligned based on, for example, the outer shape of the IC chip. However, the outer shape of the back surface of the IC chip is likely to be damaged during cutting, making accurate alignment difficult. In contrast,
In the present invention, by accurately aligning the positional relationship between the micro pins on the IC chip and the legs of the heat spreader, that is, the above-mentioned dimensions a and b, in advance, each leg of the heat spreader that acts as a positioning member and the conductor circuit are arranged. 1]
By aligning the printed circuit board with the IC electrode, the printed circuit board and the IC electrode can be automatically aligned.

また、ヒートスプレッダ2はICチップ3から発生する
熱を、裏面へ広げて伝え、ヒートスプレッダ上に取4=
Iけられる図示せぬヒートシンク等で冷却する。なお、
ヒートスプレッダの材質としてはCu/W複合材、Af
IN、SiC等の熱伝導率が良く、熱膨張係数がLSI
材料(本実施例ではシリコン)に合っているものを用い
る。これにより、ヒートシンクとしてA、l?やCu等
価格が安く、加工性の良い材料を用いることができるの
である。
In addition, the heat spreader 2 spreads and transmits the heat generated from the IC chip 3 to the back surface, and transfers the heat to the back surface of the IC chip 3.
It is cooled by a heat sink (not shown) that can be used for cooling. In addition,
The material of the heat spreader is Cu/W composite material, Af
IN, SiC, etc. have good thermal conductivity, and the thermal expansion coefficient is LSI
A material suitable for the material (silicon in this example) is used. This allows A, l? It is possible to use materials that are inexpensive and have good workability, such as copper or copper.

さらに、空冷等のヒートシンクのみならず、液冷タイプ
のコールドプレート等を圧接して冷却したり、絶縁性液
体に浸漬して冷却したりすることもできる。また、IC
と基板との熱膨張差をマイクロピンで応力緩和できる。
Furthermore, in addition to an air-cooled heat sink, it is also possible to cool by pressing a liquid-cooled type cold plate or the like, or by immersing it in an insulating liquid. Also, IC
Micro pins can relieve stress due to the difference in thermal expansion between the substrate and the substrate.

発明の詳細 な説明したように本発明は、ICチップ上に設けられる
入出力ビンに対して予め定められた位置関係となるよう
に位置決め部材をICチップに接着することにより、プ
リント基板上に実装する際、位置決め部材を接続用パッ
ドに接続するだけで入出力ピンについての位置合せが容
易、かつ正確に行えるという効果がある。
DETAILED DESCRIPTION OF THE INVENTION As described above, the present invention provides mounting on a printed circuit board by bonding a positioning member to an IC chip in a predetermined positional relationship with respect to input/output bins provided on the IC chip. In this case, the input/output pins can be easily and accurately aligned simply by connecting the positioning member to the connection pad.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)は本発明の実施例による゛1′導体パッケ
ージの裏面の外観を示す斜視図、同図(b)は同図(a
)の表面を上にした場合の外観を示す側面図、第2図は
第1図の半導体パッケージの実装例を示す側面図、第3
図は従来の?(’導体パッケージの外観を示す斜視図で
ある。 主要部分の符号の説明 1・・・・・・脚部    2・・・・・・ヒートスプ
レッダ3・・・・・・ICチップ 6・・・・・・マイ
クロピン8.11・・・・・・導体回路
FIG. 1(a) is a perspective view showing the appearance of the back side of the ``1'' conductor package according to the embodiment of the present invention, and FIG.
) is a side view showing the external appearance when the surface of the semiconductor package is facing up, FIG.
Is the diagram conventional? (It is a perspective view showing the external appearance of the conductor package. Explanation of symbols of main parts 1...Legs 2...Heat spreader 3...IC chip 6... ...Micro pin 8.11...Conductor circuit

Claims (1)

【特許請求の範囲】[Claims] (1)裏面に複数の入出力ピンを有するICチップと、
位置決め用の脚部を有し、予め定められた位置関係で前
記ICチップの表面と接着して取付けられた位置決め部
材とを含み、プリント基板上に予め設けられた位置決め
用パッドに前記脚部を接続するようにしたことを特徴と
する半導体パッケージ。
(1) An IC chip with multiple input/output pins on the back side,
It has positioning legs and includes a positioning member attached to the surface of the IC chip by adhesion in a predetermined positional relationship, and the legs are attached to positioning pads provided in advance on a printed circuit board. A semiconductor package characterized by being connected.
JP29694590A 1990-10-31 1990-10-31 Semiconductor package Pending JPH04168749A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29694590A JPH04168749A (en) 1990-10-31 1990-10-31 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29694590A JPH04168749A (en) 1990-10-31 1990-10-31 Semiconductor package

Publications (1)

Publication Number Publication Date
JPH04168749A true JPH04168749A (en) 1992-06-16

Family

ID=17840216

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29694590A Pending JPH04168749A (en) 1990-10-31 1990-10-31 Semiconductor package

Country Status (1)

Country Link
JP (1) JPH04168749A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5567984A (en) * 1994-12-08 1996-10-22 International Business Machines Corporation Process for fabricating an electronic circuit package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5567984A (en) * 1994-12-08 1996-10-22 International Business Machines Corporation Process for fabricating an electronic circuit package

Similar Documents

Publication Publication Date Title
US6208025B1 (en) Microelectronic component with rigid interposer
US6570259B2 (en) Apparatus to reduce thermal fatigue stress on flip chip solder connections
EP0559366B1 (en) Stackable three-dimensional multiple chip semiconductor device and method for making the same
US6373703B2 (en) Integral design features for heatsink attach for electronic packages
JPS63239832A (en) Method of mounting ic chip onto printed circuit board, ic chip package obtained by the method and ic chip tape carrier for implementing the method
JPH05183280A (en) Multichip-module
JPH07106477A (en) Heat sink assembly with heat conduction board
JPH05211202A (en) Composite flip-chip semiconductor device, its manufacture and method for burn-in
US8153516B2 (en) Method of ball grid array package construction with raised solder ball pads
KR20010070094A (en) Semiconductor device and method for manufacturing same
US20070130554A1 (en) Integrated Circuit With Dual Electrical Attachment Pad Configuration
JP2803603B2 (en) Multi-chip package structure
TW587325B (en) Semiconductor chip package and method for manufacturing the same
JPH06224338A (en) Electronic device
JP3715438B2 (en) Electronic device and manufacturing method thereof
US6784536B1 (en) Symmetric stack up structure for organic BGA chip carriers
JP3421137B2 (en) Bare chip mounting structure and heat sink
JPH04168749A (en) Semiconductor package
JPH06310564A (en) Semiconductor device
JPH01291438A (en) Method of mounting flip chip
JP2847949B2 (en) Semiconductor device
JP2005064118A (en) Semiconductor device and its manufacturing method
JPH0537105A (en) Hybrid integrated circuit
JP2924394B2 (en) Semiconductor device and manufacturing method thereof
JPH03248450A (en) Semiconductor package