JPH0324767A - Semiconductor rectifier - Google Patents

Semiconductor rectifier

Info

Publication number
JPH0324767A
JPH0324767A JP1160312A JP16031289A JPH0324767A JP H0324767 A JPH0324767 A JP H0324767A JP 1160312 A JP1160312 A JP 1160312A JP 16031289 A JP16031289 A JP 16031289A JP H0324767 A JPH0324767 A JP H0324767A
Authority
JP
Japan
Prior art keywords
type semiconductor
semiconductor region
recovery time
width
semiconductor regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1160312A
Other languages
Japanese (ja)
Inventor
Yoshito Akiyama
秋山 義人
Hiroyasu Kawachi
浩康 河内
Toshihiko Yoshida
稔彦 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyota Industries Corp
Original Assignee
Toyoda Automatic Loom Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyoda Automatic Loom Works Ltd filed Critical Toyoda Automatic Loom Works Ltd
Priority to JP1160312A priority Critical patent/JPH0324767A/en
Publication of JPH0324767A publication Critical patent/JPH0324767A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/872Schottky diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To cut down the inverse recovery time for accelerating the title rectifier with the gentle slope of current during the inverse recovery time kept as it is by a method wherein p<-> type semiconductor regions in specific intervals and width are intermittently formed in the surface region of n<-> type semiconductor region provided on n type semiconductor region. CONSTITUTION:The title semiconductor rectifier is composed af p<-> type semiconductor regions 13 intermittently arranged on anode side as well as a Schottky diode in short inverse recovery time trr laid between pn junction diodes. Accordingly, the inverse recovery time trr can be cut down to accelerate the rectifier moreover enabling the total impurity amount of the whole anode to be reduced without lowering the impurity concentration in the p<-> type semiconductor regions 13 so that the inverse recovery time trr may be cut down with the gentle slope of current di/dt2 during the inverse recovery time kept as it is. Through these procedures, the said characteristics can be notably enhanced by equally setting up the individual width w1 of the p<-> type semiconductor regions 13 and the width w2 between the p<-> type semiconductor regions 13.

Description

【発明の詳細な説明】 〔概  要〕 本発明は半導体整流装置に関し、逆回復時の電流の傾き
を緩やかに保ったまま、逆回復時間を短くして高速化を
可能にするために、n型半導体領域上に設けられたn”
型半導体領域の表面領域に、所定間隔で所定幅のp一型
半導体領域を断続的に形成することで、アノード側にお
いてpn接合部分とショットキー接合部分とが交互に配
設されるようにしたものである。
[Detailed Description of the Invention] [Summary] The present invention relates to a semiconductor rectifier, and in order to shorten the reverse recovery time and increase speed while maintaining a gentle slope of current during reverse recovery, the present invention relates to a semiconductor rectifier. n” type semiconductor region provided on the
By intermittently forming p-type semiconductor regions of a predetermined width at predetermined intervals on the surface region of the type semiconductor region, p-n junction portions and Schottky junction portions are arranged alternately on the anode side. It is something.

〔産業上の利用分野〕[Industrial application field]

本発明は、半導体整流装置に係り、特にはP型とn型の
半導体領域の間に低不純物濃度の半導体領域を介在させ
た、いわゆるpinダイオードの改良に関する。
The present invention relates to a semiconductor rectifier, and particularly to an improvement in a so-called pin diode in which a semiconductor region with a low impurity concentration is interposed between a P-type and an N-type semiconductor region.

〔従来の技術] 従来のpin構造を有する半導体整流装置の断面構或を
第4図に示す。
[Prior Art] FIG. 4 shows a cross-sectional structure of a semiconductor rectifier having a conventional pin structure.

同図において、不純物濃度5 X 1 0 ”cm−”
程度のn型半導体基板lの上には、エピタキシャル或長
により不純物濃度I X 1 0 1cm−”程度の低
不純物濃度のn”型半導体領域(i領域)2が厚さ40
μm程度に堆積され、その表面領域には、不純物拡散に
より表面の不純物濃度2×1016CI11−3程度の
p”型半導体領域3が深さ5〜6μm程度に形成されて
いる。そして、このp一型半導体領域3の上には、AI
!.等でできた金属電極4が真空蒸着等により被着形成
されている。
In the same figure, the impurity concentration is 5 x 10 "cm-"
An n'' type semiconductor region (i region) 2 with a low impurity concentration of about I x 101 cm-'' is formed on an n type semiconductor substrate l with a thickness of about 40 cm by epitaxial elongation.
A p'' type semiconductor region 3 with a surface impurity concentration of about 2×1016 CI11-3 is formed in the surface region by impurity diffusion to a depth of about 5 to 6 μm. On top of the type semiconductor region 3, an AI
! .. A metal electrode 4 made of, for example, is formed by vacuum evaporation or the like.

このような構或からなるダイオードに順バイアスが印加
されている状態から逆バイアスに切り換わると、一Mに
は、例えば第5図に示すような電流波形が得られる。す
なわち、先ず順電流IFが急激に減少していき、その後
、電流ゼロを経て逆電流が流れ始める。次に、逆電流の
最大値IPRに達した後、逆電流は減少し始め、最終的
に電流ゼロに落ち着く.同図において、trrは、逆電
流が流れ始めてから最大値IPIIを経て、その10%
まで回復するのに要する時間(以下、逆回復時間と称す
)であり、di/dt2は、逆電流が最大値ipt+か
らゼロまで回復する時の電流の傾きである.〔発明が解
決しようとする課題〕 半導体整流装置では、一般に高周波化の要望があり、そ
のためには逆回復時間t,..を短くする必要がある。
When the diode having such a structure is switched from being forward biased to reverse biased, a current waveform as shown in FIG. 5, for example, is obtained at 1M. That is, first, the forward current IF rapidly decreases, and then the current reaches zero and the reverse current begins to flow. Then, after reaching the maximum reverse current value IPR, the reverse current begins to decrease and finally settles to zero current. In the same figure, trr is 10% of the maximum value IPII after the reverse current starts flowing.
di/dt2 is the time required for the reverse current to recover from the maximum value ipt+ to zero (hereinafter referred to as reverse recovery time), and di/dt2 is the slope of the current when the reverse current recovers from the maximum value ipt+ to zero. [Problems to be Solved by the Invention] In semiconductor rectifiers, there is generally a demand for higher frequencies, and for this purpose, reverse recovery times t, . .. needs to be shortened.

そのための方法としては、従来から、例えばAuやpt
等の重金属を拡散したり、電子線やプロトンを照射した
りすることにより、キャリアのライフタイムをコントロ
ールする手法が知られている。ところが、このようなラ
イフタイムコントロールを行うと、順電圧VFが高くな
り、しかもリーク電流も大きくなるという問題がある.
そこで、ライフタイムコントロールを行わずに高速化を
可能にするため、第4図におけるp一型半導体領域3の
不純物濃度を低下させて、n一型半導体領域2への正札
の注入を減少させることにより、逆回復時間t,..を
短くしようとする試みがなされている。
Conventionally, methods for this purpose include, for example, Au or PT.
There are known methods to control the lifetime of carriers by diffusing heavy metals such as metals, etc., or irradiating them with electron beams or protons. However, when such lifetime control is performed, there is a problem that the forward voltage VF increases and the leakage current also increases.
Therefore, in order to increase the speed without performing lifetime control, the impurity concentration of the p-type semiconductor region 3 in FIG. Therefore, the reverse recovery time t, . .. Attempts are being made to shorten the .

ところが、このようにして逆回復時間t rrを短くし
ようとすると、逆回復時の電流の傾きdi/dt2がど
うしても大きくなってしまうことが経験的に確認された
。ai,/tit2が大きくなると、この半導体整流装
置を組み込んだ回路内に存在するインダクタンス或分L
により、−Ldi/dt2なる大きな起電力が生じ、こ
れがスパイクノイズの発生や素子の破壊等の原因になっ
てしまう。
However, it has been empirically confirmed that if an attempt is made to shorten the reverse recovery time trr in this manner, the slope di/dt2 of the current during reverse recovery inevitably increases. When ai,/tit2 increases, the inductance L existing in the circuit incorporating this semiconductor rectifier increases
As a result, a large electromotive force of -Ldi/dt2 is generated, which causes spike noise generation and element destruction.

本発明は、上記従来の問題点に鑑みてなされたものであ
り、その目的は、逆回復時の電流の傾きd i / d
 t zを緩やかに保ったまま、逆回復時間trrを短
くして高速化を実現することのできる半導体整流装置を
提供することにある。
The present invention has been made in view of the above conventional problems, and its purpose is to reduce the current slope d i / d during reverse recovery.
It is an object of the present invention to provide a semiconductor rectifier that can achieve high speed by shortening the reverse recovery time trr while keeping tz moderate.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体整流装置は、n型半導体領域と、該n型
半導体領域上に形成された低不純物濃度のn一型半導体
領域と、該n一型半導体領域の表面領域に所定間隔で断
続的に形成された低不純物濃度のp−型半導体領域と、
該p一型半導体領域上及び該p−型半導体領域間に露呈
した前記n”型半導体領域上に、該p一型半導体領域と
はオー稟ック接触し、かつ該n一型半導体領域とはショ
ットキー接触するように形成された金属電極とを有し、
前記p一型半導体領域間の幅は逆バイアス印加時にその
両側から延びる空乏層が互いに届く距離以下とし、かつ
前記p一型半導体領域の個々の幅は前記p−型半導体領
域間の幅と等しいかほぼ等しくなるようにしたことを特
徴とする。
The semiconductor rectifier of the present invention includes an n-type semiconductor region, a low impurity concentration n-type semiconductor region formed on the n-type semiconductor region, and a surface region of the n-type semiconductor region intermittently at predetermined intervals. a p-type semiconductor region with a low impurity concentration formed in
On the p-type semiconductor region and on the n''-type semiconductor region exposed between the p-type semiconductor regions, there is an orthogonal contact with the p-type semiconductor region and with the n-type semiconductor region. has a metal electrode formed in Schottky contact;
The width between the p-type semiconductor regions is less than or equal to the distance that depletion layers extending from both sides reach each other when a reverse bias is applied, and the width of each of the p-type semiconductor regions is equal to the width between the p-type semiconductor regions. It is characterized in that it is made to be almost equal.

〔作  用〕[For production]

上記構戊によれば、第1に、アノード側のp型半導体領
域が断続的に形成されているので、従来のように連続的
に形成されているもの(第4図参照)と比較して、平均
的な不H物濃度は変えずに、アノード全体の不純物総量
を減少させることが可能になる。第2に、アノード側は
、断続的に形成されたpn接合部分の間にショットキー
接合部分を介在させた構或となるので、全体的に見れば
、逆回復時間trrの小さなショットキーダイオードが
pn接合ダイオードの間に組み込まれた構或となる。以
上の点から、本発明の半導体整流装置は、逆回復時間t
rrが短くて高速化が可能になり、しかもp一型半導体
領域の不純物濃度をあまり下げる必要がなりことから逆
回復時の電流の傾きd i / d t 2は緩やかに
保たれる。そして、これらの特性は、上記のようにp”
型半導体領域の個々の幅がp一型半導体領域間の幅と等
しいかほぼ等しくなるようにした場合に良好であること
が実験により確認された。
According to the above structure, firstly, the p-type semiconductor region on the anode side is formed intermittently, compared to the conventional structure in which it is formed continuously (see FIG. 4). , it becomes possible to reduce the total amount of impurities in the entire anode without changing the average impurity concentration. Second, the anode side has a structure in which Schottky junctions are interposed between intermittently formed pn junctions, so overall, a Schottky diode with a small reverse recovery time trr can be used. The structure is built between pn junction diodes. From the above points, the semiconductor rectifier of the present invention has a reverse recovery time t
The short rr makes it possible to increase the speed, and since it is not necessary to lower the impurity concentration of the p-type semiconductor region too much, the slope d i /d t 2 of the current during reverse recovery can be kept gentle. And these properties are p” as above
It has been confirmed through experiments that the method is good when the width of each of the p-type semiconductor regions is equal to or almost equal to the width between the p-type semiconductor regions.

また、p一型半導体領域間の幅は、逆バイアス印加時に
p一型半導体領域の両側から延びる空乏層が互いに届く
ことのできる距離以下としてあるので、ショットキーダ
イオード部分が存在しているにもかかわらず、十分な逆
耐圧が得られる。
In addition, the width between the p-type semiconductor regions is set to be less than the distance that allows the depletion layers extending from both sides of the p-type semiconductor region to reach each other when a reverse bias is applied, so even if a Schottky diode portion exists, Regardless, sufficient reverse withstand voltage can be obtained.

〔実  施  例〕〔Example〕

以下、本発明の実施例について、図面を参照しながら説
明する。
Embodiments of the present invention will be described below with reference to the drawings.

第1図は本発明の一実施例の半導体整流装置の断面図で
あり、第2図はそのA−A線に沿った不純物プロファイ
ルを示す図である。
FIG. 1 is a sectional view of a semiconductor rectifier according to an embodiment of the present invention, and FIG. 2 is a diagram showing an impurity profile along the line A-A.

第1図において、不純物濃度5 X 1 0 ”cm−
’程度のn型半導体基板11上に、不純物濃度lxlQ
 + 4 cm − 3程度の低不純物濃度のn一型半
導体領域(i領域)12がエビタキシャル或長により厚
さ40μm程度に堆積されている。そして、n一型半導
体領域12の表面領域には、個々の幅w,=20μm程
度で深さd=5μm程度のp一型半導体領域l3が所定
の幅Wz=20μm程度を隔てて断続的に形成されてい
る。このp一型半導体領域l3は、例えば、B(ボロン
)等をドーズ量5X I O l2Cll1−”程度で
イオン注入し、これを深さ5μm程度まで拡散すること
により、その表面での不純物濃度がI X I O ”
cm−3程度となるように形成されている。また、n一
型半導体領域l2の表面領域には、p−型半導体領域l
3の全体を取り囲むように、複数のフィールドリミティ
ングリングl4が上記p一型半導体領域13の形或工程
と同時工程により形成されている。
In FIG. 1, the impurity concentration is 5×10”cm−
' on the n-type semiconductor substrate 11 with an impurity concentration lxlQ
An n-type semiconductor region (i region) 12 having a low impurity concentration of about +4 cm -3 is deposited to a thickness of about 40 μm by ebitaxial deposition. In the surface region of the n-type semiconductor region 12, p-type semiconductor regions l3 each having a width w of about 20 μm and a depth d of about 5 μm are disposed intermittently at a predetermined width Wz of about 20 μm. It is formed. This p-type semiconductor region l3 is formed by, for example, implanting ions of B (boron) or the like at a dose of about 5XIO12Cll1-'' and diffusing it to a depth of about 5 μm, thereby reducing the impurity concentration at the surface. IXIO”
It is formed so that it is about cm-3. Further, in the surface region of the n-type semiconductor region l2, a p-type semiconductor region l
A plurality of field limiting rings 14 are formed so as to surround the entirety of the p-type semiconductor region 13 by a process simultaneous with the formation of the p-type semiconductor region 13.

更に、フィールドリくティングリング14上は酸化膜1
5で覆われており、また、p一型半導体領域13上と、
その間に露呈したn一型半導体領域l2上には、AN(
アルミニウム)でできた表面電極16が真空蒸着等によ
り被着形成されている。ここで、Afの表面電極16は
、p一型半導体領域13との間でオーミック接触し、か
つn型半導体領域13との間でショットキー接触してい
る。一方、n型半導体基板l1の裏面には、この裏面側
から順にCr(クロム)、Ni(ニッケル)、Au(金
)を積層してなる3N構造の裏面電極I7が形成されて
いる。
Furthermore, an oxide film 1 is formed on the field lifting ring 14.
5, and also on the p-type semiconductor region 13,
AN(
A surface electrode 16 made of (aluminum) is formed by vacuum deposition or the like. Here, the Af surface electrode 16 is in ohmic contact with the p-type semiconductor region 13 and in Schottky contact with the n-type semiconductor region 13. On the other hand, on the back surface of the n-type semiconductor substrate l1, a back electrode I7 having a 3N structure is formed by laminating Cr (chromium), Ni (nickel), and Au (gold) in this order from the back surface side.

上記構戒からなる本実施例の半導体整流装置では、アノ
ード側においてp一型半導体領域13を断続的に配置さ
せたことにより、pn接合ダイオードの間に、逆回復時
間trrの小さなショットキーダイオードを介在させた
構戒となっている。よって、逆回復時間t rrを短縮
できて高速化が可能になり、しかもp一型半導体領域l
3の不純物濃度をあまり下げずにアノード全体の不純物
総量を下げることができることから、逆回復時の電流の
傾きat/atzを緩やかに保ったまま逆回復時間tr
yを短縮できる。そして、これらの特性は、上記のよう
にp一型半導体領域13の個々の幅W,とp一型半導体
領域13間の幅W2とを等しく設定したことにより、極
めて良好となることが実験的に確認された。この実験で
得られた逆バイアス印加時の電流波形(実線)を、第4
図に示した従来の半導体整流装置から得られた電流波形
(破線)と比較して、第3図に示す。同図から明らかな
ように、逆回復時間trrが従来のものでは350nS
程度であるのに対し本実施例では290nsと短く、ま
た、電流の傾きdi/dt2も従来のものが66.7A
/μSであるのに対し本実施例では28.3A/μS(
!:緩やかになる。
In the semiconductor rectifier of this embodiment having the above-mentioned structure, by disposing the p-type semiconductor regions 13 intermittently on the anode side, a Schottky diode with a small reverse recovery time trr is inserted between the pn junction diodes. It is a mediated precept. Therefore, the reverse recovery time trr can be shortened and the speed can be increased, and moreover, the p-type semiconductor region l
Since the total amount of impurities in the entire anode can be lowered without significantly lowering the impurity concentration in step 3, the reverse recovery time tr can be reduced while keeping the current slope at/atz during reverse recovery gentle.
y can be shortened. It has been experimentally shown that these characteristics are extremely good by setting the individual widths W of the p-type semiconductor regions 13 and the width W2 between the p-type semiconductor regions 13 to be equal as described above. was confirmed. The current waveform (solid line) obtained in this experiment when applying a reverse bias is
FIG. 3 shows a comparison with the current waveform (broken line) obtained from the conventional semiconductor rectifier shown in the figure. As is clear from the figure, the reverse recovery time trr is 350 nS in the conventional model.
In contrast, in this example, it is as short as 290 ns, and the current slope di/dt2 is 66.7 A in the conventional one.
/μS, whereas in this example it is 28.3A/μS (
! : Becomes gradual.

また、本実施例では、p一型半導体領域l3間の幅W2
を20μmに設定してあり、この距離は、逆バイアス印
加時に隣合ったp一型半導体領域13から延びてくる空
乏層が互いに届くことのできる距離以下である。よって
、ショットキーダイオード部分が存在しているにもかか
わらず、十分な逆耐圧が得られる。しかも、表面電極1
6をAlで形成し、周辺領域にフィニルドリミティング
リングl4を設けたことにより、548Vという非常に
大きな逆耐圧を得ることができた。更に、ショットキー
ダイオード部分が存在することにより、165A/af
lの大電流密度において1.02Vという小さな順電圧
が得られることもわかった。
In addition, in this embodiment, the width W2 between the p-type semiconductor regions l3
is set to 20 μm, and this distance is less than or equal to the distance at which depletion layers extending from adjacent p-type semiconductor regions 13 can reach each other when a reverse bias is applied. Therefore, sufficient reverse breakdown voltage can be obtained despite the presence of the Schottky diode portion. Moreover, the surface electrode 1
By forming 6 with Al and providing a finyl limiting ring 14 in the peripheral region, it was possible to obtain a very large reverse breakdown voltage of 548V. Furthermore, due to the presence of the Schottky diode part, 165A/af
It was also found that a small forward voltage of 1.02 V can be obtained at a large current density of 1.

なお、上記実施例では、p”型半導体領域l3の幅Wl
 とそれらの間の幅W2とを等しく設定したが、必ずし
も全く等しい必要はなく、例えばWl一1Bμm,W2
 =22,czmのようにw+/(w+十W2)が0.
4〜0.5となるような範囲内でほぼ等しく設定してあ
れば十分である。
In addition, in the above embodiment, the width Wl of the p'' type semiconductor region l3
and the width W2 between them are set equal, but they do not necessarily have to be completely equal; for example, Wl - 1Bμm, W2
=22, as in czm, w+/(w+10W2) is 0.
It is sufficient if they are set approximately equal within a range of 4 to 0.5.

また、p一型半導体領域13の表面の不純物濃度も、上
述した1×1016CII1−3に限定されることはな
いが、5X 1 0” 〜l X I Q”cm−3の
範囲内に設定されることが望ましい。
Furthermore, the impurity concentration on the surface of the p-type semiconductor region 13 is not limited to the above-mentioned 1×1016 CII1-3, but may be set within the range of 5×10” to l×IQ”cm−3. It is desirable that

〔発明の効果〕〔Effect of the invention〕

本発明によれば、逆回復時間t,,.を短縮して高速化
を可能にすると共に、この逆回復時間Lrrとはトレー
ドオフ関係にある電流の傾きdi/dt2を緩やかに保
つことができるようになり、しかも十分な逆耐圧を得る
ことができる。
According to the invention, the reverse recovery time t, . It becomes possible to shorten the current speed and increase the speed, and also to maintain a gentle current slope di/dt2, which has a trade-off relationship with the reverse recovery time Lrr, and to obtain a sufficient reverse breakdown voltage. can.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の半導体整流装置の断面図、 第2図は第1図のA−A線に沿った不純物プロファイル
を示す図、 第3図は逆回復時の電流波形を上記実施例と従来例とで
比較して示す図、 第4図は従来の半導体整流装置の断面図、第5図は半導
体整流装置における逆回復時の一般的な電流波形を示す
図である。 11・・・n型半導体基板、 12・・・n一型半導体領域、 l3・・・p一型半導体領域、 l4・・・フィールドリξティングリング、15・・・
酸化膜、 16・・・表面電極、 17・・・裏面電極.
Figure 1 is a cross-sectional view of a semiconductor rectifier according to an embodiment of the present invention, Figure 2 is a diagram showing an impurity profile along line A-A in Figure 1, and Figure 3 is a current waveform during reverse recovery. FIG. 4 is a cross-sectional view of a conventional semiconductor rectifier, and FIG. 5 is a diagram showing a typical current waveform during reverse recovery in a semiconductor rectifier. DESCRIPTION OF SYMBOLS 11... N-type semiconductor substrate, 12... N-type semiconductor region, l3... P-type semiconductor region, l4... Field lying ξ ring, 15...
Oxide film, 16... Surface electrode, 17... Back electrode.

Claims (1)

【特許請求の範囲】 n型半導体領域と、 該n型半導体領域上に形成された低不純物濃度のn^−
型半導体領域と、 該n^−型半導体領域の表面領域に所定間隔で断続的に
形成された低不純物濃度のp^−型半導体領域と、 該p^−型半導体領域上及び該p^−型半導体領域間に
露呈した前記n−型半導体領域上に、該p^−型半導体
領域とはオーミック接触し、かつ該n^−型半導体領域
とはショットキー接触するように形成された金属電極と
を有し、 前記p^−型半導体領域間の幅は逆バイアス印加時にそ
の両側から延びる空乏層が互いに届く距離以下とし、か
つ前記p^−型半導体領域の個々の幅は前記p^−型半
導体領域間の幅と等しいかほぼ等しくなるようにしたこ
とを特徴とする半導体整流装置。
[Claims] An n-type semiconductor region, and a low impurity concentration n^- formed on the n-type semiconductor region.
a p^- type semiconductor region with a low impurity concentration formed intermittently at predetermined intervals on the surface region of the n^- type semiconductor region, and on the p^- type semiconductor region and the p^- type semiconductor region. a metal electrode formed on the n-type semiconductor region exposed between the n-type semiconductor regions so as to be in ohmic contact with the p^-type semiconductor region and in Schottky contact with the n^-type semiconductor region; The width between the p^- type semiconductor regions is set to be less than or equal to the distance that the depletion layers extending from both sides thereof reach each other when a reverse bias is applied, and the width of each of the p^- type semiconductor regions is equal to or less than the width of the p^- type semiconductor regions. 1. A semiconductor rectifying device characterized in that the width is equal to or almost equal to the width between semiconductor regions.
JP1160312A 1989-06-22 1989-06-22 Semiconductor rectifier Pending JPH0324767A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1160312A JPH0324767A (en) 1989-06-22 1989-06-22 Semiconductor rectifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1160312A JPH0324767A (en) 1989-06-22 1989-06-22 Semiconductor rectifier

Publications (1)

Publication Number Publication Date
JPH0324767A true JPH0324767A (en) 1991-02-01

Family

ID=15712236

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1160312A Pending JPH0324767A (en) 1989-06-22 1989-06-22 Semiconductor rectifier

Country Status (1)

Country Link
JP (1) JPH0324767A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6078090A (en) * 1997-04-02 2000-06-20 Siliconix Incorporated Trench-gated Schottky diode with integral clamping diode
JP2002026339A (en) * 2000-07-05 2002-01-25 Sansha Electric Mfg Co Ltd Soft recovery diode and its manufacturing method
JP2002076371A (en) * 2000-06-12 2002-03-15 Fuji Electric Co Ltd Semiconductor device
US6583485B2 (en) * 2000-03-30 2003-06-24 Koninklijke Philips Electronics N.V. Schottky diode
JP2005167149A (en) * 2003-12-05 2005-06-23 Sanken Electric Co Ltd Semiconductor device having schottky barrier
US6975013B2 (en) 1997-06-02 2005-12-13 Fuji Electric Co., Ltd. Diode and method for manufacturing the same
US6979874B2 (en) 1997-06-18 2005-12-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing thereof
JP2006156637A (en) * 2004-11-29 2006-06-15 Shindengen Electric Mfg Co Ltd Diode and bridge diode
US7071525B2 (en) * 2004-01-27 2006-07-04 International Rectifier Corporation Merged P-i-N schottky structure

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6078090A (en) * 1997-04-02 2000-06-20 Siliconix Incorporated Trench-gated Schottky diode with integral clamping diode
US6975013B2 (en) 1997-06-02 2005-12-13 Fuji Electric Co., Ltd. Diode and method for manufacturing the same
US7276771B2 (en) 1997-06-02 2007-10-02 Fuji Electric Co., Ltd. Diode and method for manufacturing the same
US7187054B2 (en) 1997-06-02 2007-03-06 Fuji Electric Holdings Co., Ltd. Diode and method for manufacturing the same
US7112865B2 (en) 1997-06-02 2006-09-26 Fuji Electric Holdings Co., Ltd. Diode and method for manufacturing the same
US6979874B2 (en) 1997-06-18 2005-12-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing thereof
US6583485B2 (en) * 2000-03-30 2003-06-24 Koninklijke Philips Electronics N.V. Schottky diode
JP2002076371A (en) * 2000-06-12 2002-03-15 Fuji Electric Co Ltd Semiconductor device
JP2002026339A (en) * 2000-07-05 2002-01-25 Sansha Electric Mfg Co Ltd Soft recovery diode and its manufacturing method
JP2005167149A (en) * 2003-12-05 2005-06-23 Sanken Electric Co Ltd Semiconductor device having schottky barrier
JP4623259B2 (en) * 2003-12-05 2011-02-02 サンケン電気株式会社 Semiconductor device having Schottky barrier
US7071525B2 (en) * 2004-01-27 2006-07-04 International Rectifier Corporation Merged P-i-N schottky structure
US7858456B2 (en) 2004-01-27 2010-12-28 Siliconix Technology C. V. Merged P-i-N Schottky structure
US9865749B1 (en) 2004-01-27 2018-01-09 Siliconix Technology C. V. Merged P-i-N Schottky structure
JP2006156637A (en) * 2004-11-29 2006-06-15 Shindengen Electric Mfg Co Ltd Diode and bridge diode

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