JPH0324761A - Manufacture of dynamic storage device - Google Patents

Abstract

PURPOSE:To enhance the characteristics of switching MOS transistor as well as the holding characteristics of stored information by a method wherein the whole memory cell matrix array is covered with a mask and then implanted with an impurity ion to form source.drain. CONSTITUTION:The whole memory cell matrix array covered with a mask 14 is implanted with an impurity ion to form n<+> regions for source.drain thereby eliminating the implantation of the same in a gate electrode of a switching MOS transistor furthermore without forming n<+> regions on a substrate so that the said whole array may be kept in the low concentration diffused regions as they are equivalent to the n<-> regions 6 by the impurity ion implantation of LDD structured transistor. Through these procedures, the n<+> impurity ion implanted in the source.drain does not penetrate into the gate of the switching MOS transistor thus forming no n<+> diffused layers in the channel regions so as to avoid the deterioration in the transistor characteristics. Furthermore, the damage to the substrate due to ion implantation is lessened while the leakage of capacitor accumulated charge to the substrate is notably reduced thereby enabling the holding characteristics of stored information to be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a switching MO constituting a unit memory cell.
The present invention relates to a method for manufacturing a dynamic memory device that can be stably realized without deteriorating the characteristics of an S transistor, suppress leakage of charges stored in a capacitor of a memory cell, and improve retention characteristics of stored information.

BACKGROUND OF THE INVENTION In recent years, with the miniaturization of elements, deterioration of transistor characteristics due to hot electrons has become a problem even in dynamic memory devices, and as a countermeasure, semiconductor devices using transistors with a low concentration drain region structure, so-called LDD structure, have been developed. is becoming mainstream. A conventional dynamic memory device using LDD structure MOS transistors will be described below. Figure 3 is a plan view of a unit memory cell of a conventional dynamic memory device, and Figure 4 is its B.
- It is a sectional view along the B' line. 1 is a semiconductor substrate, 2 is an element isolation region, and 3 is an n by ion implantation of a capacitor part.
In the ten regions, 4 is the capacitor counter electrode of the first polysilicon layer, 5 is the gate electrode and word line of the switching transistor of the second polysilicon layer, and 6 is the impurity ion implantation at the time of forming the LDD structure of the switching transistor. area, 7 is the source of the switching transistor,
n0 region by impurity ion implantation during drain formation, 8
9 is an interlayer film, 9 is a contact window, and 10 is a bit line formed by metal wiring. To explain the operation of the dynamic memory device configured in this way, first, the switching MOS transistor of the unit memory cell selected by the word line 5 is turned on, and during writing, the "l" of the manual data is turned on. Alternatively, charges corresponding to a potential of "0" are accumulated and held in the o+ region 3 of the capacitor section through the bit $11110. During reading, the accumulated charge in the capacitor section causes a slight change in the bit line potential, and this potential change is amplified by the sense amplifier, and the stored information is
The distinction between "1" and "O" is realized depending on whether or not charge is accumulated in the capacitor section.

Problems to be Solved by the Invention However, with the above-mentioned conventional configuration, is it difficult to solve the problem of the device? As M becomes thinner, the gate film thickness of switching MOS transistors becomes thinner, and the source. When impurity ions are implanted to form a drain, the impurity ions penetrate through the gate layer and form an n+ diffusion layer 12 in the channel region 1l, deteriorating the characteristics of the transistor. In addition, a high concentration region 7 is formed at the connection portion 13 with the capacitor portion 3, which is one end of the switching MOS transistor, by two impurity ion implantations: formation of the LDD structure and subsequent formation of the source and drain. The collision of accelerated ion particles damages the substrate in this region. As a result, the accumulated charge in the capacitor section tends to leak, and the direction of the leakage current is the direction in which electrons are injected from the substrate to the capacitor section since the substrate bias ≦Ov, and the potential of the capacitor section 3 is There was a problem in that the retention characteristics of stored information deteriorated. The present invention is intended to solve the above-mentioned problems, and an object of the present invention is to provide a method for manufacturing a dynamic memory device with excellent switching MOS transistor characteristics and storage information retention characteristics.

Means for Solving the Problems In order to achieve this object, the method for manufacturing a dynamic memory device of the present invention covers the entire memory cell matrix array using a mask to form a source and a drain. Impurity ion implantation is performed to create a switching MOSt.
- The connection part with the capacitor section, which is one end of the transistor, and the connection part with the bit line, which is the other end, are formed of a low concentration diffusion region equivalent to the low concentration drain region.

Effect: This configuration prevents impurity ions implanted in the source and drain formations from penetrating into the channel region of the switching MOS transistor, thereby preventing deterioration of transistor characteristics, and achieves stable operation even when the gate film thickness is reduced. Can be done.

In addition, there is no n0 region caused by impurity ion implantation to form the source and drain at the connection part with the capacitor part, which is one end of the switching MOS transistor, reducing damage to the substrate due to ion implantation, and forming the memory cell capacitor. It is possible to suppress leakage current in the parts and improve retention characteristics of stored information. Furthermore, switching MOS
} Similarly to the above, there is no n+ region due to impurity ion implantation at the connection part with the bit line, which is the other end of the run transistor.
Unnecessary leakage current from the bit line to the substrate can be reduced.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of a unit recording cell of a dynamic memory device according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along line A-A'I. That is, the semiconductor substrate 1
After forming an element isolation region 2 thereon, impurity ions are implanted into the capacitor portion 3 to form an n+ region. Next, after forming a first gate oxide film, a first polysilicon layer is formed and patterned to form a capacitor counter electrode 4. Furthermore, after the second gate oxide film is formed, a second polysilicon layer is formed and patterned to form the gate electrode of the switching transistor and the word line 5. Using this polysilicon layer as a mask, impurity ions are selectively implanted into an n-region 6 for an LDD structure transistor.
form. Next, impurity ions are implanted by covering the entire area of the memory cell matrix array using a mask 14.
Form source and drain regions. Thereafter, after forming an interlayer film 8, a contact window 9 is opened, and a bit 11lI10 made of metal wiring is formed.

To explain the operation of the dynamic memory device formed in this example, the entire memory cell matrix array section is covered with a mask 14, and impurity ions are implanted to form n0 regions of the source and drain. Therefore, there is no injection onto the gate electrode of the switching MOS transistor constituting the memory cell, and there is no injection into the substrate.
The n-region is not formed and remains a low-concentration diffusion region equivalent to the n-region formed by impurity ion implantation of the LDD structure transistor, resulting in a structure in which damage caused by accelerated ion particles is reduced. This can prevent n+ type impurity ions implanted into the source and drain from penetrating the gate of the switching MOS transistor and forming an n+ diffusion layer in the channel region 11, and can prevent deterioration of transistor characteristics. . Furthermore, damage to the substrate due to ion implantation is reduced, leakage of capacitor stored charges to the substrate can be significantly reduced, and retention characteristics of stored information can be improved.

Further, unnecessary leakage current from the bit line to the substrate can be significantly reduced. In this embodiment, a memory cell having a two-dimensional structure is used, but the same applies to a memory cell having a three-dimensional structure.

Effects of the Invention As described above, according to the present invention, the characteristics of a switching MOS transistor constituting a unit memory cell can be maintained without deterioration even when the gate thin film is made thinner due to miniaturization.
By reducing the leakage of accumulated charge in the capacitor portion to the substrate and the leakage current from the bit line to the substrate, it is possible to realize a dynamic memory device with stable operation and excellent retention characteristics of stored information.

[Brief explanation of drawings]

FIG. 1 is a plan view of a unit memory cell of a dynamic memory device according to an embodiment of the present invention, FIG. 2 is a sectional view taken along the line A-A', and FIG. 3 is a plan view of a unit memory cell of a dynamic memory device according to a conventional technique. FIG. 4, a plan view of the unit memory cell, is a sectional view taken along line BB'. 1...Semiconductor substrate, 2...Element isolation region, 3...Capacitor section, 4...Capacitor counter electrode, 5...Switching MOS for
Gate electrode and word line of transistor, 6...
...N0 region by impurity ion implantation during LDD formation of switching MOS transistor, 7...
N+ region by impurity ion implantation when forming the source and drain of a switching MOS transistor, 8...
...Interlayer film, 9...Contact window, 10...
...Bit line by metal wiring, 1l...Switching MOS} transistor channel region, 12.
...N+ region caused by impurity ions penetrating through the gate when forming the source and drain, 13... Connection with the capacitor section which is one end of the switching MOS transistor, 14... Source , a mask to block impurity ions forming the drain.

Claims (2)

[Claims] (1) In the step of forming a dynamic memory device in which a switching MOS transistor is controlled by a word line potential, and one end of the transistor is connected to a capacitor section and the other end is connected to a bit line to constitute a unit memory cell, A method for manufacturing a dynamic memory device, characterized in that a mask pattern covering the entire memory cell matrix array section is used during impurity ion implantation for forming the source and drain of a MOS transistor. (2) The dynamic memory device according to claim 1, characterized in that a connection part with a capacitor part which is one end of the switching MOS transistor and a connection part with a bit line which is the other end are formed by low concentration diffusion. Production method.