JPH08107156A - Manufacture of non-volatile semiconductor storage device - Google Patents

Abstract

PURPOSE: To dispense with a process for forming a peripheral transistor by a method wherein the source.drain of a second MOS transistor is formed using a floating gate formed on a semiconductor region, which contains a region where the source.drain of a first MOS transistor is formed, as a mask. CONSTITUTION: A floating gate 5 is formed on a semiconductor region, which includes an N region where a P-region that forms the source.drain region of a P-channel MOS transistor is formed, using an ONO film 6 as a mask, wherein the ONO film 6 is etched through a control gate 8 as a mask. Then, the control gate 8 and the gate 9 of cells are patterned using the floating gate 5 as a mask, and then N-type impurities are injected into all the surface of a substrate for the formation of an N<-> region. At this point, the N<-> region is formed with the gates 9 of an N-channel MOS transistor and a P-channel MOS transistor as a mask.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device including a MOS transistor having a floating gate and a MOS transistor having no floating gate, which are formed in the same substrate.

[0002]

2. Description of the Related Art In a memory using a MOS transistor having a floating gate such as a flash memory,
M with floating gate used in cell
OS transistor (hereinafter referred to as cell), N channel M
There are transistors that require different characteristics from the OS transistor and the P-channel MOS transistor.

In the following, an example of a nonvolatile semiconductor memory device having a DINOR type cell structure will be described. Details of the DINOR method are described, for example, in Technical Bulletin Vol.93 No.74 P15-20, Onoda et al.
In the DINOR method, the Fuffler-Nordheim tunnel current is used for both program and erase operations.

Next, a conventional flash memory manufacturing process will be described. 13 to 20 are cross-sectional views schematically showing a memory that has undergone each process of manufacturing a conventional flash memory. FIG. 13 is a cross-sectional view of the semiconductor substrate after formation of P well and N well in which transistors are formed. In the figure, 1 is a semiconductor substrate, 2 is a P well formed in the semiconductor substrate 1, and 3 is an N well formed in the semiconductor substrate 1. Further, a region indicated by Ar1 is a cell formation region, and a region indicated by Ar2 is an N channel M.
The formation region of the OS transistor, the region indicated by Ar3 is P
This is a formation region of the channel MOS transistor.

A P well is formed in the cell and N channel MOS transistor forming regions Ar1 and Ar2, and a P channel MOS is formed.
Each mask is applied to form an N well in the transistor formation region Ar3. Then, boron is implanted into the regions Ar1 and Ar2 and phosphorus / boron is implanted into the region Ar3, and the subsequent heat treatment is performed to form the P well 2 and the N well 3. When n-polysilicon is used as the gate material, the boron implanted in the region Ar3 has a high threshold voltage V _th due to the work function. Therefore, a boron burying layer is formed on the surface to form the threshold voltage V th. _{Lower th} appropriately. Although not shown in the figure, if necessary, the cell and N-channel MOS
There may be a case where a separate implantation process is performed in which a mask is used to perform the implantation so as to change the impurity concentrations of the P wells Ar1 and Ar2 in which the transistors are formed.

Further, a plurality of transistors may be provided for both the N-channel MOS transistor and the P-channel MOS transistor for high breakdown voltage. In this case as well, a mask is applied to each transistor so that an appropriate channel concentration is obtained and an implantation step is performed. To provide.

Next, FIG. 14 is a sectional view of the semiconductor substrate showing a state after the tunnel oxide film and the floating gate are formed. In FIG. 14, 4 is a tunnel oxide film for forming the floating gate of the cell, and 5 is a floating gate formed on the tunnel oxide film 4 in the region Ar1 in which the cell is formed.

A desired tunnel oxide film 4 is formed on the entire surface of the substrate as a cell.
After forming, the polysilicon to be the floating gate of the cell is formed on the entire surface and is patterned.

FIG. 15 is a plan view showing the electrode arrangement of one MOS transistor. In FIG. 15, 10 is a gate electrode, 11 is a gate contact for making electrical connection with the gate electrode 10, 12 and 13 are source and drain regions, and 14 is source and drain regions 12 and 13.
Source / drain contacts for electrical connection with.

When patterning the floating gate, the cell is patterned only in the D1 direction, and is patterned in the D2 direction (on the source / drain of the cell) so that polysilicon remains. The D2 direction of the cell is patterned in a later process. Also, N-channel and P-channel MOS
Tunnel oxide film 4 on the periphery of the transistor
The polysilicon is removed using the as a stopper.

FIG. 16 is a sectional view taken along the line I--I of FIG. In FIG. 16, 10 is a gate electrode, 15 is a field oxide film for separating from other elements, and 16 is a gate insulating film formed under the gate electrode 10. For example, although not shown in FIG.
A field insulating film 15 is formed between the area Ar1, the area Ar2, and the area Ar3 shown in FIG. 4 in order to separate the elements formed in the respective areas.

FIG. 17 is a sectional view of the semiconductor substrate showing a state after the ONO film for insulating the floating gate and the control gate is formed. A silicon oxide film is formed on the entire surface by vapor deposition or thermal oxidation, and the oxide film on the floating gate 5 is removed except for the oxide film formed on the floating gate 5. At that time, the area Ar shown in FIG.
2, the tunnel oxide film 4 of Ar3 is also removed at the same time. Further, a silicon nitride film is formed on the entire surface and patterned so that the silicon nitride film on the floating gate 5 remains. Further, a silicon oxide film is formed on the silicon nitride film of the floating gate 5. The ONO film 6 thus formed insulates the floating gate 5 of the cell from the polysilicon of the control gate.

Next, FIG. 18 shows a control gate of a cell, a P channel MOS transistor and an N channel MOS.
It is sectional drawing of a semiconductor substrate which shows the state after forming the gate of a transistor. In FIG. 18, 7 is an N channel MO
A gate oxide film formed on the P well 2 and the N well 3 in the formation regions Ar2 and Ar3 of the S transistor and the P channel MOS transistor, 8 a control gate formed on the ONO film 6, and 9 a gate oxide film 7 It is the gate formed above.

In order to form the gate oxide film 7, the peripheral transistors are subjected to desired gate oxidation, and then polysilicon is formed on the entire surface and patterned. By this patterning, the control gate 8 and the N channel MOS
The transistor and the gate 9 of the P-channel MOS transistor are formed. Here, as the material of the control gate 8 and the gate 9 of the N-channel MOS transistor and the P-channel MOS transistor, not only polysilicon but also tungsten may be vapor-deposited on polysilicon to be silicided. After depositing polysilicon, the gate oxide film 9 is formed in the peripheral transistor and the ONO film is formed in the cell.
Polysilicon is patterned using the film 6 as a stopper. At this time, unlike the patterning in the case of the floating gate 5, the control gate 8 of the cell is also patterned in the D2 direction.

FIG. 19 is a cross-sectional view of the semiconductor substrate after the patterning of the floating gate in the D2 direction is completed. In the cell, the ONO film 6 and the floating gate 5 are patterned using the control gate 8 patterned in the previous step as a mask. At this time, although not shown, regions Ar2 and A in which peripheral transistors are formed
r3 is covered with a resist, and only the cell portion (region Ar1) is opened to perform the process.

First, the ONO film 6 is patterned using the floating gate 5 as a stopper, and then the floating gate 5 is patterned using the tunnel oxide film 4 as a stopper.

FIG. 20 is a sectional view of the semiconductor substrate showing a state after the source / drain of the cell is formed. In FIG. 20, 20 is a resist formed on the entire surface of the semiconductor substrate other than the region Ar 1, and 21 is a source / drain of the cell formed in the P well 2. Holes are formed in the resist only in the region Ar1 where cells are formed, and desired source / drain 21 is formed. In this example, the source / drain 21 of the cell is formed by the same implantation, but in some cases, only one of them is opened and the source / drain 21 is formed by different implantation.

Next, formation of the source and drain of the N-channel MOS transistor will be described. 21 is N
FIG. 9 is a cross-sectional view of the semiconductor substrate showing a state after N ⁻ regions for forming the source / drain of the channel MOS transistor are formed. In FIG. 21, 22 is a region Ar
A resist formed on the entire surface of the semiconductor substrate other than 2, 23
Is an N ^- region which constitutes the source / drain of the N-channel MOS transistor.

Only the region Ar2 where the N-channel MOS transistor is formed is opened, N-type impurities are implanted into the source / drain of the N-channel MOS transistor, and N
^-Form area 23. In general, in a transistor, a source / drain may be formed so as to partially overlap with a gate in order to secure a driving capability while ensuring reliability. Here, the N ⁻ region is formed by implanting an N-type impurity. This is done for this purpose. In the figure, the impurities are implanted perpendicularly to the substrate surface, but N-type impurities may be implanted at a predetermined angle under the gate to facilitate the implantation.

As shown in FIG. 22, the P channel M
In order to form the source / drain of the OS transistor, P as well as the N ⁻ region of the N channel MOS transistor
Impurities are implanted by opening only the region Ar3 where the channel MOS transistor is formed. In FIG. 22, 2
Reference numeral 4 is a resist formed on the entire surface of the semiconductor substrate other than the region Ar3, and 25 is a P ⁻ region formed in the N well 3.

FIG. 23 is a cross-sectional view of a semiconductor substrate showing a state of forming a source / drain of an N-channel MOS transistor after forming a sidewall. In FIG. 23, 2
Reference numeral 7 is a resist formed on the entire surface of the semiconductor substrate 1 other than the region Ar2, and 26 is a sidewall formed on the side of the gate of the transistor. After patterning the gate oxide film 7, sidewalls 26 are formed to perform appropriate source / drain implantation into the transistor. After that, only the region Ar2 where the N-channel MOS transistor is formed is opened and N-type impurities are implanted to form the N ⁺ region 28. In addition, we implanted P-type impurities by opening only Similarly area Ar3 and although not illustrated N-channel MOS transistor in the P-channel MOS transistors, conduct the formation of the P ⁺ region. Further, after the sidewall 26 is formed, the same N ⁺ region as the peripheral N-channel MOS transistor may be formed in the cell as well.

It should be noted that in the P-channel MOS transistor, the implantation is not performed to form the P ⁻ region by applying the resist, but after forming the side wall 26, the P-channel MOS transistor has such energy that it penetrates through the side wall 26. The implantation may be additionally performed at the time of implantation for forming the P ⁺ region.

In the manufacturing process of the conventional flash memory described above, the source and
N channel MOS transistor and P for drain formation
4 times including channel MOS transistor (3 times when forming P ^- region through sidewall)
When the desired source / drain formation is combined with the cell, the cost increase in the implantation process is remarkable as compared with other semiconductor memories such as DRAM / SRAM.

[0024]

Since the conventional nonvolatile semiconductor memory device is configured as described above, the source / drain injection into the cell, the source / drain injection into the N channel MOS transistor, and the P channel MOS transistor are performed. There is a problem in that the source / drain implantation into the semiconductor must be performed as a different implantation step, which requires many steps and the number of reticles required increases.

The present invention has been made to solve the above problems, and an object thereof is to reduce the steps for forming peripheral transistors and to reduce the number of reticles.

[0026]

A method of manufacturing a non-volatile semiconductor memory device according to a first aspect of the present invention comprises a first MOS transistor having a floating gate formed on one substrate and a first MOS transistor having no floating gate. A method of manufacturing a non-volatile semiconductor memory device, comprising: a conductive second MOS transistor, comprising:
To form a floating gate on a semiconductor region including a region where a source and a drain of an OS transistor are formed, and to form a source region and a drain region of the second MOS transistor using the floating gate as a mask. And a first implantation step of implanting an impurity of the first conductivity type.

A method of manufacturing a non-volatile semiconductor memory device according to a second aspect of the present invention is the method of manufacturing a non-volatile semiconductor memory device according to the first aspect of the present invention, wherein the non-volatile semiconductor memory device is a second conductive material having no floating gate. Type 3rd MO
An S-transistor is further provided, and the source region and the drain region of the third MOS transistor are implanted with the impurity of the first conductivity type in the first implanting step, and the impurity is implanted in the first implanting step. Compensating for impurities of the first conductivity type implanted into the source and drain regions of the third MOS transistor, and implanting impurities of the second conductivity type to form the source and drain of the third MOS transistor. It further comprises two injection steps.

A method of manufacturing a nonvolatile semiconductor memory device according to a third invention is the method of manufacturing a nonvolatile semiconductor memory device according to the second invention, wherein the source of the third MOS transistor is included in the first implanting step. And comparing the impurity of the first conductivity type implanted into the drain region and the impurity of the second conductivity type implanted into the source and drain regions of the third MOS transistor in the second implantation step, The impurities of the first conductivity type are the second impurities.
The first conductive type impurities are wider than the first conductive type impurities in a deeper region in the substrate, and the second conductive type impurities are wider in the channel direction than the first conductive type impurities.
An impurity of the conductivity type and the second conductivity type is implanted.

A method of manufacturing a non-volatile semiconductor memory device according to a fourth aspect of the present invention is the method of manufacturing a non-volatile semiconductor memory device according to the third aspect of the present invention, wherein the second conductivity type is injected in the second injection step. The implantation energy of the impurities is set to be shallower than the implantation energy of the impurities of the first conductivity type implanted in the first implantation step, and the implantation energy of the impurities is implanted in the second implantation step. The dose amount of the second conductivity type impurity is larger than the dose amount of the first conductivity type impurity implanted in the first implantation step.

A method of manufacturing a non-volatile semiconductor memory device according to a fifth aspect of the present invention is the method of manufacturing a non-volatile semiconductor memory device according to the fourth aspect of the present invention, wherein the second conductivity type is injected in the second injection step. It is characterized in that the impurities are further obliquely injected than the impurities of the first conductivity type which are injected in the first injection step.

[0031]

In the first injection step of the first invention, the second injection step is performed.
Since the floating gate formed in the step of forming the floating gate is used as a mask to form the source region and the drain region of the second MOS transistor, the resist for forming the source region and the drain region of the second MOS transistor is used. The step of forming the can be omitted.

The second implantation step in the second invention compensates for the impurities of the first conductivity type implanted in the source and drain regions of the third MOS transistor to form the third MOS transistor.
Since the source and drain of the transistor are formed, the source region and the drain region of the second MOS transistor are also formed in the first implantation step in the nonvolatile semiconductor memory device in which the third MOS transistor of the second conductivity type is present. It is possible to omit the step of forming a resist when implanting the first conductivity type impurity for forming the.

In the second injection step of the third invention,
Impurities of the first conductivity type can be made to exist in regions deeper than the impurities of the second conductivity type forming the source and drain regions of the third MOS transistor, and punch through hardly occurs in the third MOS transistor.

The implantation energy of the second conductivity type impurity implanted in the second implantation step in the fourth invention is
By making the implantation depth shallower than the implantation energy of the first conductivity type impurity implanted in the first implantation step, the second conductivity type impurity that constitutes the source and drain regions of the third MOS transistor is formed. Impurities of the first conductivity type can be present in a region deeper than the diffusion region. Then, by making the dose amount of the second conductivity type impurity implanted in the second implantation process larger than the dose amount of the first conductivity type impurity implanted in the first implantation process, The impurity of the first conductivity type injected into the source and drain regions of the MOS transistor No. 3 can be compensated.

By implanting the impurity of the second conductivity type implanted in the second implantation step in the fifth aspect of the invention more obliquely than the impurity of the first conductivity type, the source and the source of the third MOS transistor can be easily formed. The second conductivity type impurity forming the drain region may be wider in the channel direction than the first conductivity type impurity implanted in the source and drain regions of the third MOS transistor.

[0036]

【Example】

Example 1. The first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a cross-sectional view of a semiconductor substrate showing steps performed after formation of control gates of the cell shown in FIG. 18 and gates of P-channel MOS transistors and N-channel MOS transistors. In the figure, 6 is ONO from which the silicon oxide film on the surface side is removed.
Film, 30 N constituting the source and the drain of N-channel MOS transistor ^- region, 31 P constitutes the source and drain of the P-channel MOS transistor ^- a region ^- N made to the area to region.

Control gate 8 and gate 9 of the cell
After being patterned, N-type impurities are implanted into the entire surface of the substrate to form an N ⁻ region. At this time, N channel MOS
An N ⁻ region is formed by using the gate of the transistor and the P channel MOS transistor as a mask. Although not shown in FIG. 1, since a film similar to the field insulating film 15 shown in 17 is formed between the regions Ar1, Ar2 and Ar3, N-type impurities are implanted only in the active region. It

FIG. 2 is a sectional view of the semiconductor substrate showing a state after patterning of the floating gate of the cell.
In FIG. 2, 6 is an ONO film after being etched using the control gate 8 as a mask, and 5 is a floating gate which is etched using the etched ONO film 6 as a mask. This step can be performed in the same manner as the conventional patterning step shown in FIG.

The implantation process for forming the N ⁻ region, which has been conventionally performed by forming a resist, can be omitted because it is replaced by the implantation process for forming the N ⁻ region using the floating gate as a mask. . for that reason,
Not only can the manufacturing process be reduced, but the reticle required for resist formation can be omitted.

FIG. 3 is a sectional view of a semiconductor substrate showing a state of a P ⁺ region which constitutes a source / drain of a P channel MOS transistor. In the figure, 32 is an N ⁻ region which constitutes the source / drain of the cell, and 33 is a resist. From the state shown in FIG. 2, the regions Ar2 and Ar
3 is masked and N-type impurities are implanted only into the region Ar1 to form an N ⁻ region 32. Next, as shown in FIG. 3, a region other than the region Ar3 is masked and P-type impurities are implanted to form a P ⁻ region 34.

P-channel MOS transistor P ^- region 3
In comparison with the conventional method, the implantation energy so that the implantation of the N-type impurity forming the N ⁻ region 31 can be compensated for when forming 4
An implantation of P-type impurities having an implantation amount is added.

In FIG. 4, after forming the side wall, N
It is a cross-sectional view of a semiconductor substrate showing a step of forming the N ⁺ region and the P ⁺ region of the P-channel MOS transistor channel MOS transistor. 5 is the source of FIG.
It is sectional drawing which expanded a part of drain.

In the figure, 26 is a sidewall that covers the sidewalls of the control gate 8 and the floating gate 5 of the cell or the sidewalls of the gate 9 of the N-channel MOS transistor and the P-channel MOS transistor, and 38 is implanted using the sidewall 26 as a mask. N ⁺ region,
39 is P implanted using the sidewall 26 as a mask
⁺ Area.

The side wall 26 can be formed in the same manner as the conventional manufacturing method of the side wall 26 shown in FIG. After forming the sidewalls 26, first, a resist is formed on the entire surface of the semiconductor substrate except the region Ar2,
N-type impurities are implanted to form an N ⁺ region 38. N ⁺
When forming the region 38, N-type impurities are implanted using the sidewall 26 as a mask, and the region 30 under the sidewall 26 becomes an N ⁻ region.

Next, as shown in the figure, a resist is formed on the entire surface of the semiconductor substrate excluding the region Ar3 and P-type impurities are implanted to form a P ⁺ region 39. When the P ⁺ region 39 is formed, P-type impurities are implanted using the sidewall 26 as a mask to form the P ⁺ region.
The area 34 under 6 is a P ⁻ area. At this time, the previously implanted N-type impurities have already been compensated by the process shown in FIG.

The N ⁻ region 30 formed in the step shown in FIG. 1 is the same as the conventional N ⁻ region 23 shown in FIG.

On the other hand, the N ⁻ region 3 of the process shown in FIG.
In the implantation of N-type impurities of 0 and 31, for the cell, the control gate 6 covers the region where the source / drain of the cell is formed, and this serves as a mask.
It is possible to prevent the implantation of N-type impurities so as to substantially affect the cell characteristics.

Further, an N-type impurity is excessively implanted into the P-channel MOS transistor, but P and the implantation energy / implantation amount are adjusted so that the N-type impurity can be compensated in a later process. By adding the implantation of the type impurities, the same characteristics as the conventional one can be obtained. If necessary, the implantation at the time of forming the N well may be adjusted so that the characteristics are matched.

In FIG. 6, after forming the side wall, P
FIG. 9 is a cross-sectional view of the semiconductor substrate showing a state when forming P ⁺ regions and P ⁻ regions which form the source / drain of the channel MOS transistor. In FIG. 6, 40 is a region Ar in which a P-channel MOS transistor is formed.
Resists formed in regions other than 3, 41 is a P ⁻ region that constitutes a source / drain, and 42 is a P ⁺ region that constitutes a source / drain. Here, before injecting the P-type impurity, P ^- Since region 41 and P ⁺ region 42 is N-type impurities are implanted, implanting P-type impurities in order to compensate it, further P ^- region Implantation is needed to form 41 and P ⁺ regions 42.

As described above, by forming the N ⁻ region using the floating gate as a mask, a plurality of resist forming steps can be omitted as compared with the N ⁻ region forming step of the conventional N channel MOS transistor. The number of reticles is reduced, and as a result, the cost for forming peripheral transistors of the flash memory can be reduced.

Example 2. A method of manufacturing a nonvolatile semiconductor memory device according to the second embodiment of the present invention will be described with reference to FIGS. FIG. 7 is a sectional view for explaining the occurrence of punch through in a conventional P channel MOS transistor. In the figure, 50 is 0V to which the source is connected
Potential point, 51 is -Vd potential point to which drain is connected, 5
Reference numeral 2 is a path through which a current flows during punch-through, and 53 is a boundary line indicating the boundary of the depletion layer. Since it is necessary to use a transistor having a short gate length L because it is necessary to reduce the transistor characteristics and size, a depletion layer extends from the drain to the source as shown in FIG. 7 unless an appropriate channel structure is selected. When it reaches, punch through is likely to occur.

Instead of completely compensating the N ^- region implanted in the P-channel MOS transistor,
Although the P ⁻ region is formed, a part of the N ⁻ region is left so that the OS transistor characteristics are substantially equivalent.
^- characterized in that it utilizes an area as a punch-through stopper.

Normally, in a buried P-channel transistor, phosphorus is used as a channel structure of 120 to 200 KeV1E.
12 ~ 1E13cm ^-3 , boron 10 ~ 50KeV1
Inject about E12 to 1E13 cm ^-3 . FIG. 9 is a graph showing the concentration of impurities in the depth direction from the surface of the P-channel MOS transistor along the line XX shown in FIG. It can be seen from the graph that a large amount of boron, which is a P-type impurity, exists near the surface, and the deeper the depth, the larger the amount of phosphorus diffused to form the N well. The region near this surface is a buried boron layer.

Further, as the implantation for forming the N ⁻ region, implantation of N-type impurities is carried out at 30 to 100 KeV5E12 to
It is performed under the condition of about 5E13.

FIG. 8 is a sectional view of a semiconductor substrate showing the structure of a flash memory formed by the method for manufacturing a nonvolatile semiconductor memory device according to the second embodiment of the present invention.
The implantation depth of the P-type impurity (boron / BF2 implantation) for compensating the N-type impurity implanted region of the P-channel MOS transistor into the silicon substrate is shallower than that of the N-type impurity implantation, and the transistor characteristics are similar to those of the prior art. Then, as shown in FIG. 8, a structure such as the N ⁻ region 55 can be left. For example, N ^- in order to obtain a structure such as region 55, N ^- compared with injection of N-type impurity for forming the region 55, P ^- small implantation depth Rp of the P-type impurity compensation implantation region 39 Use the same energy and increase the dose amount. By doing so, the P ⁻ region 39 is formed in a shallow and high concentration on the surface of the substrate, and the N ⁻ region 55 is left immediately below the P ⁻ region 34 even though it is a P channel MOS transistor having substantially the same characteristics. To do.

FIG. 10 is a graph showing the concentration of impurities in the depth direction from the surface of the P-channel MOS transistor along the line YY and the line ZZ shown in FIGS. As shown in FIG. 10, the simulation result shows the distribution of the impurity concentration of the flash memory according to the second embodiment with respect to the conventional curve showing the distribution of the impurity concentration between 0.15 and 0.2. The curve is at the top, indicating that the flash memory according to the second embodiment has a higher content of phosphorus, which is an N-type impurity.

After that, when the side wall 26 is formed and a P-type impurity is implanted, the P-type impurity concentration is generally high, so that in the depth direction, incidentally when the N-channel MOS transistor is formed in the step shown in FIG. The N ⁻ region 31 of the formed P channel MOS transistor is completely compensated.

FIG. 11 shows characteristics of the impurity concentration in the depth direction of the substrate in the P ⁺ region of the P channel MOS transistor of the flash memory formed by the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment of the present invention. It is a graph shown. As described above with reference to FIG. 11, it can be seen that the N ⁻ region is completely compensated for in the P ⁺ region.

Example 3. A method of manufacturing a nonvolatile semiconductor memory device according to the third embodiment of the present invention will be described with reference to FIG. In FIG. 12, 60 is a P channel MOS
P ^- region that constitutes the source / drain of the transistor,
Reference numeral 61 is a locus of the P-type impurity implanted to form the P ⁻ region 60. As shown in the figure, the locus 61 of the P-type impurity is D2 with respect to the vertical line standing on the surface of the semiconductor substrate.
It has an angle θ1 in the direction. In addition, the locus of the N-type impurities when implanting the N-type impurities can have an angle θ2 in the D2 direction with respect to the perpendicular line standing on the surface of the semiconductor substrate. In this way, the driving angle θ1,
By giving θ2, P ⁻
The region 60 and the N ⁻ region 31 can be expanded.

The implantation angle θ1 of the P-type impurity for forming the P ⁻ region 60 is larger than the implantation angle θ2 of the N-type impurity for forming the N ⁻ region 60. Compared with the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment,
It is possible to prevent the ratio of N-type impurities to P-type impurities from increasing in the channel direction of the P-channel MOS transistor.

The implantation for forming the N ⁻ region 31 is generally performed at an angle of about 45 deg. On the other hand, in the implantation for forming the P ⁻ region 60, for example, by performing the implantation at 60 deg, the N
^- it is possible to form the region as a punch-through stopper. The graph shown in FIG. 10 shows the results when the N ⁻ region was formed at 45 deg and the P ⁻ region was formed at 60 deg.

In this embodiment, the N ⁻ region is formed on the entire surface of the substrate by implanting N type impurities, and the P channel MO is formed.
This is compensated by the S transistor, but not limited to this, the P ⁻ region is formed on the entire surface of the substrate, and the N channel MO is formed.
Compensation injection may be performed by the S transistor. In this case, the punch-through improving effect can be considered as well.

However, the cell structure is not essential in the present invention, and can be similarly applied to the NOR system and other systems.

[0064]

As described above, according to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, the first MOS is provided.
Using the floating gate left over the semiconductor region including the region where the source and drain of the transistor should be formed as a mask, impurities of the first conductivity type for forming the source region and the drain region of the second MOS transistor are used. Since it is configured to include the first implanting step of implanting, a step of forming a mask for implanting impurities of the first conductivity type to form the source region and the drain region of the second MOS transistor. And reticle can be omitted, and the number of steps can be reduced and the steps can be simplified.

According to the method for manufacturing a non-volatile semiconductor memory device of the second aspect of the present invention, the third MO in the first implantation step is used.
Since the impurities of the first conductivity type implanted into the source and drain regions of the S transistor are compensated and the impurities of the second conductivity type are implanted to form the source and drain of the third MOS transistor, a nonvolatile semiconductor The memory device does not have a floating gate and is a third MO of the second conductivity type.
Even when the S transistor is provided, it is possible to omit a step and a reticle for forming a mask for implanting impurities of the first conductivity type to form the source region and the drain region of the second MOS transistor. There is an effect that the number of steps can be reduced and the steps can be simplified.

According to the method of manufacturing a non-volatile semiconductor memory device of the third aspect of the invention, the impurities of the first conductivity type are wider than the impurities of the second conductivity type in a deeper region in the substrate,
The impurities of the second conductivity type may be wider in the channel direction than the impurities of the first conductivity type, and punch-through is performed by the impurities of the first conductivity type existing in a region deeper than the impurities of the second conductivity type. Can be hard to occur,
There is an effect that the reliability of the nonvolatile semiconductor memory device can be improved.

According to the method of manufacturing a non-volatile semiconductor memory device of the fourth aspect, the implantation energy of the second conductivity type impurity implanted in the second implantation step is implanted in the first implantation step. The implantation depth is made shallower than the implantation energy of the first conductivity type impurity, and the dose amount of the second conductivity type impurity implanted in the second implantation step is implanted in the first implantation step. Since it is larger than the dose amount of the first conductivity type impurities to be generated,
Second conductivity type impurities exist in the channel direction of the first conductivity type impurities forming the source and drain regions of the MOS transistor, and the first conductivity type is present in a region deeper than the second conductivity type diffusion region in the substrate. It is easy to make the type impurities exist, and it is possible to easily manufacture a highly reliable nonvolatile semiconductor memory device in which punch-through hardly occurs.

According to the method of manufacturing a nonvolatile semiconductor memory device of the fifth aspect, the second conductivity type impurity implanted in the second implantation step is first implanted in the first implantation step. Since the impurities of the second conductivity type are implanted more obliquely than the impurities of the second conductivity type, the impurities of the second conductivity type are likely to exist widely in the channel direction of the first conductivity type impurities forming the source and drain regions of the third MOS transistor. Therefore, it is possible to easily manufacture a highly reliable nonvolatile semiconductor memory device in which punch-through does not easily occur.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor substrate showing a step of manufacturing a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the semiconductor substrate showing a step of manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view of the semiconductor substrate showing a step of manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view of the semiconductor substrate showing a step of manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

5 is an enlarged cross-sectional view of a part of the source / drain of FIG.

FIG. 6 is a sectional view of a semiconductor substrate showing a step of manufacturing another nonvolatile semiconductor memory device according to the first embodiment of the invention.

FIG. 7 is a sectional view of a conventional P-channel MOS transistor for explaining punch-through.

FIG. 8 is a P-channel MO formed by the method for manufacturing a nonvolatile semiconductor memory device according to the second embodiment of the present invention.
It is sectional drawing which shows the structure of an S transistor.

9 is a graph showing the impurity concentration in the depth direction from the surface of the P-channel MOS transistor along the line XX of FIG.

10 is a graph showing the impurity concentration in the depth direction from the surface of the P-channel MOS transistor taken along line YY of FIG. 7 and line ZZ of FIG.

FIG. 11 is a graph showing characteristics of impurity concentration in the P + region of the P-channel MOS transistor of the flash memory according to the second embodiment of the present invention in the depth direction from the substrate surface.

FIG. 12 is a P channel M according to a third embodiment of the present invention.
FIG. 6 is a cross-sectional view of a P-channel MOS transistor showing a step of manufacturing the source / drain of the OS transistor.

FIG. 13 is a cross-sectional view of a semiconductor substrate showing a step of manufacturing a conventional nonvolatile semiconductor memory device.

FIG. 14 is a cross-sectional view of a semiconductor substrate showing a step of manufacturing a conventional nonvolatile semiconductor memory device.

FIG. 15 is a plan view showing a part of the configuration of a conventional nonvolatile semiconductor memory device.

FIG. 16 is a cross-sectional view for explaining a step of manufacturing the conventional nonvolatile semiconductor memory device.

FIG. 17 is a cross-sectional view of a semiconductor substrate showing a step of manufacturing a conventional nonvolatile semiconductor memory device.

FIG. 18 is a cross-sectional view of a semiconductor substrate showing a step of manufacturing a conventional nonvolatile semiconductor memory device.

FIG. 19 is a cross-sectional view of a semiconductor substrate showing a step of manufacturing a conventional nonvolatile semiconductor memory device.

FIG. 20 is a cross-sectional view of a semiconductor substrate showing a step of manufacturing a conventional nonvolatile semiconductor memory device.

FIG. 21 is a cross-sectional view of a semiconductor substrate showing a step of manufacturing a conventional nonvolatile semiconductor memory device.

FIG. 22 is a cross-sectional view of the semiconductor substrate showing a step of manufacturing a conventional nonvolatile semiconductor memory device.

FIG. 23 is a cross-sectional view of a semiconductor substrate showing a step of manufacturing a conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

1 semiconductor substrate, 2 P well, 3 N well, 4 tunnel oxide film, 5 floating gate, 6 ONO
Film, 7 gate oxide film, 8 control gate, 9
Gate, 26 sidewall, 30, 31, 32 N
^- regions, 33 and 37 resist, 34 P ^- region 38
N ⁺ region, 39 P ⁺ region.

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 27/115

Claims (5)

[Claims] 1. A method of manufacturing a non-volatile semiconductor memory device comprising a first MOS transistor having a floating gate and a second MOS transistor of a first conductivity type having no floating gate formed on one substrate. Forming a floating gate on a semiconductor region in the substrate including a region where a source and a drain of the first MOS transistor are to be formed, and using the floating gate as a mask, A first implanting step of implanting a first conductivity type impurity to form a source region and a drain region, and a method for manufacturing a non-volatile semiconductor memory device. 2. The non-volatile semiconductor memory device further includes a second MOS transistor of a second conductivity type having no floating gate, wherein the source region and the drain region of the third MOS transistor have the first MOS transistor. In the first implanting step, the first conductive type impurities are implanted, and the first conductive type impurities implanted in the source and drain regions of the third MOS transistor in the first implanting step are compensated for, The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, further comprising a second implantation step of implanting an impurity of a second conductivity type to form the source and the drain of the third MOS transistor. 3. The impurity of the first conductivity type implanted into the source and drain regions of the third MOS transistor in the first implantation step, and the third MOS transistor in the second implantation step. Comparing the impurities of the second conductivity type injected into the source and drain regions, the impurities of the first conductivity type are wider than the impurities of the second conductivity type in a deeper region in the substrate, and The second conductivity type impurities are wider in the channel direction than the first conductivity type impurities, so that the first conductivity type impurities and the second conductivity type impurities are present.
The method for manufacturing a nonvolatile semiconductor memory device according to claim 2, wherein conductivity type impurities are implanted. 4. The implantation energy of the impurities of the second conductivity type, which is implanted in the second implantation step, is set to the first implantation energy.
The implantation depth is made shallower than the implantation energy of the first conductivity type impurity implanted in the second implantation step, and the dose amount of the second conductivity type impurity implanted in the second implantation step. 4. The method for manufacturing a nonvolatile semiconductor memory device according to claim 3, wherein the dose is larger than the dose amount of the impurities of the first conductivity type implanted in the first implanting step. 5. The impurity of the second conductivity type implanted in the second implantation step is further obliquely implanted than the impurity of the first conductivity type implanted in the first implantation step. 5. The method for manufacturing a non-volatile semiconductor memory device according to claim 4, further comprising: