JPS63136557A - Memory - Google Patents

Abstract

PURPOSE:To manufacture a dynamic type memory having the excellent holding characteristics of memory information by constituting the region of a connecting section with a capacitor section as one end of a MOS transistor for switching by a low-concentration diffusion region equal to a low-concentration drain region. CONSTITUTION:An element isolation region 2 is formed onto a semiconductor substrate 1, and impurity ions are implanted to a capacitor section 3 to shape an N+ region. Since the region of a connecting section with the capacitor section 3 as one end of a MOS transistor for switching is covered with a mask 12 and impurity ions are implanted, the N<+> regions of a source and a drain are not formed, a low concentration region equal to an N<-> region through the implantation of impurity ions in an LDD-structure transistor is shaped as it is, ions are implanted only once, structure in which the damage of the substrate is reduced is formed, and the leakage to the substrate of storage charges in the capacitor section can be minimized remarkably, thus improving the holding characteristics of memory information.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a dynamic memory device capable of suppressing leakage of charges stored in a capacitor of a memory cell and improving retention characteristics of stored information.

Conventional technology In recent years, with the miniaturization of devices, deterioration of transistor characteristics due to hot electrons has become a problem, and as a countermeasure to this problem, semiconductor devices using transistors with a low concentration drain region structure, so-called LDD structure, have become mainstream. .

A conventional dynamic storage device will be explained below. FIG. 3 is a plan view of a unit memory cell of a conventional dynamic memory device, and FIG. 4 is a cross-sectional view taken along line BB'. 1 is a semiconductor substrate, 2 is an element isolation region, 3 is an n+ region formed by ion implantation in a capacitor portion, 4 is a capacitor counter electrode of the first polysilicon layer, 5 is a switching transistor and word line of the second polysilicon layer, 6 7 is an n-region formed by impurity ion implantation during formation of the switching transistor L and DD; 7 is an n-small region formed by impurity ion implantation during formation of the switching transistor source and drain; 8 is an interlayer film; 9 is a contact window; 10 is a bit line made of aluminum wiring. The operation of the dynamic storage device configured as described above will be described below. First, the switching transistor of the unit memory cell selected by the word line 5 and the bit line 9 is turned on, and during writing, charge corresponding to the potential of the bit line is accumulated in the n+ region 3 of the capacitor section. At the time of reading, the accumulated charge in the capacitor section is read onto the bit line. -1 of memory information
, "O" is distinguished by whether or not charge is accumulated in the capacitor section, which means that the difference between the amount of charge read on the bit line and the comparison reference amount of charge generated by the dummy cell is amplified by the sense amplifier. This is realized by

Problems to be Solved by the Invention However, in the above conventional configuration, the switching MO
A high concentration region 11 is formed at the connection part with the capacitor part 3, which is one end of the 8l-transistor, by forming an LDD structure, followed by forming a source/drain, and implanting impurity ions twice. The collision causes damage to the substrate in this area. As a result, the accumulated charges in the capacitor section are likely to leak (and the direction of the leakage current is the direction in which electrons are injected from the substrate to the capacitor section since the substrate bias ≦ OV). The present invention has the problem that the potential of the storage device decreases, resulting in poor retention characteristics of stored information.The present invention aims to solve the above-mentioned problems, and aims to provide a dynamic storage device with excellent retention characteristics of stored information. purpose.

Means for Solving the Problems In order to achieve this object, the dynamic memory device of the present invention has a low concentration region that is equivalent to the low concentration drain region in the region connecting to the capacitor portion, which is one end of the switching MOS transistor. It consists of a concentration diffusion region.

Effect: With this configuration, there is no n+ region formed by impurity ion implantation to form the source and drain at the connection part with the capacitor part, which is one end of the switching MO3 transistor.
Therefore, damage to the substrate due to ion implantation can be reduced, leakage current in the storage cell capacitor portion can be suppressed, and retention characteristics of stored information can be improved.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of a unit memory cell of a dynamic memory device according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along line AA'. That is, after forming the element isolation region 2 on the semiconductor substrate 1, impurity ions are implanted into the capacitor section 3 to form an n+ region. Next, after performing gate oxidation, a first polysilicon layer is formed and patterned to form the capacitor counter electrode 4. Furthermore, after performing gate oxidation, a second polysilicon layer is formed and patterned to form the gate electrode of the switching transistor and the word line 5. Using this polysilicon layer as a mask, impurities are selectively ion-implanted,
After forming an n-region for an LDD structure transistor, a sidewall is formed using an oxide film. Next, using a mask 12, the region of the connection portion with the capacitor portion, which is one end of the switching MOS transistor, is covered and impurity ions are implanted to form the n+ region 7 of the source and drain.

Thereafter, after forming an interlayer film 8, a contact window is opened and a bit line 10 made of aluminum wiring is formed.

The operation of the dynamic storage device of this embodiment configured as described above will be described below. The region connected to the capacitor section, which is one end of the switching MOS transistor, is covered with a mask 12 and impurity ions are implanted. Therefore, the n-middle region of the source and drain is not formed, and the impurity of the LDD structure transistor is not formed. It remains a low-concentration region equivalent to the n- region created by ion implantation, and the number of ion implantations is only one, resulting in a structure that reduces damage to the substrate and prevents leakage of accumulated charges in the capacitor to the substrate. It can be significantly reduced and the retention characteristics of stored information can be improved. The pattern of the mask 12 is a rectangular pattern in this embodiment, but it goes without saying that any pattern may be used as long as it can cover the area of the connection with the capacitor section, which is one end of the switching MOS transistor. .

Effects of the Invention As described above, according to the present invention, it is possible to reduce the leakage of accumulated charges in the capacitor portion to the substrate, thereby realizing a dynamic memory device with excellent retention characteristics of stored information.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a unit memory cell of a dynamic memory device according to an embodiment of the present invention, FIG. 2 is a sectional view taken along the line A-A', and FIG. 3 is a plan view of a unit memory cell of a dynamic memory device according to a conventional technique. FIG. 4, a plan view of the unit memory cell, is a sectional view taken along line BB'. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Element isolation region, 3... Capacitor section, 4... Capacitor counter electrode, 5... Switching MO3 for
Transistor gate electrode and word line, 6...
. . . N- region by impurity ion implantation when forming an LDD of a switching transistor, 7 . . . N + region 8 by impurity ion implantation when forming a source and drain of a switching MOS transistor. Interlayer film, 9...Contact window, 10...Arylemium wiring, 11...N for switching
Connection part with the capacitor part which is one end of the OS transistor, 12...Mask pattern for blocking impurity ions forming the source and drain. Name of agent Patent attorney Toshio Nakao and 1 other famous confectioners 1 Figure 3 Figure 4

Claims (1)

[Claims] In a memory device in which a switching MOS transistor using a lightly doped drain structure is controlled by a word line potential, and one end of the transistor is connected to a capacitor section and the other end is connected to a bit line to form a unit memory cell, the above-mentioned switching A memory device characterized in that a connection part with a capacitor part, which is one end of a transistor, is formed of a low concentration diffusion region.