JPH03247038A - Multiplex system - Google Patents

Abstract

PURPOSE:To obtain a multiplex circuit facilitating the synchronization of a data with a block pulse by applying speed conversion to a transmission line signal read from a storage means. CONSTITUTION:A multiplex circuit 3 is provided with elastic storage devices 4, 5, speed conversion circuits 6, 7 a timing generating circuit 8, AND gates 9-12 and an OR gate 13, and receives data from code conversion circuits 1, 2 and multiplexes them and outputs a multiplexed data. That is, an output data from the code conversion circuits 1, 2 is written once in the elastic storage devices 4, 5 by using a clock and a block pulse outputted from the code conversion circuits 1,2 and read the data by using other clock and block pulse. Thus, no delay circuit is required and the adjustment of the delay time is not called for.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a multiplexing circuit, and particularly in digital communication, inputs a plurality of signals converted into transmission line codes, multiplex-converts these input signals to make a multiplexed signal, and then transmits the multiplexed signal in the same manner as before conversion. This paper relates to road codes and multiplexing methods.

[Conventional technology]

Here, a conventional multiplexing circuit of this type will be explained with reference to FIGS. 3 and 4. In FIG. 3, a multiplexing circuit with a multiplexing number of 2 is shown. Here, the transmission path code is n81c, and the transmission speeds before and after multiplexing are each '0+Zf6. The multiplexing circuit 36 includes a speed conversion circuit 37 and a 38° timing generation circuit 39. AND game) 40-430R gate 4
4. and delay circuits 59 and 6o, and outputs multiplexed data after inputting data from code conversion circuits 34 and 35 and multiplexing the data twice, as described later. In the multiplexing circuit 36 shown in FIG.
(n+1) block pulse 48 (n is a positive integer) 9 frequency 2fo clock 49 (replacement pulse 51 according to the multiplicity) is output. The code conversion circuit 34 receives the clock 47 and the block pulse 48, The data 45 is output in synchronization with the block pulse 48.The data 45 is delayed by a delay amount that is in phase with the block pulse 48 in a delay circuit 59, and then inputted as data 61 to the speed conversion circuit 37.Speed conversion circuit Clock 4 on 37
7. 2fo with block pulse 48 and AND gate 40
A clock 52 generated by the product of a clock 49 and a switching pulse 50 is input, and data 61 at a transmission rate f0 is converted into burst data 54 at a transmission rate 2fo and output. AND gate 42 inputs data 54 and switching pulse 50, and outputs data 56 for tooth extraction. Similarly, the code conversion circuit 35 inputs the clock 47° and the block pulse 48, and outputs data 46 synchronized with these by the delay circuit 6° and the block pulse 48.
After being delayed to be in phase with 8, data 6
2 is input to the speed conversion circuit 38. The speed conversion circuit 38 uses a clock 47. Block pulse 48 and AND
The gate 41 converts the data 62 at the transmission rate f0 generated by the product of the 2fo clock 49 and the switching clock 5 to burst data 55 at the transmission rate 2fo and outputs it. AND gate 43 inputs data 55, switching pulse 55, and switching pulse 51, and outputs data 57 for tooth extraction. O
The R gate 44 inputs the missing data 56 and 57 and outputs the multiplexed data 58 as an OR output.

[Problems to be Solved by the Invention] By the way, in the multiplexing circuit described above, the code conversion circuit 34
35 and the multiplexing circuit 36; in order to prevent the influence of delays inside the code conversion circuits 34 and 35, delay circuits 59 and 6o are provided, and these delay circuits 59
and 60, it is necessary to delay data 45 and 46 by a predetermined delay amount and provide data 61 and 62 synchronized with block pulse 48 to speed conversion circuits 37 and 38.
It is extremely difficult to set the delay amounts of 9 and 60. Therefore. There is a problem in that it is difficult to synchronize the data 61 and 62 with the block pulse 48. An object of the present invention is to provide a multiplexing circuit in which synchronization of data to block pulses is extremely easy. [Means for solving the problem] According to the present invention, a transmission line signal having a transmission code length defined by a first block pulse is generated in synchronization with a predetermined first clock. In the multiplexing method, the code conversion circuit includes a plurality of code conversion circuits that output the transmission line signal, and a multiplexing circuit that receives the transmission line signal and converts the speed at different timings. generation means for generating a block pulse and a second clock synchronized with the first clock, and the multiplexing circuit generates the transmission line signal based on the second clock and the second block pulse. is written, and the transmission line signal is read out based on the first clock and the first block pulse, and the transmission line signal is speed-converted based on the first block pulse. A multiplexing system is obtained, characterized in that the multiplexing circuit has the first clock and the first clock.
Pulse generating means for generating block pulses is provided.

[Example] Next, the present invention will be explained by referring to an example. 1 and 2, a multiplexing circuit 3 according to the invention includes elastic stores 4 and 5. Speed conversion circuits 6 and 7. Timing generation circuit 8. AND gates 9-12.
Equipped with OR gate 13. After inputting the data of code conversion circuits 1 and 2 and multiplexing the data into two, the multiplexed data is output. The timing generation circuit 8 outputs a switching pulse 26 with a frequency f0 clock of 16° inverted. The code conversion circuit 1 receives a clock 16. A block pulse 17 is input, and data 14 synchronized therewith, a clock 18 of frequency lf0, and a block pulse 19 are output. Data 14 is written to elastic store 4 using clock 18 and block pulses 19. The data written in the elastic store 4 is then read out by the clock 16 and block pulse 17. As a result, data 22 synchronized with block pulse 17 is read out. Speed conversion circuit 6 receives data 22 and clocks 16 . block pulse 17, and AND
A clock 27 generated by multiplying the 2fo clock 24 and the switching pulse 25 is input to the gate 9, and the transmission rate f is input.
0 data 22 is converted into burst data 29 at a transmission rate of 2ro.
The speed is converted to and output. AND gate 11 is data 2
9 and switching pulse 25 are input, and burst data 31 is output. Similarly, the code conversion circuit 2 receives a clock 16° block pulse 17 and outputs data 15, a clock 21, and a block pulse 22 synchronized therewith. This data 15 is written to the elastane ink store 5 using a clock 21 and a block pulse 22. and,
Data written to the elastic store 5 is read out using a clock 16 and a block pulse 17. As a result, data 23 synchronized with block pulse 17 is read out. The speed conversion circuit 7 receives the data 23, inputs the clock 16, the block pulse 17, and the clock 28 generated by the product of the 2fo clock 24 and the switching pulse 26 at the AND gate 10, and transmits the data 23 at the transmission speed f0. The speed is converted to burst data 30 with a speed of 2fo and output. AND gate 12 inputs data 30 and switching pulse 26 and outputs burst data 32. OR gate 13 receives burst data 31 and 32 and outputs multiplexed data 33 as an OR output. Although the case of two multiplexes has been described above, it is easy to understand that in the case of three or more multiplexes, the number of elastic stores can be similarly increased according to the degree of multiplexing.

【Effect of the invention】

As described above, in the present invention, an elastic store is provided, and after the output data from the code conversion circuit is once written into the elastic store using the clock and block pulse output from the code conversion circuit, other clocks,
Since reading is performed using block pulses, there is no need to provide a delay circuit and no need to adjust the delay time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the multiplexing circuit according to the present invention, FIG. 2 is a time chart for explaining the operation of the multiplexing circuit shown in FIG. 1, and FIG. 3 is a conventional multiplexing circuit. FIG. 4 is a time chart for explaining the operation of the multiplexing circuit shown in FIG. 3. 1.2... code conversion circuit, 3... multiplexing circuit, 45
...Elastic store, 6.7... Speed conversion circuit, 8... Timing generation circuit, 9, 10, 11゜1
2...AND gate, 13...OR gate, 1
4゜15...Data, 16...Clock, 17...
- Block pulse, 18...clock, 19...block pulse. 20... Clock, 21... Flock pulse, 22
゜23...Data, 24...2fo clock, 25
．． 26...Switching pulse, 27.28...Clock,
29,30°31.32...Data, 33...Multiplexed data, 34°35...Code conversion circuit, 37.38
...Speed conversion circuit. 39...timing generation circuit, 40.41, 42°4
3...AND gate 44...OR gate 45°46...data, 47...clock, 48...block pulse, 49...2f, clock, 50.51
...Switching pulse, 52.53...Clock, 54.
55°56.57...data, 58...multiplexed data, 59°60...delay circuit. Figure multiplexing circuit 36

Claims (1)

[Claims] 1. A plurality of code conversion circuits that output transmission line signals having a transmission code length defined by a first block pulse in synchronization with a predetermined first clock; and the transmission line signals. In the multiplexing system, the code conversion circuit includes a second block pulse synchronized with the transmission path signal and a second block pulse synchronized with the first clock. The transmission line signal is written in the multiplexing circuit based on the second clock and the second block pulse, and the transmission path signal is written in the multiplexing circuit based on the first clock and the first block pulse. 1. A multiplexing system comprising: storage means for reading out the transmission line signal based on pulses; and speed conversion of the transmission line signal read from the storage means. 2. In the multiplexing system described in claim 1, the multiplexing circuit is equipped with pulse generation means for generating the first clock and the first block pulse. multiplexing method.