JPH0324698B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for sharing a storage device among a plurality of processing devices in a data processing system configured with a plurality of processing devices and a storage device shared by a group of the processing devices. Regarding the method.

FIG. 1 shows a configuration diagram of a conventional time-division memory sharing method, and FIG. 2 shows an explanatory diagram of the operation of the conventional method.

As shown in FIG. 1, processing units (hereinafter abbreviated as CPUs) 91 to 94 are connected to the shared memory 4 via a time division control unit 10. The time division control unit 10 sequentially allocates time slots (hereinafter abbreviated as states) in which data exchange with the shared memory 4 is permitted to each of the CPUs 91 to 94 asynchronously and independently of the CPU group. Therefore, even a CPU that wants to send and receive data quickly has the disadvantage of having to wait until its own state arrives, just like other CPUs.
For example, as shown in FIG. 2, even if six internal requests are made to the shared memory within the CPU 91 at the timing shown, data can only be exchanged three times within time T1. For this reason, this time-sharing memory sharing method becomes a bottleneck for CPUs that operate in real time or for CPUs that handle a large amount of information, and has the drawback of contributing to a decline in the processing performance of the entire system.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing system that uses a time-sharing memory sharing method and has high processing performance, which has been made to eliminate the above-mentioned drawbacks of the conventional methods.

The present invention is characterized by determining one or more priority CPUs among a group of CPUs, and performing time-sharing control of the shared memory in synchronization with the operation of the priority CPUs. Forcibly prioritize the next state if
The reason is that it is allocated to the CPU. The present invention will be explained below with reference to the drawings.

FIG. 3 is a diagram showing the principle of the time-division memory sharing system according to the present invention. With CPU91 as the priority CPU, the states are sequentially synchronized with its basic operation clock.
Assigned to CPUs 91-94. Also, CPU
The synchronization control circuit 50 built into the time division control unit 5 is provided with a function of allocating the next state to the CPU 91 when an access request from the CPU 91 is detected.

FIG. 4 is an explanatory diagram of the operation of the present invention. Since the time division control unit 5 is synchronized with the CPU 91,
The change point of the time division state is always the same as the time point when the internal request of the CPU 91 is generated. The changing point of the time division state is the point at which access from each CPU 91 to 94 can be switched, and the shared memory 4 has
Access from the CPU is also allowed. Therefore, the synchronous control circuit 50 suddenly changes the next state to the CPU 91.
It does not affect the operation of other CPUs even if it is assigned to a CPU.

According to the present invention, in FIG. 4, for example, the occurrence of six times within time T1 at the illustrated timing
It is possible to process all internal requests of the CPU 91 without waiting time.

Next, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 5 is a block diagram of an embodiment of the present invention, showing a terminal control device that controls terminals connected via a line. CPUs 1 and 2 and a refresh circuit 3 are connected to a shared memory 4 via a time division control section 5. CPU1 is for business management,
A dedicated memory 7 of the CPU 1 and a disk device 8 are connected, and programs for the CPU 1 are stored in the dedicated memory 7. The CPU 1 normally creates transmission data, decomposes received data, etc., and transfers transmission data to a terminal from the dedicated memory 7 or disk device 8 to the shared memory 4, or stores the data in the shared memory 4. Since the shared memory 4 is not accessed except when transferring data received from a terminal connected to the dedicated memory 7 or disk device 8, the CPU
1 accesses the shared memory 4 very rarely. Therefore, even if the access time to the shared memory 4 becomes a little longer, there is almost no effect on the entire device, so the CPU 1 is treated as a non-priority CPU.

The CPU 2 is for line control, and is connected to a line control unit 6, which transfers transmission data stored in the shared memory 4 to the terminal via the line, stores received data from the terminal in the shared memory 4, and so on. , real-time processing is required to control line procedures. Also, shared memory 4 and CPU 2
, the CPU 2 accesses the shared memory 4 extremely frequently. Therefore, CPU2 is treated as the priority CPU.

The refresh circuit 3 is necessary because the shared memory 4 is constituted by a dynamic RAM, and in order to avoid competition with the CPUs 1 and 2, it is time-shared as a non-priority CPU.
The bus line 31 of the refresh circuit 3 consists only of address lines necessary for memory refresh.

The bus line 11 of CPU1 and the bus line 21 of CPU2 are
Both are composed of address lines, data lines, control lines (lines for controlling memory write and memory read), etc. necessary for memory access. An access wait line (not shown) sent from the time division control unit 5 is further added to the bus line 11 of the CPU 1, which is a non-priority CPU.

The access wait line becomes "1" when an access request is made to the shared memory 4 from the CPU 1, and becomes "0" when an access from the CPU 1 is executed in the state of the CPU 1. While this is "1", the CPU 1 is kept waiting while issuing an access request. Therefore, from the CPU 1, it appears that the shared memory 4 is being accessed during that time, and the shared memory 4 is recognized as a storage device with a slow access time. Note that in the conventional time-sharing memory sharing method, all CPUs accessing the shared memory
However, each of them required control using the access weight line.

The time division control unit 5 connects the bus line 21 of the CPU 2 to the CPU
1 bus line 11, refresh circuit 3 bus line 3
1, each bus line is connected to the shared memory bus line 41 in units of one state.

FIG. 6 shows a block diagram of the time division control section 5 in FIG. 5, and FIG. 7 is a time chart of FIG. In FIG. 6, the time division control section includes a synchronization control circuit 50, a time division state generation section 58, and a wait control section 60. The synchronous control circuit 50 includes
A basic operating clock 51 that determines the basic operating time of CPU2, which is the priority CPU, is input. The time division operation suppression circuit 52 is for suppressing the operation of the synchronous control circuit 50 until the basic operation clock 51 becomes stable when the power is turned on. After stabilization, the suppression is released at a change point of the basic operation clock 51. As a result, a frequency divider circuit consisting of two stages of flip-flops FF1 and FF2 and a NAND gate 501 starts operating, and this frequency divider circuit, which divides the frequency of the output 53 of the oscillator 59 by 1/4, synchronizes with the basic operation clock 51. As a result, a memory access signal 54 and a state switching signal 55 whose phases are shifted by 90 degrees from each other are output. While the memory access signal 54 is “1”, the shared memory 4
Writing and reading operations to and from the shared memory 4 are performed using a control signal from the CPU applied to the control line and the main memory access signal 54.

The weight control section 60 is a flip-flop FF6.
and an AND gate 504, which is a non-priority
If an access request is made from a CPU, that CPU
Control is performed such that access waits until the state of . That is, when the access request signal 110 is generated from the CPU 1 to the shared memory 4, the flip-flop F.F6 is set via the inverter 505, and the access wait line 111 of the CPU 1 becomes "1". , wait for the access wait line to become "0" while sending a signal to the control line.
When the memory access signal 54 becomes “1” in the CPU1 state, the AND gate 504 turns on and
At the end of access, reset flip-flop F.F6. At this time, the access wait line 111 becomes "0".

The time-division state generator 58 is a flip-flop
It is composed of F.Fs 3 to 5 and AND gates 12, 22, and 32, and its operation is controlled by a signal from a synchronous control circuit 50. That is, in the time division state generation section 58, the state switching signal 55 is
This occurs at intervals of the basic operation time of the flip-flop FF in synchronization with the basic operation clock 51.
3 to 5 are set sequentially. Flip Flop F.
Each output of F3-5 is AND gate 1
This is one of the inputs of 2, 22, and 32. Signals from the bus line 11 of the CPU 1, the bus line 21 of the CPU 2, and the refresh bus line 31 become the other inputs of the AND gates 12, 22, and 32, respectively. The outputs of the AND gates 12, 22, and 32 are input to the shared memory via the shared memory bus line 41. accordingly
Time-sharing states occur repeatedly in the order of CPU2 state, CPU1 state, and refresh state.

When the memory access in the current state is completed, the memory access signal 54 and the state switching signal 55 are "0", and the NAND gate 502 outputs a signal. In this state, shared memory access request signal 5 is sent from CPU2.
6 is output, a state forced switching signal 57 is output from the AND gate 503 when the oscillator output 53 is "1". This forced state switching signal 57 resets the flip-flops F3 to F5 of the time-division state generating section 58, and temporarily puts them into the refresh state. (During this refresh state, the memory access signal 54 remains "0", so no actual refresh operation is performed.) As a result, the next state is automatically set to CPU2.
state, and data can be exchanged with the shared memory without making CPU2 wait.
Therefore, CPU2 uses shared memory as dedicated memory,
You will be able to access it freely without having to worry about waiting time.

As described above, according to this embodiment, the line control
By setting CPU2 as the priority CPU, it is possible to eliminate the waiting time peculiar to time-division control and to perform real-time processing of the line by using the shared memory as a dedicated memory.

According to the present invention, by making a processing device that operates in real time or a processing device that frequently exchanges data with the shared memory a priority processing device, data can be exchanged with the shared memory within its own access time without waiting time. It can be done with Therefore, there is an effect that a device or system with high processing capacity can be realized.

[Brief explanation of drawings]

Fig. 1 is a configuration diagram of a time-sharing memory sharing method according to the prior art, Fig. 2 is an explanatory diagram of the operation of the conventional method, and Fig. 3 is a diagram illustrating the operation of the conventional method.
4 is a diagram explaining the operation of the present invention, FIG. 5 is a block diagram of an embodiment of the present invention, and FIG. 6 is the time-sharing control in FIG. 5. 7 is a time chart of FIG. 6. 1, 2, 91-94...processing unit (CPU), 3
...Refresh circuit, 4...Shared memory, 5...
...Time division control unit, 6... Line control unit, 7... Dedicated memory, 8... Disk device, 11, 21, 31
...Bus line, 12, 22, 32, 503, 504
...and gate, 41...shared memory bus line,
50...Synchronization control circuit, 52...Time division operation suppression circuit, 58...Time division state generation unit, 59...
Oscillator, 60... Weight control section, 501, 50
2...Nand Gate, 505..., FF1~6...
…flipflop.

Claims (1)

[Claims] 1. In a memory sharing method in which a control circuit is provided between a plurality of processing devices and a memory common to these processing devices, and the memory is accessed by a group of processing devices in a time-sharing manner, the control circuit a first memory access signal for the memory based on a periodic signal applied from the device;
and a second circuit that creates a signal that allocates a periodic time period in which the memory can be accessed to each processing device in a time-sharing manner based on a periodic signal given from the specific processing device. , the second
A memory characterized in that, when a memory access request signal from the specific processing device is given, the circuit leaves only the allocation signal corresponding to the specific processing device and blocks the allocation signal corresponding to other processing devices. Sharing method.