JPH0324268A - Formation of thin film - Google Patents
Formation of thin filmInfo
- Publication number
- JPH0324268A JPH0324268A JP16009289A JP16009289A JPH0324268A JP H0324268 A JPH0324268 A JP H0324268A JP 16009289 A JP16009289 A JP 16009289A JP 16009289 A JP16009289 A JP 16009289A JP H0324268 A JPH0324268 A JP H0324268A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gas
- insulating film
- gaseous
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015572 biosynthetic process Effects 0.000 title description 3
- 239000010409 thin film Substances 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims abstract description 22
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910000077 silane Inorganic materials 0.000 claims abstract description 17
- 239000012495 reaction gas Substances 0.000 claims abstract description 8
- 239000007789 gas Substances 0.000 claims description 52
- 238000000034 method Methods 0.000 claims description 24
- 229910004205 SiNX Inorganic materials 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 13
- 229910052710 silicon Inorganic materials 0.000 abstract description 13
- 239000010703 silicon Substances 0.000 abstract description 13
- 230000007547 defect Effects 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 8
- 229910052681 coesite Inorganic materials 0.000 abstract 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract 4
- 239000000377 silicon dioxide Substances 0.000 abstract 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract 4
- 229910052682 stishovite Inorganic materials 0.000 abstract 4
- 229910052905 tridymite Inorganic materials 0.000 abstract 4
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 102100021821 Enoyl-CoA delta isomerase 1, mitochondrial Human genes 0.000 description 1
- 101000896030 Homo sapiens Enoyl-CoA delta isomerase 1, mitochondrial Proteins 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229960001730 nitrous oxide Drugs 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 238000003756 stirring Methods 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
- Chemical Vapour Deposition (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
［産業］二の利用分野］
本発明は、絶縁膜の形成方法に関し、更に詳しくは、バ
イアスＥＣＩ１プラズマＣＶＤ法を用いて低ストレス化
された絶縁膜の形戊方法に係るものである。[Detailed Description of the Invention] [Industry] Second Field of Application] The present invention relates to a method of forming an insulating film, and more specifically, to a method of forming an insulating film with low stress using bias ECI1 plasma CVD method. This is related.
［発明の概要］
第１の発明は、段差を有する基体上にバイアスＥＣＲプ
ラズマＣＶＤ法に上り絶縁膜を形成する方法において、
はじめに、シラン系ガスとＮ．０ガスを用いてＣＶＤを
行ない、次いで、シラン系ガスとＯ，ガスを用いてＣＶ
Ｄを行なうことにより、又、第２の発明は、反応ガスに
シラン系ガスを用い、該シラン系ガスの流量比を小さく
しながらＣＶＤを行なうことにより、
共に、低ストレスな絶縁膜を段差部に埋め込めるように
したしのである。[Summary of the Invention] The first invention is a method for forming an insulating film on a substrate having a step using a bias ECR plasma CVD method,
First, silane gas and N. CVD is performed using 0 gas, and then CVD is performed using silane gas and O gas.
By performing step D, and in the second invention, by using a silane gas as a reaction gas and performing CVD while reducing the flow rate ratio of the silane gas, both can form a low stress insulating film on the stepped portion. I made it possible to embed it in.
第３の発明は、段差を有する基体上にバイアスＥＣＲプ
ラズマＣＶＤ法により絶縁膜を形成する方法において、
はじめに、ＳｉＯｚ膜を形成し、次いで、ＳｉＮｘ膜を
形成することにより、段差部への密着性の高い絶縁膜を
形成することを可能にするようにしたしのであり、例え
ばトレンチアイソレーションにおけるトレンチ内壁への
密着性を改善し、リーク電流の低減を図ることが可能と
なる。A third invention is a method for forming an insulating film on a substrate having a step by bias ECR plasma CVD,
By first forming a SiOz film and then forming a SiNx film, we have made it possible to form an insulating film with high adhesion to the stepped portion, for example on the inner wall of a trench in trench isolation. It is possible to improve adhesion to the surface and reduce leakage current.
［従来の技術］
バイアスＥＣＲプラズマＣＶＤ法は、デバイスの高集積
化が今後、増々進む中で、層間膜の平坦化の要求に応え
得る重要な技術となりつつある。[Prior Art] The bias ECR plasma CVD method is becoming an important technology that can meet the demand for planarization of interlayer films as devices become increasingly highly integrated.
即ち、バイアスＥＣＲプラズマＣＶＤ法は、低圧で高密
度プラズマを形戚できるため、アスベクト比の高い溝，
段差へも高速で膜成長可能なうえ、ウエハにＲＦバイア
スを印加することにより余分な膜をエッヂング除去する
ことが出来、同一装置内で平坦化絶縁膜を形成出来る利
点かある。しかも、このＣＶＤ法は、低温プラズマを用
いるため、低愚戊長が可能である。In other words, the bias ECR plasma CVD method can form high-density plasma at low pressure, so it can form grooves with high aspect ratios.
This method has the advantage that it is possible to grow a film at high speed even on steps, and that excess film can be removed by etching by applying an RF bias to the wafer, and that a flattened insulating film can be formed in the same device. Furthermore, since this CVD method uses low-temperature plasma, it is possible to achieve a low length.
この種のバイアスＥＣＲプラズマＣＶＤ法としては、特
開昭６３−８０５３８号公報記載のものが知られている
。この技術は、シラン（ＳｉＨ．）ガスと酸素（０，）
ガスを反応ガスとして用い、ＳｉＯｚ膜をエッチングし
て平坦化しながら堆積さＵ・るようにし、また、基板に
バイアス電圧を印加し、アルゴン（Ａｒ）よりも質量の
重い不活性ガスを用いることにより、横方向のエソチン
グ速度を大きくし、平坦化処理時間を短縮ずろようにし
たちのである。As this type of bias ECR plasma CVD method, the one described in Japanese Patent Application Laid-open No. 80538/1983 is known. This technology uses silane (SiH.) gas and oxygen (0,)
By using gas as a reactive gas, the SiOz film is etched and deposited while planarizing it, and by applying a bias voltage to the substrate and using an inert gas with a mass heavier than argon (Ar). The aim was to increase the etching speed in the lateral direction and shorten the planarization process time.
斯るバイアスＥＣＲプラズマＣＶＤｉの特徴を生かして
、例えば素子間分離領域にトレインチを形成し、そのト
レインチ内にバイアスＥＣＵＬプラズマＣＶＤ法でＳｉ
ｎｓなどの絶縁膜を埋め込もうという研究開発が近年行
なわれている。Taking advantage of the characteristics of bias ECR plasma CVDi, for example, a train trench is formed in the isolation region between elements, and Si is deposited in the train trench by bias ECUL plasma CVD.
In recent years, research and development has been carried out to embed an insulating film such as NS.
［発明が解決しようとする課題］
しかしながら、このような従来の絶縁膜の形成方法にあ
っては、バイアスＥＣＲプラズマＣＶＤの反応ガスとし
てＳｉｔ｛．と０，を用いるが、堆積した絶縁膜のスト
レスが比較的大きいため、トレインチ浬込み後に、デバ
イス形ｆ戊過程で加わる熱処理等により、基体結晶に欠
陥を誘起したり、塊込み膜にクラックが生じ易いという
問題点があった。[Problems to be Solved by the Invention] However, in such a conventional method for forming an insulating film, Sit{. and 0, are used, but since the stress of the deposited insulating film is relatively large, the heat treatment applied during the device forming process after the train trench is drilled may induce defects in the base crystal or cracks in the agglomerated film. There was a problem that it was easy to occur.
本発明は、このよう紅従来の問題点に着目して創案され
たものであって、段差に埋め込む絶縁膜の低ストレス化
を期し得るようにしたちのである。The present invention has been devised by focusing on the problems of the conventional method, and is intended to reduce the stress of the insulating film buried in the step.
Ｆ課゛題を解決するための手段］
そこで、第１の発明は、段差を有する基体上にバイアス
ＥＣＲプラズマＣＶＤ法により絶縁模を形成する方法に
おいて、はじめに、シラン系ガスとＮ ｔ Ｏガスを用
いてＣＶＤを行ない、次いで、シラン系ガスとＯ！ガス
を用いてＣＶＤを行なうことを、その・解決手段として
いる。Means for Solving Problem F] Therefore, the first invention is a method for forming an insulating pattern on a substrate having a step by bias ECR plasma CVD, in which silane-based gas and N t O gas are first mixed. CVD is then carried out using silane gas and O! The solution is to perform CVD using gas.
第２の発明は、段差を有する基体上にバイアスＥ Ｃ
ＲプラズマＣＶＤ法により絶縁膜を形成ずろ方法におい
て、反応ガスにプラン系ガスを用い、該シラン系ガスの
流量比を小さくしながらＣＶＤを行なうことを、その解
決手段としていろ。The second invention is a bias E C on a substrate having a step.
A solution to this problem is to use a plan-based gas as a reaction gas and perform CVD while reducing the flow rate ratio of the silane-based gas in a method for forming an insulating film by R plasma CVD.
第３の発明は、段差を有する基体上にバイアスＥＣ Ｒ
プラズマＣＶＤ法により絶縁膜を形成する方法において
、はじめに、Ｓｉｎ２膜を形成し、次いで、ＳｉＮｘ膜
を形成することを、その解決手段としている。The third invention is a bias ECR on a substrate having a step.
In a method of forming an insulating film by plasma CVD, the solution is to first form a Sin2 film and then to form a SiNx film.
［作用］
第１の発明においては、はじめに、基体上にＳｔ１−１
．ガスとＮ ｔ Ｏガスを用いてＳｉｎ２膜を形成す
ることにより、段差表面をおよそＩＸＩ０９ｄｙｎ ｅ
／ ｃ ｍ″以下の低ストレスな膜で保護するため、
後工程でＳ ｉ １−■．ガスと０，ガスを用いた通常
のバイアスＥＣＲプラズマＣＶＤを行なってもＳＩＯｔ
膜全体としては基体側へ応力を与えることが抑制される
。[Operation] In the first invention, first, St1-1 is applied on the substrate.
．． By forming a Sin2 film using gas and N t O gas, the step surface is approximately IXI09dyn e
/cm″ or less for protection with a low-stress film,
In the post-process, S i 1-■. Even if normal bias ECR plasma CVD using gas and 0 gas is performed, SIOt
As a whole, stress is suppressed from being applied to the substrate side.
第２の発明においては、シラン系ガスの流量比を小さく
しながらＣＶＤを行なうため、段差に付着するＳｉｆｔ
膜は、低ストレスなしのが頭初形成される。このため、
ＳｉＯｚ膜が基体側へ応力を与えるのを防止できる。In the second invention, since CVD is performed while reducing the flow rate ratio of the silane gas, Sift adhering to the step
The membrane is initially formed under low stress. For this reason,
It is possible to prevent the SiOz film from applying stress to the substrate side.
第３の発明においては、ＳｉＯｙ膜を形成した後、ノリ
コン窒化膜（ＳｉＮス）を形成することにより、Ｓｉｎ
ｓ膜の圧縮応力を、ＳｉＮｘ膜の引張り応力で緩和し、
基体側へ応力を及ぼずのを防止する。このため、例えば
トレンチ部でのリーク電流を低減し、高アスペクト比の
トレンチ埋達みを可能にする。In the third invention, after forming the SiOy film, a silicon nitride film (SiN film) is formed to
The compressive stress of the S film is relaxed by the tensile stress of the SiNx film,
Prevents stress from being applied to the base body side. Therefore, for example, leakage current in the trench portion can be reduced, making it possible to fill a trench with a high aspect ratio.
［実施例］
以下、本発明に係る絶縁膜の形成方法の詳細を図面に示
す実施例に基づいて説明する。[Example] Hereinafter, details of the method for forming an insulating film according to the present invention will be described based on an example shown in the drawings.
（第１実施例）
第ｌ図Ａ〜第ｌ図Ｃは、本発明の第１実施例の工程を示
す断面図である。(First Embodiment) FIGS. 1A to 1C are sectional views showing the steps of the first embodiment of the present invention.
先ず、第１図Ａに示すように、基体としてのンリコン基
板ｌの表面に、リソグラフィー技術及びドライエッチン
グ技術を用いて、段差としてのトレンチｌａを形成した
後、該トレンチｌａ内壁面及びシリコン基板１表面に熱
酸化を行ない、酸化膜２を１００〜２００人程度の厚さ
に形成する。First, as shown in FIG. 1A, a trench la is formed as a step on the surface of a silicon substrate l as a base using lithography and dry etching techniques, and then the inner wall surface of the trench la and the silicon substrate 1 are formed. The surface is thermally oxidized to form an oxide film 2 to a thickness of about 100 to 200 layers.
次に、第１図Ｂに示すように、シラン（ Ｓ ｉＨ ４
）ガスと酸化二窒素（Ｎ１０）ガスを反応ガスとして用
いて、バイアスＥＣＲプラズマＣＶＤ法を行ない絶縁膜
としての第ｌ次Ｓｉｎ，膜３を約５００〜３０００人の
膜厚に形成する。このバイアスＥＣＲプラズマＣＶＤ法
の条件としては、ＳｉＨ＋ガスの流量を２０ＳＣＣＭ．
ＮｔＯガスの流量４０８ＣＣＭ，圧力を５Ｘ Ｉ Ｏ−
’Ｔｏ ｒ ｒ，マイクロ波電力を８００Ｗ，ＲＦバイ
アスを３００Ｗに設定した。Next, as shown in FIG. 1B, silane (S iH 4
) gas and dinitrogen oxide (N10) gas as reaction gases, a bias ECR plasma CVD method is performed to form the first-order Sin film 3 as an insulating film to a thickness of approximately 500 to 3000 nm. The conditions for this bias ECR plasma CVD method include a flow rate of SiH+ gas of 20 SCCM.
NtO gas flow rate 408CCM, pressure 5X IO-
'Torr, microwave power was set to 800W, and RF bias was set to 300W.
次いで、第Ｉ図Ｃに示すように、反応ガスをＳｉＨ４ガ
スと酸素（Ｏ，）ガスとアルゴン（Ａｒ）ガスに代えて
バイアスＥＣｒ｛プラズマＣＶＤを行ない、第２次Ｓｉ
Ｏｔｔ［ｉ４を埋め込み平坦化を行なう。なお、このバ
イアスＥＣＲプラズマＣＶＤの条件は、ＳｉＨ４ガスの
流量を２０ＳＣＣＭ．０，ガスの流量を４０ＳＣＣＭ，
アルゴンガスの流量をＩＯｓｃｃＭとし、圧力を５Ｘ１
０−３Ｔｏｒｒ、マイクロ波電力を８００Ｗ，ＲＦバイ
アスを３００に設定した。Next, as shown in FIG.
Embed Ott[i4 and perform planarization. Note that the conditions for this bias ECR plasma CVD are that the flow rate of SiH4 gas is 20SCCM. 0, gas flow rate 40SCCM,
The flow rate of argon gas is IOsccM, and the pressure is 5X1.
The settings were 0-3 Torr, microwave power 800 W, and RF bias 300.
上記Ｌ タ第１ 次Ｓ ｉ Ｏ ｔ 膜３ ハ、約ＩＸ
ｌＯ’ｄｙ ｎ ｅ ／ ｃ ｍ ’以下の低ストレス
化を期し得るものであり、第２次Ｓｉｎ，膜４の応力が
約２×１０”ｄ ｙ ｎ ｅ／ｃｍ’と比較的高ストレ
スであっても第ｌ次ＳｉＯｚ膜３からシリコン基板ｉ側
へ応力を及ぼずことを防止出来る。The above L ta primary S i O t film 3 c, about IX
It is possible to expect a low stress of less than lO'dyne/cm', and the stress of the secondary Sin film 4 is relatively high at about 2×10"dyne/cm'. However, stress can be prevented from being applied from the lth-order SiOz film 3 to the silicon substrate i side.
このようにして形威されたトレンチＩのＳｉｎｓ膜（第
１次Ｓｉｎｔ膜３及び第２次Ｓｉｎ，膜４）は全体とし
て低ストレス化が図れるため、デバイス形成過程で行な
われる熱処理を経ても、シリコン基板ｌの結晶に欠陥を
生じたり、９４０，膜にクラックが生じたりすることが
ない。Since the Sins film (first Sint film 3 and second Sin film 4) in the trench I formed in this way can have low stress as a whole, even after the heat treatment performed in the device formation process, Defects do not occur in the crystals of the silicon substrate 1, and cracks do not occur in the film.
（第２実施例）
第２図Ａ〜第２図Ｃは、本発明に係る絶縁膜の形成方法
の第２実施例の工程を示す断面図である。(Second Example) FIGS. 2A to 2C are cross-sectional views showing steps of a second example of the method for forming an insulating film according to the present invention.
先ず、第２図Ａに示すように、シリコン基板ｌの表面に
、リソグラフィー技術及びドライエッチング技術を用い
て、トレンチｌａを形戊した後、熱酸化を行なって該ト
レンチ１ａ内壁面及びシリコン基板１表面に酸化膜２を
１００〜２００人程度の厚さに形成する。First, as shown in FIG. 2A, a trench la is formed on the surface of a silicon substrate l using lithography and dry etching techniques, and then thermal oxidation is performed to form the inner wall surface of the trench la and the silicon substrate 1. An oxide film 2 is formed on the surface to a thickness of about 100 to 200 layers.
次に、第２図Ｂに示すように、反応ガスとしてシラン（
ＳｉＨ＊）ガスと酸素（０１）ガスを用いて、バイアス
ＥＣＲプラズマＣＶＤを行ないトレンチｌａ内及びンリ
コン基板ｌ上にＳｉｎ２膜５を形成する。このＣＶＤの
条件としては、ＳｉＨ４ガスの流攪を２０ＳＣＣＭ，Ｏ
，ガスを２０８ＣＣＭ，圧力を５ｘ １ ０−３Ｔｏ
ｒ ｒｓ ？イク口波電力を８００Ｗ％ＲＦバイアスを
３００Ｗに設定した。この条件でＳｉｆｔ膜５を５００
〜３０００人程度の厚さに形成した後、圧力，マイクロ
波電力及びＲＦバイアスを同一条件に保ったまま、Ｓｉ
Ｈ４の流量比を小さくして、さらに、ＳｉＯｙ膜５の堆
積、平坦化をバイアスＥＣＲプラズマＣ■Ｄによって行
う（第２図Ｃ）。この場合、Ｓ ｔ Ｈ４ガスを２０Ｓ
ＣＣＭ．ｏｔガスの流量を４０３ＣＣＭ．アルゴンガス
をＩＯｓｃｃＭのｄ量とした。Next, as shown in Figure 2B, silane (
Bias ECR plasma CVD is performed using SiH*) gas and oxygen (01) gas to form a Sin2 film 5 in the trench la and on the silicon substrate l. The conditions for this CVD include flow stirring of SiH4 gas at 20 SCCM, O
, gas 208CCM, pressure 5x 1 0-3To
rrs? The output wave power was set to 800W%, and the RF bias was set to 300W. Under these conditions, the Sift film 5 was
After forming the film to a thickness of about 3,000 yen, the Si
The flow ratio of H4 is reduced, and the SiOy film 5 is further deposited and planarized using bias ECR plasma C-D (FIG. 2C). In this case, S t H4 gas was
CCM. The flow rate of ot gas was set to 403CCM. The amount of argon gas was d of IOsccM.
上記したように、Ｓ ＩＨ ４ガスの流量比を段階的に
小さくしたが、連続的にＳｉ８４ガスの流量比を小さく
するようにしてもよい。即ち、トレンチＩａ内壁を覆う
Ｓｉｎ，膜形成時のＳｉＨ＋の流量比が大きければ（Ｓ
ＩＨ４ガスとＯ，ガスとの流量比がｌ：１程度）、充分
に低ストレス化を図ることが可能である。As described above, the flow rate ratio of the S IH 4 gas is decreased in stages, but the flow rate ratio of the Si 84 gas may be decreased continuously. That is, if the flow rate ratio of Sin covering the inner wall of trench Ia and SiH+ during film formation is large, (S
If the flow rate ratio of IH4 gas and O gas is about 1:1), it is possible to achieve sufficiently low stress.
なお、本実施例においては、アルゴンガスを加えたが、
他の不活性ガスを加えてもよい。Although argon gas was added in this example,
Other inert gases may also be added.
（第３実施例）
第３図Ａ〜第３図Ｃは、本発明の第３実施例の工程を示
す断面図である。(Third Embodiment) FIGS. 3A to 3C are cross-sectional views showing the steps of a third embodiment of the present invention.
先ず、第３図Ａに示すように、シリコン基板１のトレン
ヂ１ａの内壁及びシリコン基板１表面を熱酸化により酸
化膜２を形成する。First, as shown in FIG. 3A, an oxide film 2 is formed on the inner wall of the trench 1a of the silicon substrate 1 and the surface of the silicon substrate 1 by thermal oxidation.
次いで、第３図Ｂに示すように、反応ガスとしてＳｉｌ
４＋ガスと，Ｏガスを用いてバイアスＥＣＲプラズマＣ
ＶＤを行ないｓｉｏ，＠ｓを５００〜３０００人程度の
膜厚で形成する。このＳｉｆｔ膜５は、圧縮応力を有す
る。このＣＶＤの条件は、ガス流量をＳ ｉ Ｈ ４／
Ｏ ｔ＝ ２ ０ ／ ４ ０ ３ Ｃ Ｃ Ｍ圧力
を５ＸＩＯ−３Ｔｏｒｒ１マイクロ波電力を８００ＷＳ
ｒｌＦバイアスを３００Ｗに設定した。Next, as shown in FIG. 3B, Sil is used as the reaction gas.
Bias ECR plasma C using 4+ gas and O gas
VD is performed to form sio and @s to a film thickness of about 500 to 3000 layers. This Sift film 5 has compressive stress. The conditions for this CVD are that the gas flow rate is S i H 4/
O t = 2 0 / 4 0 3 C CM pressure 5XIO-3Torr1 microwave power 800WS
The rlF bias was set to 300W.
次に、第３図Ｃに示すように、バイアスＥＣＲプラズマ
ＣＶＤＩにより、窒化ンリコン（ＳｉＮｘ）膜６を平坦
化、形成する。むお、このＣＶＤの条件は、反応ガスの
流潰をＳ ｉＨ −／ Ｎ ｔ ＝ ２ ０ ／ ６０
９ＣＣＭ，圧力を５ＸＩＯ−’Ｔｏｒｒ， マイクロ波
電力を８００Ｗ，ＲＦバイアスを３００Ｗに設定した。Next, as shown in FIG. 3C, a silicon nitride (SiNx) film 6 is planarized and formed by bias ECR plasma CVDI. Well, this CVD condition is such that the reaction gas collapses as SiH −/N t = 2 0 / 60
The pressure was set to 9CCM, the pressure was set to 5XIO-'Torr, the microwave power was set to 800W, and the RF bias was set to 300W.
なお、この窒化シリコン膜６は、引張り応力を有し、上
記Ｓｉｄｅ膜の圧縮応力を緩和する。Note that this silicon nitride film 6 has tensile stress and relieves the compressive stress of the Side film.
本実施例では、ＳｉＯ！膜５とＳ ｉ Ｎ ｘｌｌｌｉ
６の２層としたが、トレンチＩａの内壁に密着する層
かＳｊＯ．膜であれば、窒化シリコン膜との多層構造と
してもよい。また、Ｓｔｏｗ膜５とＳｉＮＸ膜６の成膜
工程を、反応ガスを除々に代えることにより連続的に形
成してもよい。この場合、例えば、ＳＬＨａガスの流量
を２０８ＣＣＭに保ち、Ｏｄｆスを４０ＳＣＣＭからＱ
ＳＣＣＭに変化させ、同時にＮ，ガスをＯから６０ＳＣ
ＣＭに変化させることにより、連続的なバイアスＥＣＲ
プラズマＣＶＤが可能となる。このように連続的に絶縁
膜を形成した場合、２層のものに比べてＳｉＯｚ膜とＳ
ｉＮｘ膜の密着性が改善される。In this example, SiO! Membrane 5 and S i N xlli
6, but the layer that is in close contact with the inner wall of the trench Ia or the SjO. If it is a film, it may have a multilayer structure with a silicon nitride film. Furthermore, the Stow film 5 and the SiNX film 6 may be formed continuously by gradually changing the reaction gas. In this case, for example, the flow rate of SLHa gas is kept at 208CCM, and the Odf gas is changed from 40SCCM to Q
Change to SCCM and at the same time change N and gas from O to 60SC
Continuous bias ECR by changing to CM
Plasma CVD becomes possible. When an insulating film is formed continuously in this way, the SiOz film and S
The adhesion of the iNx film is improved.
また、シリコン基仮ｌの温度等を制御することにより、
さらに、膜質を向七することが可能である。In addition, by controlling the temperature etc. of the silicon base material,
Furthermore, it is possible to change the film quality.
本実施例によれば、ＳｉＯｙ膜のみでトレンヂ埋込みを
行なうよりら、リーク電流等を低減化し、トレンヂ分離
能の良好なアイソレーションを高アスペクト比のトレン
ヂにおいてら実現することが可能となる。According to this embodiment, it is possible to reduce leakage current and the like and realize isolation with good trend separation ability even in a trend with a high aspect ratio, compared to trench burying using only the SiOy film.
理を施しても基体結晶に欠陥が生じることがなく、例え
ばリーク電流等を低減した良好な特性を有する効果があ
る。Even when subjected to treatment, defects do not occur in the base crystal, and for example, it has the effect of having good characteristics such as reduced leakage current.
第ｌ図Ａ〜第１図Ｃは本発明に係る絶縁膜の形成方法の
第１実施例の工程を示す断面図、第２図Ａ〜第２図Ｃは
同第２実施例の工程を示す断面図、第３図Ａ〜第３図Ｃ
は同第３実施例の工程を示す断面図である。
■・・・ンリコン基板、ｌａ・・・トレンチ、２・・酸
化膜、３・・第１次Ｓｉｎ，膜、４・・第２次Ｓｔｏｗ
膜、５・・・Ｓ ｉ Ｏ ｖ膜、６・・ＳｉＮｘ膜。
［発明の効果］
以上の説明から明らかなように、本発明に係る絶縁膜の
形戚方法によれば、段差部、特にトレンチに埋め込まれ
た絶縁膜の一低ストレス化を図ることか可能となり、デ
バイス形威過程において熱処／ｋｌ．ｉ”，
第１
図Ｇ
青５２突 ス１と イダリ σ９ 工 １１【 左 示
す 断ｄｈ 巨虱第２図Ａ
第２図Ｂ
第２図Ｃ1A to 1C are cross-sectional views showing the steps of the first embodiment of the insulating film forming method according to the present invention, and FIGS. 2A to 2C are sectional views showing the steps of the second embodiment. Cross-sectional views, Figures 3A to 3C
FIG. 3 is a cross-sectional view showing the steps of the third embodiment. ■... Silicon substrate, la... trench, 2... oxide film, 3... primary Sin, film, 4... secondary Stow
film, 5...SiOv film, 6...SiNx film. [Effects of the Invention] As is clear from the above explanation, according to the insulating film forming method according to the present invention, it is possible to reduce the stress of the insulating film embedded in the stepped portion, particularly in the trench. , heat treatment/kl. in the device shaping process. i”, Fig. 1 G Blue 52 Tsutsu 1 and Idari σ9 Eng 11
Claims (3)
ＣＶＤ法により絶縁膜を形成する方法において、 はじめに、シラン系ガスとＮ＿２Ｏガスを用いてＣＶＤ
を行ない、次いで、シラン系ガスとＯ＿２ガスを用いて
ＣＶＤを行なうことを特徴とする絶縁膜の形成方法。(1) In the method of forming an insulating film on a substrate with steps by bias ECR plasma CVD method, first, CVD is performed using silane gas and N_2O gas.
1. A method for forming an insulating film, which comprises performing CVD using a silane-based gas and an O_2 gas.
ＣＶＤ法により絶縁膜を形成する方法において、 反応ガスにシラン系ガスを用い、該シラン系ガスの流量
比を小さくしながらＣＶＤを行なうことを特徴とする絶
縁膜の形成方法。(2) A method for forming an insulating film on a substrate having steps by bias ECR plasma CVD, characterized in that a silane-based gas is used as a reaction gas, and CVD is performed while reducing the flow rate ratio of the silane-based gas. A method for forming an insulating film.
ＣＶＤ法により絶縁膜を形成する方法において、 はじめに、ＳｉＯ＿２膜を形成し、次いで、ＳｉＮｘ膜
を形成することを特徴とする絶縁膜の形成方法。(3) A method for forming an insulating film on a substrate having steps by bias ECR plasma CVD, the method comprising: first forming an SiO_2 film, and then forming an SiNx film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1160092A JP2976442B2 (en) | 1989-06-22 | 1989-06-22 | Method of forming insulating film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1160092A JP2976442B2 (en) | 1989-06-22 | 1989-06-22 | Method of forming insulating film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0324268A true JPH0324268A (en) | 1991-02-01 |
| JP2976442B2 JP2976442B2 (en) | 1999-11-10 |
Family
ID=15707688
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1160092A Expired - Fee Related JP2976442B2 (en) | 1989-06-22 | 1989-06-22 | Method of forming insulating film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2976442B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0539804A2 (en) * | 1991-10-15 | 1993-05-05 | Canon Kabushiki Kaisha | A substrate for a liquid jet recording head, a manufacturing method for such a substrate, a liquid jet recording head, and a liquid jet recording apparatus |
| JP2013514661A (en) * | 2009-12-16 | 2013-04-25 | ナショナル セミコンダクター コーポレーション | Stress compensation for large area gallium nitride or other nitride-based structures on semiconductor substrates |
| JP2020035931A (en) * | 2018-08-30 | 2020-03-05 | 富士電機株式会社 | Gallium nitride based semiconductor device and method of manufacturing gallium nitride based semiconductor device |
-
1989
- 1989-06-22 JP JP1160092A patent/JP2976442B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0539804A2 (en) * | 1991-10-15 | 1993-05-05 | Canon Kabushiki Kaisha | A substrate for a liquid jet recording head, a manufacturing method for such a substrate, a liquid jet recording head, and a liquid jet recording apparatus |
| US6149986A (en) * | 1991-10-15 | 2000-11-21 | Canon Kabushiki Kaisha | Methods for manufacturing a substrate for a liquid jet recording head, liquid jet recording head, and liquid jet recording apparatus |
| JP2013514661A (en) * | 2009-12-16 | 2013-04-25 | ナショナル セミコンダクター コーポレーション | Stress compensation for large area gallium nitride or other nitride-based structures on semiconductor substrates |
| JP2020035931A (en) * | 2018-08-30 | 2020-03-05 | 富士電機株式会社 | Gallium nitride based semiconductor device and method of manufacturing gallium nitride based semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2976442B2 (en) | 1999-11-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7402498B2 (en) | Methods of forming trench isolation regions | |
| US5726090A (en) | Gap-filling of O3 -TEOS for shallow trench isolation | |
| JP3228183B2 (en) | Insulating film, semiconductor device having the insulating film, and method of manufacturing the same | |
| US7514366B2 (en) | Methods for forming shallow trench isolation | |
| US6642141B2 (en) | In-situ silicon nitride and silicon based oxide deposition with graded interface for damascene application | |
| US20050035426A1 (en) | Isolation structure with nitrogen-containing liner and methods of manufacture | |
| US6689646B1 (en) | Plasma method for fabricating oxide thin films | |
| US6902960B2 (en) | Oxide interface and a method for fabricating oxide thin films | |
| JPH11251271A (en) | Silicon carbide for stopper layer in chemical-mechanical polishing for planarizing insulating dielectric | |
| JPH08203884A (en) | Oxynitride, deposition thereof, and deposition of isolation oxide of oxynitride | |
| KR100557943B1 (en) | Method of improving sti process characteristics by plasma process | |
| KR20060048666A (en) | Gap-filling for isolation | |
| US20040175900A1 (en) | Manufacturing method of shallow trench isolation | |
| JPH0324268A (en) | Formation of thin film | |
| US5920791A (en) | Method of manufacturing intermetal dielectrics for sub-half-micron semiconductor devices | |
| JPH07307382A (en) | Trench element isolation structure and formation thereof | |
| JP2000058641A (en) | Semiconductor device, manufacture thereof, and method for forming interlayer insulating film | |
| KR20020049807A (en) | Isolation method for a semiconductor device | |
| JP2000012674A (en) | Manufacture of semiconductor device and method for separating element | |
| JPH0376577B2 (en) | ||
| JP3315907B2 (en) | Method for manufacturing semiconductor device | |
| CN118099079A (en) | Semiconductor device and method of manufacturing the same | |
| JPH03159124A (en) | Manufacture of semiconductor device | |
| JPH10335447A (en) | Manufacture of dielectric isolation substrate | |
| JPH0215650A (en) | Semiconductor device and manufacture thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |