JPH0376577B2 - - Google Patents
Info
- Publication number
- JPH0376577B2 JPH0376577B2 JP22652782A JP22652782A JPH0376577B2 JP H0376577 B2 JPH0376577 B2 JP H0376577B2 JP 22652782 A JP22652782 A JP 22652782A JP 22652782 A JP22652782 A JP 22652782A JP H0376577 B2 JPH0376577 B2 JP H0376577B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- silicon
- etching
- group
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 30
- 239000010703 silicon Substances 0.000 claims description 30
- 229910052710 silicon Inorganic materials 0.000 claims description 30
- 239000010409 thin film Substances 0.000 claims description 22
- 239000010408 film Substances 0.000 claims description 18
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 13
- 238000001312 dry etching Methods 0.000 claims description 5
- 150000001875 compounds Chemical class 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- 239000000470 constituent Substances 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 description 18
- 239000000758 substrate Substances 0.000 description 12
- 238000006243 chemical reaction Methods 0.000 description 11
- 239000007789 gas Substances 0.000 description 9
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229910052594 sapphire Inorganic materials 0.000 description 4
- 239000010980 sapphire Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 150000004678 hydrides Chemical class 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 229910004014 SiF4 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
- H01L29/78657—SOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Drying Of Semiconductors (AREA)
Description
【発明の詳細な説明】
本発明は薄膜MISトランジスタ形成法に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of forming a thin film MIS transistor.
従来、薄膜MISトランジスタは絶縁基板上に形
成された半導体薄膜を用いて作られるものであ
り、サフアイヤ単結晶基板上にシリコン単結晶薄
膜を形成したシリコン・オン・サフアイヤ（以下
SOSと略す）を用いたものが多く作られている。 Conventionally, thin-film MIS transistors have been made using a semiconductor thin film formed on an insulating substrate.
Many products are made using the SOS (abbreviated as SOS).
SOSを用いたMISトランジスタにおいて従来の
素子分離法の一つにサフアイヤ基板上にシリコン
薄膜のアイランドを形成する方法がある。第１図
１，２，３，４はこの方法を説明するための図
で、主要工程における概略断面を順次示した図で
ある。尚、図中の１のサフアイヤ基板、２はシリ
コン膜、３はシリコン酸化膜、５はシリコン中に
拡散した族元素に対応する。まずシリコン膜２
上にシリコン酸化膜３を形成しレジストをマスク
としてシリコン酸化膜３のパターンニングを行う
（第１図１）。 One of the conventional element isolation methods for MIS transistors using SOS is to form islands of silicon thin films on sapphire substrates. FIGS. 1, 2, 3, and 4 are diagrams for explaining this method, and are diagrams sequentially showing schematic cross sections in main steps. In the figure, 1 corresponds to the sapphire substrate, 2 to the silicon film, 3 to the silicon oxide film, and 5 to the group element diffused into the silicon. First, silicon film 2
A silicon oxide film 3 is formed thereon, and the silicon oxide film 3 is patterned using a resist as a mask (FIG. 1).
次にこの酸化膜３をマスクにしてシリコン膜２
をエツチングする（第１図２）。このエツチング
液として一般にヒドラジンが用いられる。ヒドラ
ジンは異方性エツチング液でありシリコン表面が
（100）面の時、断面として（111）面を出すこと
ができる即ちテーパーエツチングをすることがで
きるという利点があるからである。こうして第１
図の２のようなシリコンアイラドが形成される。
またシリコンアイランドの側面の（111）面は
（100）面に比較して固定電荷が大きくリーク電流
が流れやすいので、その対策として通常側面の不
純物濃度を高くするという手段がとられる。特に
ＮチヤンネルのMOSイランジスタの場合シリコ
ンアイランド側面に不純物として族元素を酸化
膜３をマスクにしてイオン注入することによつて
行なわれる（第１図３）。 Next, using this oxide film 3 as a mask, the silicon film 2
(Fig. 1, 2). Hydrazine is generally used as this etching solution. This is because hydrazine is an anisotropic etching liquid and has the advantage that when the silicon surface is a (100) plane, it can produce a (111) plane as a cross section, that is, it can perform taper etching. Thus the first
A silicon island like 2 in the figure is formed.
In addition, the (111) side surface of the silicon island has a larger fixed charge than the (100) side, and leakage current tends to flow more easily.As a countermeasure to this, the usual measure is to increase the impurity concentration on the side surface. Particularly in the case of an N-channel MOS transistor, this is carried out by ion-implanting a group element as an impurity into the side surface of a silicon island using the oxide film 3 as a mask (FIG. 1, 3).
次に酸化膜３を除去する（第１図４）。 Next, the oxide film 3 is removed (FIG. 1, 4).
しかし、このような方法では最初のマスクに対
して計３回の転写工程（レジスト、酸化膜、シリ
コン）を要する為に設計と実際の寸法との誤差が
大きいという欠点、またヒドラジンによるシリコ
ン・エツチングにおいて側面に対するサイドエツ
チングが無視できないため側面へのイオン注入が
不確実であるという欠点を有する。またテーパー
の角度が選択酸化法（LOCOS法）などで生じる
段差の角度より急であるためテーパーの上を通る
配線に断線が生じやすいという欠点もある。 However, this method requires a total of three transfer steps (resist, oxide film, and silicon) for the first mask, resulting in a large error between the design and actual dimensions. However, since side etching on the side surfaces cannot be ignored, ion implantation into the side surfaces is uncertain. Another drawback is that the taper angle is steeper than the angle of the step created by the selective oxidation method (LOCOS method), so wires passing over the taper are more likely to break.
本発明は上記の欠点を除去した薄膜MISトラン
ジスタの形成方法を提供することを目的とする。 An object of the present invention is to provide a method for forming a thin film MIS transistor that eliminates the above-mentioned drawbacks.
本発明によれば絶縁体上に形成されたシリコン
薄膜にMISトランジスタを形成する薄膜MISトラ
ンジスタの形成方法において、前記シリコン薄膜
上にマスクパターンを形成し、次いでSiF4とO2
に族元素あるいは族元素を構成元素として含
む化合物ガスを加えた混合ガスを用いてドライエ
ツチングを行なうことによつて前記シリコン薄膜
をテーパーをもたせてエツチングし、同時に該エ
ツチングで現われた断面上に前記族あるいは
族元素を含んだSiO2膜を形成し、次いで熱処理
を行なつて前記シリコン薄膜中に前記族あるい
は族元素を拡散することを特徴とした薄膜MIS
トランジスタの形成方法が得られる。 According to the present invention, in a method for forming a thin film MIS transistor in which an MIS transistor is formed on a silicon thin film formed on an insulator, a mask pattern is formed on the silicon thin film, and then SiF 4 and O 2
The silicon thin film is etched in a tapered manner by performing dry etching using a mixed gas containing a group element or a compound gas containing a group element as a constituent element. A thin film MIS characterized in that a SiO 2 film containing a group element or a group element is formed, and then heat treatment is performed to diffuse the group element or group element into the silicon thin film.
A method for forming a transistor is obtained.
本発明は次の原理に基づく。SiF4とO2の混合
ガスはプラズマ中で下記の反応を生ずる。 The present invention is based on the following principle. A mixed gas of SiF 4 and O 2 causes the following reaction in the plasma.
SiF4＋O2→SiO2＋4F* ……
上記の反応に示されるようにSiF4，O2の混
合ガスをプラズマ中に注入するとSiO2と活性化
されたF*が生成する。ここでSiO2は堆積し、一
方F*は下記の反応式に従いSiと反応してSiF4（揮
発性）を生じる。 SiF 4 +O 2 →SiO 2 +4F * ... As shown in the above reaction, when a mixed gas of SiF 4 and O 2 is injected into plasma, SiO 2 and activated F * are generated. Here, SiO 2 is deposited, while F * reacts with Si to produce SiF 4 (volatile) according to the reaction equation below.
Si＋4F*→SiF4↑ ……
このプラズマ・エツチング機構の特徴はSiO2
膜の堆積とSiのエツチングが同時に起こることに
ある。 Si＋4F * →SiF 4 ↑ …… The feature of this plasma etching mechanism is SiO 2
This is because film deposition and Si etching occur simultaneously.
前者のSiO2の堆積反応に関して言えばこれは
SiO2の気相成長反応に準じている。この気相成
長の反応式は下記のようにあらわせ上記の反応
との違いは、反応ガスとしてのSiF4とSiH4と
の違いである。 Regarding the former SiO 2 deposition reaction, this is
This is similar to the SiO 2 vapor phase growth reaction. The reaction formula for this vapor phase growth is shown below, and the difference from the above reaction is that SiF 4 and SiH 4 are used as the reaction gases.
SiH4＋O2→SiO2＋2H*↑ ……
後者のSiエツチングに関してもこれは通常よく
用いられるCF4とO2との反応（）に準じており
このとの反応の特徴を兼ねそなえているのが
反応である。 SiH 4 +O 2 →SiO 2 +2H * ↑ ... Regarding the latter Si etching, this is similar to the commonly used reaction between CF 4 and O 2 (), and it also has the characteristics of this reaction. is the reaction.
CF4＋O2→CO2＋4F* ……
次にこのプラズマ・エツチングの効果を具体的
に説明する。絶縁基板上に形成されたシリコン薄
膜をエツチングするとき、CF4，O2の混合ガスに
代表されるような通常のプラズマエツチングを行
なつた場合、理想的には第２図のようなエツチン
グ断面が得られる。ここで２がSi薄膜、７がエツ
チングのマスク、８が絶縁基板である。ところが
SiF4，O2の混合ガスを用いた場合、Siのエツチ
ングと同時にSiO2の堆積が起こるため、第３図
のようにテーパーをもつたエツチング断面が得ら
れる。このテーパーエツチの機構は第４図に従つ
て次のように説明される。 CF 4 +O 2 →CO 2 +4F * ...Next, the effect of this plasma etching will be specifically explained. When etching a silicon thin film formed on an insulating substrate, if normal plasma etching is performed using a mixed gas of CF 4 and O 2 , ideally the etching cross section will be as shown in Figure 2. is obtained. Here, 2 is a Si thin film, 7 is an etching mask, and 8 is an insulating substrate. However
When a mixed gas of SiF 4 and O 2 is used, deposition of SiO 2 occurs simultaneously with etching of Si, resulting in a tapered etched cross section as shown in FIG. The mechanism of this taper etch will be explained as follows with reference to FIG.
プラズマ中でSiF4とO2は前述のように活性化
されたF*とSiO2を生ずる。F*はSiO2が堆積する
よるはやくSi表面をエツチングしはじめ、第４図
においてS1までエツチングしたとする。こととき
F*はそのスパツタ効果により基板の垂直方向に
対し水平方向をほとんどエツチングしないため、
ここにT1−T0の厚さをもつたSiO2が堆積する。
従つてこれをくり返していくとθ＝tan-1
（So−Sp／To−p）のテーパー角をもつたエツチング断
面
が得られる。このテーパー角θはSiF4に対する
O2の流量比を大きくすると小さくなり、Siのエ
ツチレートは減少する。 In the plasma, SiF 4 and O 2 produce activated F * and SiO 2 as described above. Assume that F * starts etching the Si surface as soon as SiO 2 is deposited, and etches up to S 1 in FIG. 4. Kototoki
Because F * hardly etches in the horizontal direction compared to the vertical direction of the substrate due to its sputtering effect,
SiO 2 with a thickness of T 1 −T 0 is deposited here.
Therefore, by repeating this, θ=tan -1
An etched cross section with a taper angle of (S o −S p /T o − p ) is obtained. This taper angle θ is for SiF 4
When the flow rate ratio of O 2 is increased, it becomes smaller, and the etching rate of Si decreases.
即ちSiF4とO2の流量比を調整することによつ
てテーパー角θの大きさを制御することができ
る。従つてエツチング中に上記流量比を変えれば
エツチング断面を曲面とすることができ、特に上
の凸の曲面を形成すればその上を通る配線を断線
を著しく減らすことができる。 That is, the magnitude of the taper angle θ can be controlled by adjusting the flow rate ratio of SiF 4 and O 2 . Therefore, by changing the flow rate ratio during etching, the etched cross section can be made into a curved surface, and in particular, by forming a curved surface with a convex top, it is possible to significantly reduce disconnection of the wiring passing over the curved surface.
更にエツチング時に族元素あるいは族元素
を含む化合物ガス（たとえばB2H6，PH3，AsH3
などの水素化物）をSiF4，O2の混合ガスととも
に供給すると堆積するSiO2の中に族元素ある
いは族元素がドープされるので、エツチング後
に高温熱処理をすることによつてシリコン・アイ
ランドの側面のみに族元素あるいは族元素を
拡散することが可能である。 Furthermore, during etching, a group element or a compound gas containing a group element (for example, B 2 H 6 , PH 3 , AsH 3
When a hydride ( such as hydrides such as It is possible to diffuse group elements or group elements only.
次に本発明をＮチヤンネルMOSトランジスタ
の形成に適用した場合を例にとり第５図に従つて
詳細に説明する。尚、図中の１はサフアイヤ基
板、２はシリコン基板、４はレジスト、５はシリ
コン中に拡散した族元素、６は族元素がドー
プしたSiO2膜に対応する。 Next, a case in which the present invention is applied to the formation of an N-channel MOS transistor will be explained in detail with reference to FIG. 5, taking as an example. In the figure, 1 corresponds to a sapphire substrate, 2 to a silicon substrate, 4 to a resist, 5 to a group element diffused into silicon, and 6 to a SiO 2 film doped with a group element.
まずシリコン基板上にレジスト４のパターンを
形成する（第５図１）。 First, a pattern of resist 4 is formed on a silicon substrate (FIG. 5, 1).
次にレジストをマスクにしてシリコンのドライ
エツチングを行う。ドライエツチング装置として
は一般に平行平板型プラズマエツチング装置が用
いられる。エツチング条件は圧力7.0Pa、高周波
電力300W、パワー密度0.24w／cm2であり、エツ
チングガスはSiF4とO2の混合ガスに、族元素
が構成元素として含まれる化合物ガス（ここでは
B2H6）を加えたものを供給する。ここではSiF4
とO2の流量比２：１とした。（SiF4＝30SCCM、
O2＝15SCCM）こうして得られたエツチング断
面は第５図の２に示したようにテーパーをもちな
おかつその部分には族元素（ここではＢ）がド
ープされたSiF4膜６が堆積している。 Next, dry etching of silicon is performed using the resist as a mask. A parallel plate type plasma etching apparatus is generally used as the dry etching apparatus. The etching conditions were a pressure of 7.0 Pa, high-frequency power of 300 W , and a power density of 0.24 w/ cm2 .
B 2 H 6 ) is added. Here SiF 4
The flow rate ratio of O 2 and O 2 was set at 2:1. ( SiF4 =30SCCM,
(O 2 = 15 SCCM) The etched cross section obtained in this way has a taper as shown in 2 in Fig. 5, and a SiF 4 film 6 doped with a group element (here B) is deposited on that part. .
さらにレジスト４をはくりし高温の熱処理をす
ると側面のシリコン中に族元素が拡散される
（第５図３）。 Further, when the resist 4 is removed and heat treatment is performed at a high temperature, group elements are diffused into the silicon on the side surfaces (FIG. 5, 3).
尚、テーパー角度及び族元素の濃度はエツチ
ング時に供給するそれぞれのガスの流量によつて
調整できる。最後にSiO2膜６をエツチングする
（第５図４）。 Note that the taper angle and the group element concentration can be adjusted by adjusting the flow rates of the respective gases supplied during etching. Finally, the SiO 2 film 6 is etched (FIG. 5, 4).
以上のように本発明は従来法に比較して転写工
程が少なく（レジスト、シリコン）かつドライ・
エツチングを用いているため寸法精度が高いとい
う長所に加え、シリコンアイランド側面に対する
族元素あるいは族元素の拡散が確実に行なう
ことができ、しかもテーパー角を制御できるとい
う効果がある。 As described above, the present invention requires fewer transfer steps (resist, silicon) and dry transfer compared to conventional methods.
In addition to the advantage of high dimensional accuracy due to the use of etching, the group element or group elements can be reliably diffused into the side surface of the silicon island, and the taper angle can be controlled.
以上の説明はSOS構造のＮチヤンネルMOSト
ランジスタを例としたが、本発明はSOS構造に限
らず一般に薄膜半導体を用いたMISトランジスタ
にも同様に応用できる。 Although the above description has been made using an N-channel MOS transistor with an SOS structure as an example, the present invention is not limited to the SOS structure but can be similarly applied to MIS transistors generally using thin film semiconductors.
第１図はSOS構造のMOSトランジスタにおけ
るシリコンアイランド形成に関する従来の工程を
示す概略断面図。第２図は従来のドライエツチン
グ法を用いて絶縁基板上のシリコン薄膜をエツチ
ングしたときの断面形状を示す概略断面図。第３
図、第４図は本発明の原理を説明するための概略
断面図。第５図は本発明の方法を説明するための
概略断面図。
図中の１はサフアイヤ基板、２はシリコン薄
膜、３はSiO2膜、４はレジスト、５はシリコン
中に拡散した族元素、６は族元素をドープし
たSiO2膜、７はエツチングマスク、８は絶縁基
板である。
FIG. 1 is a schematic cross-sectional view showing a conventional process for forming a silicon island in a MOS transistor with an SOS structure. FIG. 2 is a schematic cross-sectional view showing the cross-sectional shape of a silicon thin film on an insulating substrate etched using a conventional dry etching method. Third
FIG. 4 is a schematic sectional view for explaining the principle of the present invention. FIG. 5 is a schematic sectional view for explaining the method of the present invention. In the figure, 1 is a sapphire substrate, 2 is a silicon thin film, 3 is a SiO 2 film, 4 is a resist, 5 is a group element diffused into silicon, 6 is a SiO 2 film doped with a group element, 7 is an etching mask, 8 is an insulating substrate.
Claims (1)
ランジスタを形成する薄膜MISトランジスタの形
成方法において、前記シリコン薄膜上にマスクパ
ターンを形成し、次いでSiF4とO2に族元素あ
るいは族元素を構成元素として含む化合物ガス
を加えた混合ガスを用いてドライエツチングを行
なうことによつて前記シリコン薄膜をテーパーを
もたせてエツチングし、同時に該エツチングで現
われた断面上に前記族あるいは族元素を含ん
だSiO2膜を形成し、次いで熱処理を行なつて前
記シリコン薄膜中に前記族あるいは族元素を
拡散することを特徴とした薄膜MISトランジスタ
の形成方法。1. In a method for forming a thin film MIS transistor in which a MIS transistor is formed on a silicon thin film formed on an insulator, a mask pattern is formed on the silicon thin film, and then a group element or a group element is added to SiF 4 and O 2 as constituent elements. The silicon thin film is etched in a tapered manner by performing dry etching using a mixed gas containing a compound gas containing SiO 2 containing the above-mentioned group or group elements. 1. A method for forming a thin film MIS transistor, comprising forming a film and then performing heat treatment to diffuse the group or group elements into the silicon thin film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22652782A JPS59119763A (en) | 1982-12-25 | 1982-12-25 | Formation of thin film metal insulator semiconductor transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22652782A JPS59119763A (en) | 1982-12-25 | 1982-12-25 | Formation of thin film metal insulator semiconductor transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59119763A JPS59119763A (en) | 1984-07-11 |
| JPH0376577B2 true JPH0376577B2 (en) | 1991-12-05 |
Family
ID=16846523
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22652782A Granted JPS59119763A (en) | 1982-12-25 | 1982-12-25 | Formation of thin film metal insulator semiconductor transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59119763A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2782342B2 (en) * | 1988-05-10 | 1998-07-30 | 大成建設株式会社 | Environmental control facilities |
| JP2522041B2 (en) * | 1989-04-21 | 1996-08-07 | 富士電機株式会社 | Plasma etching method |
-
1982
- 1982-12-25 JP JP22652782A patent/JPS59119763A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59119763A (en) | 1984-07-11 |
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