JPH03241766A - Lsi package - Google Patents
Lsi packageInfo
- Publication number
- JPH03241766A JPH03241766A JP3890590A JP3890590A JPH03241766A JP H03241766 A JPH03241766 A JP H03241766A JP 3890590 A JP3890590 A JP 3890590A JP 3890590 A JP3890590 A JP 3890590A JP H03241766 A JPH03241766 A JP H03241766A
- Authority
- JP
- Japan
- Prior art keywords
- external connection
- package
- board
- lsi
- lsi package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 abstract description 2
- 238000007634 remodeling Methods 0.000 abstract 2
- 239000000523 sample Substances 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000012937 correction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はLSIパッケージに関する。[Detailed description of the invention] [Industrial application field] The present invention relates to an LSI package.
従来、LSIパッケージをプリント配線基板に搭載した
場合に、基板上の配線パターン等の設計ミスにより修正
を行うときは、LSIパッケージの外部接続ピンごとに
対応してあらかじめ基板上に設けた改造用パッド間に布
線を接続することがある。Conventionally, when an LSI package is mounted on a printed wiring board, when corrections are made due to design errors such as wiring patterns on the board, modification pads are prepared in advance on the board for each external connection pin of the LSI package. Wires may be connected between them.
一方、LSIパッケージの外部接続ピンが基板上に確実
にはんだ付けされているかどうかをチエツクするために
、LSI内部に外部接続ピンのうちの入力ピンから出力
ピンへのスルーパスを設け、入力ピンにあたえたパター
ンがそのままピンにあられれることを検証する方法をと
ることがある。また、基板のLSIパッケージ実装面の
裏側からネットに1対1に対応したプローブをたてて、
入力ピンに対応したプローブにテストパターンを印加し
、出力ピンに対応したプローブにあられれるパターンを
検証するインサーキットテスト法をとることもある。On the other hand, in order to check whether the external connection pins of the LSI package are securely soldered on the board, a through path is provided inside the LSI from the input pins to the output pins among the external connection pins, and the pins are connected to the input pins. Sometimes a method is used to verify that the pattern that was created can be applied to the pin as is. Also, from the back side of the LSI package mounting surface of the board, probes that correspond one-to-one to the net are set up.
An in-circuit test method is sometimes used in which a test pattern is applied to a probe corresponding to an input pin and the pattern applied to the probe corresponding to an output pin is verified.
上述したように従来のLSIパッケージは、外部接続ピ
ンが基板上にきちんとはんだ付けされているかどうかを
チエツクするためだけにスルーパスを設けることは、そ
のためにセレクタをはじめとするかなりのハード量が必
要になり、現実的には困難である。また、基板の両面に
LSIパッケージを実装した場合などは、LSIパッケ
ージ実装面の裏側からプローブをたてることは非常に困
難となる。更に、近年、基板上のLSIパッケージの実
装個数が増加し、実装LSIパッケージどうしの間隔が
狭くなるにつれて、上述した従来の改造用パッドを基板
上に設けることが困難になってきているという問題点が
ある。As mentioned above, in conventional LSI packages, providing a through path just to check whether external connection pins are properly soldered on the board requires a considerable amount of hardware, including selectors. This is difficult in reality. Furthermore, when LSI packages are mounted on both sides of the board, it is extremely difficult to set up a probe from the back side of the LSI package mounting surface. Furthermore, in recent years, as the number of LSI packages mounted on a board has increased and the distance between mounted LSI packages has become narrower, it has become difficult to provide the above-mentioned conventional modification pads on the board. There is.
本発明のLSIパッケージは、LSIパッケージにおい
て、外部接続ピンに1対1に対応した導電部分をパッケ
ージの上面に設けること、または、外部接続ピンがパッ
ケージを貫通して上面に導電部分が露出していることに
より構成される。The LSI package of the present invention is characterized in that a conductive part is provided on the top surface of the package in one-to-one correspondence with the external connection pin, or the external connection pin penetrates the package and the conductive part is exposed on the top surface. It is composed of
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1図(a)および(b)は本発明の一実施例のそれぞ
れ平面図および側面図である。第1図において、基板1
2上のパターン13に設けられたスルーホールに外部接
続ピン11が接続され、基板12はケース13上に搭載
されてカバー15により覆われているが、基板12はパ
ターン13と共にケース14の外部に露出されていて、
LSIパッケージの上部からパターンに接続可能となっ
ている。FIGS. 1(a) and 1(b) are a plan view and a side view, respectively, of an embodiment of the present invention. In FIG. 1, a substrate 1
The external connection pin 11 is connected to the through hole provided in the pattern 13 on the top 2, and the board 12 is mounted on the case 13 and covered by the cover 15, but the board 12 and the pattern 13 are connected to the outside of the case 14. being exposed,
It is possible to connect to the pattern from the top of the LSI package.
第2図(a)および(b)は本発明の別の実施例のそれ
ぞれ平面図および側面図である。第2図において、基板
22上のパターン23に設けられたスルーホールに外部
接続ピン21が接続され、外部接続ピン21に設けられ
たパッド24が、基板22を搭載したケース25の上面
に露出している。なお、ケース25にはLSIのチップ
28が搭載され、ボンディングワイヤ27によりパター
ン23に接続されている。FIGS. 2(a) and 2(b) are a plan view and a side view, respectively, of another embodiment of the invention. In FIG. 2, an external connection pin 21 is connected to a through hole provided in a pattern 23 on a substrate 22, and a pad 24 provided on the external connection pin 21 is exposed on the upper surface of a case 25 on which the substrate 22 is mounted. ing. Note that an LSI chip 28 is mounted on the case 25 and connected to the pattern 23 by a bonding wire 27.
以上説明したように本発明は、LSIパッケージの上面
に外部接続ピンと1対1に対応した導電部分が露出して
いるので、プリント基板上に予め改造用のパッドを要し
ないと共に、LSIパッケージの外部接続ピンとプリン
ト基板との間のはんだ付は不良の検査を容易にするとい
う効果がある。As explained above, the present invention has conductive parts exposed on the top surface of the LSI package in one-to-one correspondence with external connection pins, so there is no need for pads for modification on the printed circuit board, and Soldering between the connection pins and the printed circuit board has the effect of facilitating inspection for defects.
第1図(a)および(b)は本発明の一実施例のそれぞ
れ平面図および側面図、第2図(a)および(b)は本
発明の別の実施例のそれぞれ平面図および側面図である
。
11.21・・・外部接続ピン、12.22・・・基板
、13.23・・・パターン、14.25・・・ケース
、15.2E!・・・カバー、18.28・・・ボンデ
ィングワイヤ、24・・・パッド。FIGS. 1(a) and (b) are a plan view and a side view, respectively, of one embodiment of the present invention, and FIGS. 2(a) and (b) are a plan view and a side view, respectively, of another embodiment of the present invention. It is. 11.21... External connection pin, 12.22... Board, 13.23... Pattern, 14.25... Case, 15.2E! ...Cover, 18.28...Bonding wire, 24...Pad.
Claims (1)
に対応した導電部分をパッケージの上面に設けることを
特徴とするLSIパッケージ。 2、LSIパッケージにおいて、外部接続ピンがパッケ
ージを貫通して上面に導電部分が露出していることを特
徴とするLSIパッケージ。[Claims] 1. In an LSI package, one to one external connection pin
An LSI package characterized in that a conductive portion corresponding to the above is provided on the upper surface of the package. 2. An LSI package characterized in that an external connection pin passes through the package and a conductive portion is exposed on the top surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3890590A JPH03241766A (en) | 1990-02-19 | 1990-02-19 | Lsi package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3890590A JPH03241766A (en) | 1990-02-19 | 1990-02-19 | Lsi package |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03241766A true JPH03241766A (en) | 1991-10-28 |
Family
ID=12538211
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3890590A Pending JPH03241766A (en) | 1990-02-19 | 1990-02-19 | Lsi package |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03241766A (en) |
-
1990
- 1990-02-19 JP JP3890590A patent/JPH03241766A/en active Pending
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