JPH03237684A - Picture storage device - Google Patents

Abstract

PURPOSE:To simplify software constitution by reading picture element data in the direction of a row to which row selection data, column selection data and a row selection signal are supplied and in which a picture element is set to be a head, and reading picture element data in the direction of a column to which row selection data, column selection data and a column selection signal are supplied and in which the picture element is set to be the head. CONSTITUTION:A memory cell in the p-th row of a memory cell array 1 is selected in correspondence with row selection data (p) and memory cells from a q-th column to a q+a-th column in the memory cell array 1 are selected in correspondence with column selection data (q). Then, data on the memory cells in the p-th row q-th to q+a-th columns, which are selected by a row selection means 2 and an intra-row selection means 3 are read in correspondence with a row direction selection signal. The memory cell in the q-th column in the memory cell array 1 is selected in correspondence with column selection data (q) and the memory cells from the p-th row to the p+a-th row are selected in correspondence with row selection data (p). Then, data on the memory cells in p-th to p+a-th columns q-th column, which are selected by a column selection means 5 and an intra-column selection means 6 are read. Thus, software constitution becomes simple.

Description

[Detailed description of the invention] 【overview】

Regarding image storage devices, it is possible to reduce the number of memory accesses when performing image processing,
In addition, for the purpose of simplifying the software configuration of image processing, a memory cell array including memory cells in M rows and N columns, and a memory cell in the p-th row of the memory cell array are selected according to row selection data p. Row selection means and column selection data q
from the qth column to the (q+a)th column of the memory cell array according to
), and the memory cells in the pth row and qth to (q+a) columns selected by the row selection means and the intrarow selection means in response to a row direction selection signal. row data reading means for reading out the data of the memory cell array; column selection means for selecting the memory cell in the qth column of the memory cell array according to the column selection data q; Intra-column selection means for selecting the memory cells from the p-th row to the (p+a)-th row; ) column data reading means for reading the data of the memory cell in the qth column; the row selection means and the intra-row selection means are enabled by the row direction selection signal; The internal selection means is configured to be enabled by the column direction selection signal.

[Industrial application field] The present invention relates to a semiconductor image storage device.

[Conventional technology]

In conventional image storage devices, the pixel scanning direction on the image and the address direction on the image storage device uniquely correspond. FIG. 6 shows the relationship between pixels on an image and pixel storage locations on the memory map of the image storage device. This image consists of 256x256 pixels, and if the X and Y directions are taken as shown in the figure, any pixel has the coordinate (i
, j). The storage position of pixel (i, j) on the memory map corresponds to the position when the image is scanned in the X direction. This is because the pixels are arranged two-dimensionally, whereas the addresses on the memory map are arranged one-dimensionally and uniquely. For this reason, X
It is easy to process images along directions. However, when processing an image along the Y direction, even though the pixels on the image are consecutively arranged in the Y direction, the storage locations on the memory map are scattered.
There are problems in that the image processing becomes complicated, the number of accesses to the image storage device increases, and the processing time becomes longer. For example, as shown in FIG. 5, a window 1 of 20×10 pixels
When there is an object area 12 in the window 1 and image processing is performed by scanning the inside of the window 11 in the X and Y directions, the scanning in the Y direction is performed as shown in FIG. (20) Assign the initial value 96.6 to the address AO and bit i of the pixel in the upper left corner of FIG. 5 of the window 11. (21) Assign AO to the processing address A. (23) To process the next pixel, add 32 to address A.
The added value is set as a new address A, and a counter J, which is the Y coordinate on the window 11, is incremented. (24) If j≦jO, return to step 22. Here, JO is the number of pixels in the window 11 in the Y direction. If j>jO, (25) Increment bit l to process the next column. (26) If AO<99, that is, if it is not the last column, (27) Determine whether i≦7. If 1≦7, return to step 21. If 1>7, (28) Assign 0 to bit l, increment column start address AO, and return to step 21. If the above process is repeated and A099 is determined in step 26, (29) determine whether i≦2, and if 1≦2, return to step 21. If i>2, the process ends.

[Problem to be solved by the invention]

In the case of FIG. 5, the number of memory accesses is 4X10=40 when performing image processing by scanning in the X direction, but when performing image processing by scanning in the Y direction as described above. , 10X20=20 (] times.In addition, when performing image processing by scanning in the X direction, the software configuration is almost the same as shown in Figure 4, which will be described later. In view of the above-mentioned problems, the object of the present invention is to reduce the number of memory accesses when performing image processing, and to improve the software configuration of image processing. An object of the present invention is to provide an image storage device that can simplify image storage.

[Means to solve the problem]

FIG. 1 shows the basic configuration of an image storage device according to the present invention. In the figure, l is a memory cell array, which includes memory cells arranged in M rows and N columns. Reference numeral 2 denotes a row selection means, which selects a memory cell in the p-th row of the memory cell array l in accordance with row selection data p. In-row selection means 3 selects memory cells from the q-th column to the (q+a)-th column of the memory cell array 1 in accordance with column selection data q. Reference numeral 4 denotes row data reading means, which reads data from the memory cells in the pth row and qth to (q+a) columns selected by the row selection hand &2 and the in-row selection means 3 in response to the row direction selection signal. Reference numeral 5 denotes a column selection means, which selects a memory cell in the q-th column of the memory cell array 1 in accordance with column selection data q. Intra-column selection means 6 selects memory cells from the p-th row to the (p+a)-th row of the memory cell array 1 in accordance with the row selection data p. Reference numeral 7 denotes column data reading means, which reads data of the memory cells in the p-th to (p+a) rows and q-th columns selected by the column selecting means 5 and the intra-column selecting means 6 in response to the column direction selection signal. Note that the row selection means 2 and intra-row selection means 3 are enabled by the row direction selection signal, and the column selection means 5 and intra-column selection means 6 are enabled by the column direction selection signal.

[Effect]

By supplying row selection data p, column selection data q, and row selection signals to the storage device configured as described above, data of pixels (a+1) in the row direction starting from pixel (p, q) can be read. In addition, by supplying row selection data, 5 column selection data q, and a column selection signal, it is possible to read out the data of (a+1) pixels in the column direction starting from pixel (p, q). . Therefore, the number of memory accesses when performing image processing can be reduced, and the software configuration for image processing can be simplified.

[Embodiment] An embodiment of the present invention will be described below based on the drawings. FIG. 2 shows the overall configuration of the image storage device. The memory cell array 30 has a size of 256×256 as shown in FIG.
A memory cell C(i,
j) (i, j=Q~255). In Figure 2, C
(i, j) indicates only i, j) without C. This memory cell C(i.j) is constructed as shown in FIG. That is, memory cell C (i, j> is the component 31 to 3
5, bit memory 3] is enabled when the cell select terminal C5 is set to low level, and the bit memory 3 is enabled when the cell select terminal C5 is set to a low level, and
When set to low level, it enters the read state and the write terminal WR
When set to low level, the write state is entered. X selection line XWj
And the Y-direction byte data selection line YSi is an AND gate 3.
It is connected to the input terminal of 2, and the X direction byte data sorting line
Sj and Y selection line YWi are connected to the input terminal of AND gate 33, and the output terminals of AND gates 32 and 33 are connected to cell selection terminal C8 of bit memory 31 via NOR gate 34. The data input/output terminal of the bit memory 31 is connected to the selector 35.
through the X-direction data line X' or the Y-direction data line Yi
connected to either one. That is, when the direction selection signal X/Y supplied to the control terminal of the selector 35 is at a high level, the X direction data 1ilXj becomes valid and the Y direction data line Y1 becomes a high impedance state. Conversely, when the direction selection signal X/Y is at a low level, the Y-direction data line Y1 is enabled and the X-direction data line Xj is placed in a high impedance state. Further, the selector 35 is bidirectional, and depending on the level of the write terminal WR, the data line Xj
, Yi becomes the read direction or the write direction. In FIG. 2, the address of the memory cell array 30 is
The most significant bit address (q,
p) and the direction selection signal X/Y. When direction selection signal X/Y is at high level, memory cell C(i
, j) , 1=p−p+7, J=q 1 byte is selected. When the direction selection signal X/Y is low level,
Memory cell C (i, j) i=p, j=q~Q+7
1 byte of is selected. These p and q are externally supplied to and held in an 8-bit X address register 40X and Y address register 40Y, respectively. X address register 40X and Y
The output of the address register 40Y is supplied to the X address recorder 41X and the Y address recorder 41Y, respectively, and of the X selection lines XWO-XW225 connected to the output terminal of the X address recorder 41X, only xWp becomes high level, and the Y address recorder Of the Y selection lines YWO-YW255 connected to the output terminal of 41Y, only YWq becomes high level, and the others become low level. However, the X address recorder 41X is valid only when the direction selection signal X/Y inverted by the inverter 42 is high level, and the Y address recorder 41Y is valid only when the direction selection signal X/Y is high level. When disabled, all outputs are low level. The output of the X address register 40X is also supplied to the X selector 43X, and when the content of the X address register 40X is p, the X direction byte data selection mxso~X S 255 f! connected to the output terminal of the X selector 43X is supplied. ,xS
Only p-xSp+7 is at a high level, and the others are at a low level. However, the X selector 43X is valid only when the direction selection signal X/Y is at a high level, and when the direction selection signal Become. The X-direction byte data selection line XSj is connected to the memory cell C shown in FIG.
(i, j), connected to i=0 to 255. Similarly, the output of the Y7 address register 40Y is the output of the Y selector 43Y.
is also supplied, and when the content of the Y address register 40Y is q, the Y direction byte data selection lines YSO to YS255 connected to the output terminal of the Y selector 43Y are YSq-Y.
Only Sq+7 is at a high level, and the others are at a low level. However, the Y selector 43Y uses the direction selection signal X/Y.
It is valid only when the direction selection signal X/Y is at a low level.
is at a high level, the Y-direction byte data selection line YS
All O-YS255 become low level. The Y-direction byte data selection line YSi is connected to the memory cell C(i,
j), connected to j-0 to j-255. Such a configuration enables the above-mentioned address specification. X-direction data line Xj (j=0
~255) is connected to the data terminal of the byte data selector 44x, and the Y-direction data line Yi (i=o~255) of the memory cell c (i.j) is connected to the data terminal of the byte data selector 44x.
It is connected to the data terminal of the byte data selector 44Y. When the read signal RD is at a low level and the content of the X address register 40X is p, the node data selector 44X selects X p of the X direction data lines XO to x255.
-X p + 7 only is selected and taken out as 1 byte data to the data line 45-x. When the read signal ``fail'' is at a high level and the contents of the X address register 40X are p, the byte data selector 44X takes in the data on the data line 45 is supplied to the cell array 30.Similarly, when the read signal RD is at a low level, the Y address register 4
If the content of 0Y is q, the byte data selector 44
Y is yq to YQ+ among Y direction data lines YO to Y255
7 is selected and taken out as 1-byte data to the data line 45Y. When the read signal R is at a high level and the content of the Y address register 40Y is q, the byte data selector 44Y takes in the data on the data line 45Y and supplies it to the memory cell array 30 as data on yq to Yq+7. . Data lines 45X and 45Y are selectively connected to data line 47 via selector 46. That is, when the direction selection signal X/Y is at a high level, the selector 46 connects the data line 45X and the data line 47, disconnects the data line 45Y from the data line 47, and outputs the direction selection signal X/Y.
When Y is low level, data line 45Y is connected to data line 4
7 and disconnect the data line 45X from the data line 47. Further, the selector 46 is also a bidirectional buffer gate, and the redata direction becomes the read direction or the write direction depending on the level of the read signal RD. With the above configuration, X starting from any pixel (p, q)
It becomes possible to read and write 1-byte data of 8 pixels in the direction or the Y direction to the memory cell array 30. Next, the same process as shown in FIG. 7 when using this image storage device will be explained based on FIG. 4. (50) Set direction selection signal X/Y to low level, and set X (X
Set 6 in the address register (40X), and (51) Y
(Y address register 40Y) is set to 3. (52) Read 1-byte data of pixels (X, Y) to (X, Y+7) and perform data processing on each bit. (53) Add 8 to Y, (54) If Y≦12, return to step 52. If Y>12, (55) increment X; (56) if X≦20, return to step 51. If x>25, the process ends. Comparing FIG. 4 and FIG. 7, this embodiment has a simpler software configuration and fewer memory accesses than the conventional example (200 in the conventional example, 200 in the present example). 40 times). When performing image processing by scanning in the X direction, in FIG. 4, simply replace X and Y, replace constants 6 and 3, replace constants 12 and 25, and change "low level" in step 50 to " You can set it to "high level". Therefore, the overall software configuration becomes even simpler. Note that the present invention is characterized by reading out binary image data.
The writing of binary image data is not limited to the above configuration in which the operation is opposite to that of reading, but for example, in the write state, all memory cells C(i.j) are connected in series in the image scanning direction as a shift register, The structure may be such that binary data is transferred to this shift register in synchronization with image scanning.

【Effect of the invention】

As explained above, according to the image storage device according to the present invention, data of a plurality of consecutive pixels in the row direction or column direction starting from an arbitrary pixel can be read out from the memory cell array, so image processing can be performed. It has the excellent effect of reducing the number of memory accesses when performing image processing and simplifying the software configuration for image processing.
It greatly contributes to speeding up and facilitating real-time image processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the principle configuration of an image storage device according to the present invention. 2 to 4 relate to an embodiment of the present invention, in which FIG. 2 is a block diagram showing the overall configuration of an image storage device, and FIG. 3 is a block diagram showing the configuration of memory cell C(i, j). , FIG. 4 is a flowchart when the image within the window shown in FIG. 5 is scanned and processed in the Y direction. FIG. 5 is a diagram showing examples of image processing targets according to the present embodiment and the conventional example. 6 and 7 relate to the conventional example. FIG. 6 is a diagram showing the relationship between image pixels and storage positions on the memory map. FIG. 7 is a diagram showing the image in the window shown in FIG. 5 in the Y direction. It is a flowchart in the case of scanning and processing. In the figure, 30 is the memory cell array C (i, j) is the memory cell 40X is the X address register 40Y is the Y address register 41X is the X address recorder 41Y is the Y address recorder 43X is the X selector 43Y is the Y selector : Image 11: Window 12: Object area Figure 5

Claims (1)

[Claims] Memory cell array (1) comprising memory cells in M rows and N columns.
and a row selection means (2) for selecting the memory cell in the p-th row of the memory cell array in accordance with the row selection data p; an intra-row selection means (3) for selecting the memory cells up to column q+a); and p-th row and q-(q+a) columns selected by the row selection means and the intra-row selection means in accordance with the row direction selection signal. row data reading means (4) for reading data of the memory cell in the memory cell; column selection means (5) for selecting the memory cell in the q-th column of the memory cell array in accordance with column selection data q; intra-column selection means (6) for selecting the memory cells from the p-th row to the (p+a)-th row of the memory cell array in response to data p; column data reading means (7) for reading out the data of the memory cells in the p-th to (p+a)th rows and the q-th columns selected by the intra-column selecting means, and the row selecting means and the intra-row selecting means An image storage device characterized in that it is enabled by a row direction selection signal, and the column selection means and the intra-column selection means are enabled by the column direction selection signal.