JPH03237533A - Microcomputer - Google Patents

Abstract

PURPOSE:To prevent the malfunction that the mode is switched to the test mode because of external pulse noise by switching the mode to the test mode by AND between a test level detection signal and a test permission signal which is based on the test level detection signal, a reset signal, and an internal reset signal. CONSTITUTION:A test permission flag generating circuit 4 is provided which takes a reset signal SR1, an internal reset signal SR2, and a test level detection signal S6 as the input and outputs a test permission signal S8. When the pulse noise higher than the test level is applied to an input terminal T1, the signal S6 is generated. However, the signal S6 is not continuously generated in the period from release of the signal SR1 to release of the signal SR2. Therefore, the circuit 4 is cleared at the time of release of the signal S6, and a test recognition signal S4 of the circuit 4 is kept cleared though the signal S6 is generated again, and a test signal S7 is not generated. Consequently, the malfunction of switching to the test mode is avoided though the external pulse noise is applied in the middle of normal operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer, and more particularly to a microcomputer having a test signal generation circuit for setting a test mode.

[Conventional technology]

Conventionally, the test signal generation circuit for this type of microcomputer (hereinafter referred to as microcomputer) was a professional one as shown in Figure 5.
It is structured as follows.

This test signal generation circuit is connected to an input terminal TI,
It has a test level detection circuit 3 that outputs a test level detection signal S6 when a test level voltage VT corresponding to the test mode setting is applied to the input signal SX.

And the reset signal SR input to the reset terminal T.
is the reset signal ff supplied internally via the reset signal SB, DOPA, and FBR, and the internal reset signal FF which is released after a predetermined period of time after the reset signal SB is stopped via the wait circuit l. 2 reset signal SR2 is generated.

FIG. 6 is a timing chart for explaining the operation of the blocks in FIG. 5.

First, FIG. 6 shows the operation of setting the test mode.

In the period T21, the input signal SX of the input terminal TI.

The applied voltage is a test level voltage V higher than the logic voltage VDD
It is more than 1.

From now on, the test level detection signal 86 is generated, the test signal S7 becomes active, and the microcomputer enters the active state.

[Problem to be solved by the invention]

The conventional microcomputer described above easily switches to test mode and malfunctions even if a test signal is generated erroneously when a pulse noise higher than the test level voltage is applied to the input terminal of the test signal generation circuit during normal use. There was a drawback.

That is, as shown in FIG. 7, during the period T-3, the input signal S! Since the applied voltage ranges from the ground level (hereinafter referred to as GND level) to the power supply voltage level (hereinafter referred to as VDD level), the test level detection circuit 3 generates the test level detection signal S. First, since the test signal Sγ does not become active, the microcomputer enters a normal logical operation state.

In period TZ3, when pulse noise P of VDD or higher is applied to input terminal TI, test level detection signal S6
is erroneously generated, and the test signal S7 becomes active. As a result, the microcomputer enters a test mode and malfunctions.

Even if the period T snow aK input signal SX is the test level voltage V
Even if things go back to below 100, once a malfunction occurs, the microcontroller will go out of control, and there is a very small chance that it will return to normal operation.

An object of the present invention is to provide a microconbeater that is unlikely to switch to test mode erroneously due to external pulse noise.

[Means to solve the problem]

The microconbeater of the present invention is an internal resetter that inputs a reset signal to widen the width of the predetermined time.

A test signal equipped with a wait circuit that outputs a logic signal, and a test level detection circuit that outputs a test level detection signal and sets the test mode in response to a test level higher than the voltage of the normal logic signal among the input signals. In the microcomputer having a generation circuit, the test signal generation circuit includes an R-8 flip-flop that inputs the test level detection signal, the reset signal, and the internal reset signal and outputs a test permission signal based on these logic signals. The test permission flag generating circuit has a test permission flag generating circuit, and a test permission section has a test permission section having an AND circuit that outputs a logical product of the test permission signal and the test level detection signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a schematic diagram of an embodiment of the present invention.

The test signal generation circuit of the microcomputer is constructed by adding a test permission section 2 to the test level detection circuit 3, which inputs the test level detection signal S6 and the reset signal SR1v8R2 and outputs the test signal SA, as shown in FIG. .

The test permission section 2 includes a test permission flag generation circuit 4 which generates a test recognition signal S4 outputted by H, -8F/H, which receives DR multiplied signals of three signals corresponding to the test level detection signal S6 and reset signals SR1+SR2. and signal S
Test permission signal S8 of the logical product of 4 and reset signal SB2
AND circuit AND, which outputs the test enable signal S8.
and the test level detection signal S6.
It has an input ND circuit AND which outputs 7.

2 to 4 are timing charts for explaining the operation of the circuit shown in FIG. 1.

FIG. 2 shows the operation in test mode.

From the time the reset signal SRI is generated, the second reset signal S
The period 'I'tt-'I'tz during the at release seal is the reset mode MR, and the period s''Ig is the operation mode MD.

From release of reset signal 8R1 to internal reset signal S
During the T-th period until R2 is released, a voltage of test level 77 or higher is continuously applied to the input terminal TI, so
Test level detection signal 8sFi is generated continuously.

Therefore, the test permission flag generating circuit 4 remains set by the reset signal SRI, and since the second reset signal SR2 is not released, the test permission signal S8 is not generated.

During the period T13 after the release of the second reset signal SR2, the test permission flag generation circuit 4 is set, so the test permission signal Ss is generated.

Therefore, the test level detection signal S and the test permission signal S
Since both test signals 8 and s are generated, the AND circuit AND2 outputs the test signals 8 and 8. occurs, and the microcontroller enters test mode.

Next, FIG. 3 shows the operation in the normal logic operation state.

During the period T14''I'll, the input terminal Tx is connected to GND.
Since the voltage of the input signal SX within the range of -VDD level is applied, the test level detection signal S6 does not become active.

For this reason, the test signal S7 is not generated and the microcomputer is in a normal operating state.

Next, FIG. 4 shows the operation when noise is applied to the input terminal 2.

During period T16, input terminal T! When a pulse noise vP of test level 7 or more is applied to the test level detection signal S6, a test level detection signal S6 is generated.

However, since the test level detection signal S6 cannot continue to be generated during the period 'I'ts' from the release of the reset signal SRI to the release of the internal reset signal SR2, the test permission flag is The generation circuit 4 is cleared when the test level detection signal S6 is released,
Even if the test level detection signal S6 occurs again during the period 'I'ts, the test recognition signal S of the test permission flag generation circuit 4
4 remains cleared, and even after the internal reset signal 8R1 is released, the test permission signal S8 remains ON.

For this reason, the period T! Even if the test level detection signal S6 is generated from 6 to TF, the output of the test enable signal Ss is always 1.
Since the signal is 0#, the test signal S7 is not generated.

In this way, even momentarily during reset mode, connect VDD to GND.
When a level is applied to the input terminal Sx, the output of the test enable signal S8 is "0", even if the test level v
Even if a large pulse noise exceeding T is applied, normal operation is maintained and no malfunction occurs.

For example, the logic circuit of the middle test permission flag generation circuit 4 inverts three input signals, converts the 08 circuit into an AND circuit, and converts the NA
The ND circuit may be transformed into a NOR circuit.

〔Effect of the invention〕

As described above, the present invention does not enter the test mode state in the normal logic operating state even if pulse noise of a test level voltage or higher is applied to the test-common input terminal.

Therefore, even if external noise or the like is applied during normal operation, it is possible to avoid malfunctions such as being drawn into the test mode.

Fig. 4 is a typing chart of each part to explain the operation of the first block, Fig. 5 is a diagram of an example of a conventional microcomputer, and Figs. It is a timing chart of each part for explaining the operation of the pro.

l...Wait circuit, 2...Test permission section, 3...Test level detection circuit, 4-...
...Test permission flag generation circuit s S5...
Normal input signal, S...Test level detection signal, S7...Test signal sSm...Test permission signal, 8th...Input signal, 5R2SRI
--- Reset signal, SR□ --- Internal reset signal, TB --- Reset terminal, TI.
...Input terminal.

Claims (1)

[Claims] A wait circuit inputs a reset signal and outputs an internal reset signal with a wider predetermined time width, and a wait circuit outputs a test level detection signal in response to a test level higher than the voltage of the normal logic signal among the input signals. In the microcomputer, the microcomputer has a test signal generation circuit provided with a test level detection circuit that sets the test mode by inputting the test level detection signal, the reset signal, and the internal reset signal. A test permission flag generation circuit having an R-S flip-flop that outputs a test permission signal based on a logic signal, and an AND circuit that outputs a logical product of the test permission signal and the test level detection signal are added. A microcomputer characterized by: