JPH03236620A - Flip-flop circuit with reset function - Google Patents

Abstract

PURPOSE:To interrupt circuit power at reset state by providing a circuit generating a reset signal for a FF and a current adjustment signal from an external reset signal and providing a delay means between the circuit and the FF. CONSTITUTION:A gate voltage of a constant current FFTJ 11 is controlled by a current adjustment signal VR1 and a current I1 flows to the circuit. When a level of the signal VR1 gets higher, the circuit current is increased. A FF1 outputs an input signal DIN synchronously with a clock signal CK. When a reset signal SR is inputted, the FF 1 outputs an H or L level signal independently of the signal DIN or the CK. While an external reset signal RS0 is not inputted, a signal generating circuit 2 generates an L level as the reset signal RS1 and an H level as the signal VR1, and a prescribed circuit current flows to the FF 1. When the signal RS0 is at an L level, the FF acts like a conventional FF and when the RS0 changes from L to H, the VR1 changes from H to L and the circuit current of the FF 1 is interrupted. On the other hand, when the signal RS0 changes from L to H, the circuit current of the FF 1 is arisen and a current flows to the circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a flip-flop, and particularly to a flip-flop having a reset function and a power supply current adjustment function with improved performance.

[Conventional technology]

FIG. 4 shows a circuit diagram of a conventional flip-flop with a reset function, in which l is a flip-flop with a reset function, VDD is a power supply voltage, DIN is an input signal, CK is a clock signal, R8 is a reset signal, and OUT is the output signal. Furthermore, VD is a power supply voltage terminal, D is a data input terminal, C is a clock signal input terminal, R is a reset signal input terminal, and Q is an output signal terminal. In addition, Jll is a field effect transistor (hereinafter referred to as F) that constitutes a constant current circuit.
ET), the gate voltage VRl and FE
The circuit current 11 flowing through the flip-flop 1 is determined by the size of T.

Next, the operation will be explained.

The circuit current 11 of the flip-flop is determined by the following equation.

11=β(VR1-vP)”
-(t) where β: FET transconductance parameter VP: FET threshold voltage.

It can be seen from equation (1) that the circuit current 11 of the flip-flop can be changed by changing the gate potential VRI.

Furthermore, a flip-flop circuit is formed on a constant current circuit, is formed by a source-coupled logic circuit centered on a differential amplifier, and outputs an input signal DIN in synchronization with a clock signal CK. be. Also, since it has a reset function, when the reset signal R3 is not input, it performs normal operation, but when the reset signal R3 is input, the flip-flop l outputs the "old gh" or Lo-" as the input signal. It is output regardless of DIN or clock signal CK.

[Problem to be solved by the invention]

Since the conventional flip-flop circuit with a reset function is configured as described above, the flip-flop only has to stop in the "old GH" or Lo- state while the reset function is operating. Sometimes it is important to reduce the circuit current of a flip-flop to reduce power consumption.

In order to do this, it is conceivable to reduce the gate voltage of the constant current FET that controls the current of the circuit when the reset signal is input, thereby reducing the circuit current.

An example of a circuit for performing this operation will now be described with reference to FIG.

In the figure, the same reference numerals as in FIG. 3 indicate the same or corresponding parts, and 2 is a signal that controls the reset signal R'S of the flip-flop 1 and the gate potential of the constant current circuit FET from the externally inputted reset signal R3O. This is a signal generation circuit for generating VRI.

Next, the operation will be explained.

The signal generator 2 does not generate the signal RS unless the external reset signal R3O is input, and the VRI controls the gate potential of the constant current FET so that a current sufficient to operate the flip-flop flows. , so the flip-flop performs normal operation.

When the external reset signal R3O is input, the signal generation circuit 2 generates the signal R3, and at the same time, the potential of VRI decreases, and the flip-flop becomes "old gh" or
It becomes a Lo- state and stops, and the circuit current is also reduced.

However, by lowering the gate potential of the constant current FET, the FE
Reducing the current flowing through T means that the constant current FET has equivalently become high in resistance, so in the flip-flop circuit formed on the constant current circuit, all potentials approach the power supply voltage. It turns out. That is, all the potentials of the flip-flops become "High". This happens regardless of the presence or absence of the reset signal, so
Taking as an example a case where a circuit which becomes "Lo-" when the reset signal R3O is inputted is adopted as a flip-flop, the following problem occurs.

That is, in the flip-flop having the above reset function, it is necessary to start operation from the reset state (Low" state) at the same time as the reset signal RSO from the outside is released. However, if R5 changes at the same time as VRl, V
It happens that the signal R3 is released before RI becomes hll and the flip-flop circuit current 11 reaches a predetermined value and flows.In the state where this circuit current [l is reduced, the flip-flop All potentials of props are “
The problem is that the reset function does not work properly because it is not in the reset state (Low' state) and the circuit current flows and starts operating from this state. There is.

In the above, the flip-flop is in the reset state and is Low”
, but if a source-coupled logic circuit is used as the logic circuit and a positive signal and its inverted signal are used as each signal, the reset state will be "H".
It is a problem whether it is "high" or "Lo-".

This is because when the current is reduced, all the potentials of the flip-flop circuit are "old gh".
This is because the positive signal and its inverted signal are both "High" at the same time, and the states of the signals cannot be distinguished. Then, even if the circuit current reaches a predetermined value and the flip-flop starts operating from the state where both of these are "High",
There was a problem in that it was not possible to operate from the reset state.

This invention was made to solve the above problems, and it provides a reset function that can turn off the power of the circuit in the reset state, regardless of the state of the flip-flop at the time of reset or the configuration method of the logic circuit. The purpose of this invention is to provide a flip-flop circuit.

[Means to solve the problem]

The flip-flop circuit with a reset function according to the present invention includes a signal generation circuit that generates a flip-flop reset signal and a current adjustment signal from an external reset signal, and a signal generation circuit that is a path for the flip-flop reset signal. A delay means for delaying and outputting the reset signal is provided between the generation circuit and the flip-flop.

[Effect]

In this invention, a signal generation circuit is provided that generates a flip-flop reset signal and a current adjustment signal from an external reset signal, and a signal generation circuit that is a path for the flip-flop reset signal is connected to the flip-flop. In between, a delay means for delaying and outputting the reset signal is provided so that the reset signal is input to the flip-flop later than the current adjustment signal, so that when the reset signal is released, the circuit is first When the current is turned on and this circuit current reaches a desired value, the reset of the flip-flop is released, and the flip-flop starts operating from this reset state.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a flip-flop with a reset function according to an embodiment of the present invention, where the same reference numerals as in FIGS. 4 and 5 indicate the same or corresponding parts, and 2 indicates a reset signal R30 input from the outside. 3 is a signal generation circuit for generating a reset signal R3I of the flip-flop and a signal VR1 for controlling the gate potential of the constant current FET; 3 is a signal delay circuit for delaying the reset signal R3I generated from the signal generation circuit 2; Further, Jll is a field effect transistor (FET) that serves as the bottom of the constant current circuit, and has an N-type channel.

Next, the operation will be explained. First, as in the conventional case, the gate voltage of constant current FET J 11 is controlled by VRI, and current 11 flows through the circuit. Here, since the FET has an N-type channel, when the potential of the current adjustment signal VRI becomes high, the circuit current increases, and when it becomes low, the circuit current decreases.

Also, the flip-flop 1 is formed on a constant current circuit like the conventional one, and is formed by a source-coupled logic circuit centered on a differential amplifier, and synchronizes the input signal DIN with the clock signal GK. This is what is output. It also has a reset function, and if the reset signal R3 is not input manually, it will operate normally, but when R3 is input, the flip-flop will output the "old gh" or LO- output to the manual signal DIN or clock. It is output regardless of the signal CK.

This time, a new signal generation circuit 2 and a signal delay circuit 3 have been added, and when the external reset signal R3O is not input (herein referred to as LO-''), the signal generation circuit 2 allows the reset signal to be reset. L as signal R3I
ow, and “old ghl+” as the current adjustment signal VR1.
is generated. Since VRI is "old gh", a predetermined circuit current flows through the flip-flop. Further, R5I becomes R3 by the signal delay circuit 3, but this signal RS is the same as the signal RSO, and since Lo- is input to the flip-flop, the flip-flop does not enter the reset state. That is, when R3O is Lo-, it operates as a normal flip-flop.

Next, when R3O changes from "Low" to "old ghll", the current adjustment signal VRI first changes from "old gh" to Low.
As a result, the circuit current of the flip-flop is turned off and no current flows through the circuit. After this, R3 becomes L
However, since the current in the circuit has already been turned off, the signal R3 does not affect the operation of the circuit.After this, if RSO remains in the "old gh" state, the flip-flop This means that the circuit is stopped with the current turned off.

Next, when RSO changes from “old gh” to Lo-, the current adjustment signal VRI changes from “Low” to “High”.
The circuit current of the flip-flop turns on and current begins to flow through the circuit. After the circuit current is turned on by the signal delay circuit 3, R3 changes from “High” to L.
However, immediately after the circuit current is turned on, R3 becomes “Hi”.
gh'', the flip-flop enters the reset state at this time.After this, R3I is delayed from the signal delay circuit 3 and output as R3, and 'Lo-' is output from the old gh11.
Therefore, the reset state is released and the flip-flop starts operating from the reset state.

In the above embodiment, a configuration using a signal generator 2 and a signal delay circuit 3 was shown, but as shown in FIG. A similar effect can be obtained by using a signal inversion UB path 31 instead of 3.

Furthermore, in each of the above embodiments, a signal delay circuit or a signal inversion circuit is used to output the reset signal R3 to the flip-flop.
However, the point is that R3 is delayed after the external reset signal R3I is released and the circuit current is turned on.
It is only necessary that the voltage be set to "Low", and it is also possible to configure it as shown in FIG.

To explain in detail using the diagram, 32 is an OR circuit, Nl is the drain potential of Jll of the constant current FET, and the other components are the same or equivalent parts as in Figures 1 and 2 above. It represents.

Next, the operation will be explained. When RSO is Low', R3I is Lo- and VRI is "old gh", and Jl
Since l is turned on, the drain potential Nl of Jll is Lo
-, so R3 also becomes "Low" and the flip-flop performs normal operation.

Also, when RSO is “High”, R5I is “High”.
At h#, VRI becomes Lo- and Jll is turned off, reducing the circuit current. Further, at this time, the drain potential N1 of Jll becomes ``High''.

Here, when RSO changes from "High" to "Lo-", R3I becomes "Low" and VRI becomes "High", and Jll is turned on, so the drain potential of Jll becomes N1.
becomes “Low from old ghll”. RS is L.

-'' occurs when both R3I and N1 are Low, so RS becomes Low after the circuit current is turned on.

w”.In other words, RSO changes from “old gh” to Lo%1
When the voltage changes to 1'', the circuit current is first turned on, and since R3 is still ``High'' at this time, the flip-flop is in a reset state at this time.After this, N1 immediately becomes Lo-. Therefore, R3 changes from "old gh" to "Lo-", the reset state is released, and the flip-flop starts normal operation.

(Effects of the Invention) As described above, the flip-flop circuit with a reset function according to the present invention includes a signal generation circuit that generates a flip-flop reset signal and a current adjustment signal from an external reset signal. In addition, a delay means for delaying and outputting the reset signal is provided between the signal generation circuit and the flip-flop, which is the path for the reset signal of the flip-flop, so that when the reset signal is input, the circuit current is turned off and the reset signal is output. 7) At the same time as the signal is released, the current in the circuit becomes a predetermined value, the flip-flop enters the reset state, and normal operation can be performed immediately from that state, regardless of the reset state of the flip-flop. This has the advantage that the circuit current can be controlled and the flip-flop can be reset using an external reset signal.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a flip-flop with a reset function according to one embodiment of the present invention, FIGS. 2 and 3 are circuit diagrams of a flip-flop with a reset function according to another embodiment of the present invention, and FIGS. FIG. 5 shows a circuit diagram of a conventional flip-flop with a reset function. 1 is a flip-flop, 2 is a signal generation circuit, 3 is a signal delay circuit, 21.31 is a signal inversion circuit, 32 is an OR circuit,
Jll is a field effect transistor that constitutes a constant current circuit, VDD is a power supply voltage, DIN is an input signal, CK is a clock signal, R5O is an external reset signal, VRI is a current adjustment signal, OUT is an output signal, and VD is a Power supply voltage terminal, D is data input terminal, C is clock signal input terminal, R
is the reset signal input terminal of the flip-flop, Q is the output signal terminal, and Nl is the drain potential of constant current FET Jll. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A constant current circuit that flows a current according to the voltage, a flip-flop connected as a load of the constant current circuit and having a reset function, a control signal that stops the constant current operation of the constant current circuit, and the flip-flop A signal generator that generates a reset signal using an external signal and a delay circuit that delays the reset signal generated by the signal generator are provided, and the reset signal lags behind the control signal that stops the constant current. A flip-flop circuit with a reset function, characterized in that the reset function is input to the flip-flop.