JP2572866B2 - Flip-flop circuit with reset function - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-flop, particularly to a flip-flop having a reset function and a power supply current adjusting function with high performance.

[Conventional technology]

FIG. 4 is a circuit diagram of a conventional flip-flop with a reset function. In the figure, 1 is a flip-flop having a reset function, VDD is a power supply voltage, DIN is an input signal, CK
Is a clock signal, RS is a reset signal, and OUT is an output signal. VD is a power supply voltage terminal, D is a data input terminal,
C is a clock signal input terminal, R is a reset signal input terminal, and Q is an output signal terminal. J11 is a field effect transistor (hereinafter abbreviated as FET) constituting a constant current circuit, and determines a circuit current I1 flowing through the flip-flop 1 according to the gate voltage VR1 and the size of the FET.

 Next, the operation will be described.

 The circuit current I1 of the flip-flop is determined by the following equation.

I1 = β (VR1−VR) ² (1) where β: transconductance parameter of FET VP: threshold voltage of FET.

Equation (1) shows that the circuit current I1 of the flip-flop can be changed by changing the gate potential VR1.

The flip-flop circuit is formed on a constant current circuit, is formed by a source-coupled logic circuit centered on a differential amplifier, and converts an input signal DIN into a clock signal C.
Output in synchronization with K. In addition, since it has a reset function, normal operation is performed when the reset signal RS is not input. However, when the reset signal RS is input, the flip-flop 1 outputs “High” or “Low” output to the input signal DIN or It is output regardless of the clock signal CK.

[Problems to be solved by the invention]

Since the conventional flip-flop circuit with a reset function is configured as described above, it is as if the flip-flop is stopped in the “High” or “Low” state during the reset function operation. It is important to reduce the circuit current of the flip-flop in order to reduce the power consumption, in order to do so, when a reset signal is input, the constant current FE that controls the circuit current
It is conceivable to reduce the gate voltage of T to reduce the circuit current.

Here, an example of a circuit for performing this operation will be described with reference to FIG.

3, the same reference numerals as those in FIG. 3 denote the same or corresponding parts, and reference numeral 2 denotes a reset signal RS0 from the externally input reset signal RS of the flip-flop 1 and a FE for a constant current circuit.
This is a signal generation circuit for generating a signal VR1 for controlling the gate potential of T.

 Next, the operation will be described.

If the reset signal RS0 from the outside is not input, the signal generator 2 does not generate the signal RS, and the VR1 sets the gate potential of the constant current FET so that a sufficient current flows for the flip-flop to operate. , The flip-flop performs a normal operation.

Then, when an external reset signal RS0 is input, the signal generation circuit 2 generates a signal RS, and at the same time, the potential of VR1 decreases, and the flip-flop is stopped in a “High” or “Low” state, Circuit current is also reduced.

However, lowering the gate potential of the constant-current FET and reducing the current flowing through the FET means that the constant-current FET has become equivalently a high resistance, so it was formed on the constant current circuit. In the flip-flop circuit, all potentials approach the power supply voltage. That is, all the potentials of the flip-flops become “High”. This occurs irrespective of the presence or absence of the reset signal. Therefore, the following problem occurs when a circuit that goes low when the reset signal RS0 is input is employed as a flip-flop.

That is, in the flip-flop having the reset function, it is necessary to start the operation from the reset state (Low state) at the same time when the external reset signal RS0 is released. "Hig
Before "h" and the circuit current I1 of the flip-flop reaches a predetermined value, the signal RS is released. When the circuit current I1 is reduced, all the potentials of the flip-flop are reduced. Is "High" and is not in the reset state (Low state). From this state, the circuit current flows and the operation starts.
There is a problem that the reset function does not operate normally.

In the above description, an example in which the flip-flop is in the reset state and becomes “Low” has been described as an example. Is “High”,
This is a problem regardless of whether the signal is low or low. When the current is reduced, all the potentials of the flip-flop circuit are "high", so that the positive signal and its inverted signal are also simultaneously "high". This is because the state of the signal cannot be distinguished, and even if the current of the circuit becomes a predetermined value and the flip-flop starts operating from the state of both being “High”, the reset state There was a problem that the operation from the device could not be performed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has a reset function capable of turning off circuit power in a reset state irrespective of a reset state of a flip-flop or a configuration method of a logic circuit. It is an object of the present invention to provide a flip-flop circuit provided with.

[Means for solving the problem]

A flip-flop circuit with a reset function according to the present invention has a control terminal, and in accordance with a control signal to the control terminal,
A constant current circuit for controlling a current flowing through a load circuit connected to the output terminal; and a reset terminal connected as a load circuit of the constant current circuit and having a reset terminal. The reset function is performed by an input signal input to the reset terminal. The flip-flop to be activated or released, the output signal for activating or releasing the reset function by an external signal, and the control signal to the constant current circuit for controlling the reduction or recovery of the current flowing through the flip-flop are linked to each other. A signal generator to be generated, and a control signal interposed between the signal generator and the reset terminal for restoring a current flowing through the flip-flop when the reset function of the flip-flop is released is applied to the control terminal. An input signal to the reset terminal is issued in response to the output signal so that the reset function of the flip-flop is released with a delay. A delay circuit which is those with.

[Action]

According to the present invention, when releasing the reset function of the flip-flop, an output signal for releasing the reset function from the signal generator in response to an external signal and a control signal for controlling the recovery of the current flowing through the flip-flop are linked. In response to the output signal of the signal generator, a signal is output from the delay circuit to the reset terminal so that the reset function of the flip-flop is released later than the application of the control signal to the control terminal of the constant current circuit. Since an input signal is generated, when an external signal for releasing the reset function is input, first, the constant current circuit is turned on, and when the circuit current reaches a desired value, the reset of the flip-flop is released. The flip-flop starts operating from this reset state.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a flip-flop with a reset function according to an embodiment of the present invention. The same reference numerals as in FIGS. 4 and 5 denote the same or corresponding parts, and 2 denotes a reset signal RS0 input from the outside. And a signal delay circuit 3 for delaying the reset signal RS1 generated from the signal generation circuit 2 for generating a reset signal RS1 of the flip-flop and a signal VR1 for controlling the gate potential of the constant current FET. J11 is a field-effect transistor (FET) constituting a constant current circuit and has an N-type channel.

Next, the operation will be described. First, as in the conventional case, the gate voltage of the constant current FET 11 is controlled by VR1, and a current I1 flows through the circuit. Here, since the FET has an N-type channel, the circuit current increases as the potential of the current adjustment signal VR1 increases, and the circuit current decreases as the potential decreases.

The flip-flop 1 is formed on a constant current circuit as in the prior art, is formed by a source-coupled logic circuit centered on a differential amplifier, and synchronizes an input signal DIN with a clock signal CK. Output. In addition, it has a reset function and performs a normal operation when the reset signal RS is not input. However, when the RS is input, the flip-flop outputs “High” or “Low” output to the input signal DIN or the clock signal. It is output regardless of CK.

Then, a signal generation circuit 2 and a signal delay circuit 3 are newly added this time.
In a state where the external reset signal RS0 is not input (here, it is set to Low), the signal generation circuit 2 causes the reset signal RS1 to be “Low” and the current adjustment signal VR1 to be “High”. Is generated. VR1 is “High”
Therefore, a predetermined circuit current flows through the flip-flop. Further, RS1 is converted to RS by the signal delay circuit 3, and since this signal RS is the same as the signal RS0 and Low "is input to the flip-flop, the flip-flop does not enter the reset state. When it is "Low", it operates as a normal flip-flop.

Next, when RS0 changes from "Low" to "High", first, the current adjustment signal VR1 changes from "High" to "Low", so that the circuit current of the flip-flop is turned off and no current flows through the circuit. After that, RS changes from Low to “High”, but since the current of the circuit is already off, the signal RS does not affect the operation of the circuit.After that, RS0 is in the “High” state. This means that the flip-flop is stopped with the circuit current turned off.

Next, when RS0 changes from "High" to "Low", first, the current adjustment signal VR1 changes from "Low" to "High", so that the circuit current of the flip-flop is turned on, and the current starts flowing through the circuit. After the circuit current is turned on by the signal delay circuit 3, RS changes from “High” to “Low”. Immediately after the circuit current is turned on, RS is “High” and the flip-flop is reset at this time. Thereafter, RS1 is delayed from the signal delay circuit 3 and output as RS, and changes from "High" to "Low".
, The reset state is released, and the flip-flop starts operating from the reset state.

In the above embodiment, the signal generator 2 and the signal delay circuit 3
2, the signal inverting circuit 21 is used instead of the signal generating circuit 2 and the signal inverting circuit 31 is used instead of the signal delay circuit 3 as shown in FIG. Similar effects can be obtained.

In each of the above embodiments, a reset signal RS to the flip-flop is provided by using a signal delay circuit or a signal inversion circuit.
The point is that RS only needs to be low after the external reset signal RS1 is released and the circuit current is turned on, and a configuration as shown in FIG. 3 is also possible. .

In detail with reference to the drawings, 32 is an OR circuit, N1 is the drain potential of J11 of the constant current FET, and the other components are the same or equivalent to those in FIGS. Is represented.

Next, the operation will be described. When RS0 is Low, RS1 is
When "Low", VR1 becomes "High" and J11 is turned on, so that the drain potential N1 of J11 becomes "Low", so that RS also becomes "Low" and the flip-flop performs a normal operation.

When RS0 is “High”, RS1 is “High” and VR1 is Lo.
w ", and the circuit current is reduced because J11 is turned off. At this time, the drain potential N1 of J11 becomes" High ".

Here, when RS0 changes from “High” to “Low”, RS0
1 is Low, VR1 is High, and J11 is turned on.
Of the drain potential N1 changes from “High” to Low.
RS is low when both RS1 and N1 are low, so RS goes low after the circuit current is turned on. That is, RS0 is “H”
When the current changes from “igh” to “Low”, the circuit current first turns on,
At this time, since the RS is still at “High”, the flip-flop is reset at this time. After this, N1 immediately becomes Lo
Since it is "w", RS changes from "High" to "Low", the reset state is released, and the flip-flop starts normal operation.

〔The invention's effect〕

As described above, according to the flip-flop circuit with the reset function of the present invention, when releasing the reset function of the flip-flop, the output signal and the flip-flop for releasing the reset function from the signal generator according to the external signal A control signal for controlling the recovery of the current flowing through the flip-flop is generated in conjunction with the control signal, and the signal is generated such that the reset function of the flip-flop is released later than the application of the control signal to the control terminal of the constant current circuit. Since the delay circuit generates an input signal to the reset terminal according to the output signal of the device, when an external signal for releasing the reset function is input, the constant current circuit is first turned on, and the circuit current is set to a predetermined value. And the flip-flop is reset,
The normal operation can be immediately performed from that state, and the circuit current can be controlled and the flip-flop can be reset by an external reset signal regardless of the reset state of the flip-flop.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a flip-flop with a reset function according to one embodiment of the present invention, FIGS. 2 and 3 are circuit diagrams of a flip-flop with a reset function according to another embodiment of the present invention, and FIGS. FIG. 5 is a circuit diagram of a conventional flip-flop with a reset function. 1 is a flip-flop, 2 is a signal generation circuit, 3 is a signal delay circuit, 21 and 31 are signal inversion circuits, 32 is an OR circuit, J11 is a field effect transistor constituting a constant current circuit, VDD is a power supply voltage, and DIN is Input signal, CK is clock signal, RS0 is reset signal from outside, VR1 is current adjustment signal, OUT is output signal, VD is power supply voltage terminal, D is data input terminal, C is clock signal input terminal, R is flip-flop Reset signal input terminal, Q is output signal terminal, N1 is constant current FET J11
Is the drain potential. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] A constant current circuit having a control terminal for controlling a current flowing through a load circuit connected to an output terminal of the constant current circuit in response to a control signal to the control terminal; A flip-flop connected and having a reset terminal and having a reset function activated or released by an input signal input to the reset terminal; an output signal for activating or releasing the reset function by an external signal; A signal generator that generates a control signal to the constant current circuit that controls the current reduction or recovery of the current flowing through the flip-flop in conjunction with each other; and a signal generator that is interposed between the signal generator and the reset terminal. Rather than applying the control signal to the control terminal for restoring the current flowing through the flip-flop when releasing the reset function of the flip-flop. Which are as reset function of the flip-flop is released, the reset function flip-flop circuit and a delay circuit for generating an input signal to the reset terminal in response to the output signal.