JPH03235339A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH03235339A
JPH03235339A JP2032797A JP3279790A JPH03235339A JP H03235339 A JPH03235339 A JP H03235339A JP 2032797 A JP2032797 A JP 2032797A JP 3279790 A JP3279790 A JP 3279790A JP H03235339 A JPH03235339 A JP H03235339A
Authority
JP
Japan
Prior art keywords
electrode pads
semiconductor element
long side
zip
soj
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2032797A
Other languages
Japanese (ja)
Inventor
Kiyoaki Tsumura
清昭 津村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2032797A priority Critical patent/JPH03235339A/en
Publication of JPH03235339A publication Critical patent/JPH03235339A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Abstract

PURPOSE:To reduce the number of electrode pads of the same function to only one, to suppress the nonuniformity of characteristics and to prevent the lowering of humidity resistance by wiring the electrode pads on the long side of a semiconductor element to inner leads on the short side/the long side when semiconductor elements of the same function are assembled in different kinds of packages. CONSTITUTION:Electrode pads 3 are provided on the two long sides of a semiconductor element so that they correspond to SOJ (Small Outline J-leaded package), and wiring is made by stretching wires 5 on the semiconductor element from the pads 3 on the long sides to inner leads 4 so arranged on the short sides as to correspond to ZIP(Zigzag in-line package). In another way, the pads 3 are provided on one long side and the two short sides so that they correspond to the ZIP, and wiring is made by stretching the wires 5 on the semiconductor element from the pads on the short sides to the leads 4 so arranged on the long side as to correspond to the SOJ. According to this constitution, the electrode pads of the same function can be reduced to only one, the nonuniformity of characteristics is suppressed and the lowering of humidity resistance is eliminated.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体素子の電極パッドを一機能に対して
一個、・）パッドを対応させることとで、素子寸法の増
大を抑え、特性のばらつきや耐湿性劣化を抑える半導体
装置、及び、信号遅延の少ない半導体装置に関するもの
である。[Detailed Description of the Invention] [Industrial Field of Application] This invention suppresses the increase in device size and improves the characteristics by assigning one electrode pad to a semiconductor device for one function. The present invention relates to a semiconductor device that suppresses variations and deterioration of moisture resistance, and a semiconductor device that has less signal delay.

〔従来の技術〕[Conventional technology]

第７図は従来の半導体素子をＳ　ＯＪ　（ＳｍａｌｌＯ
ｕｔｌｌｎｅ　Ｊ　−１ｅａｄｅｄ　ｐａｃｋａｇｅ　
）　ＩＣ組立時ノワイヤポンド後の正面図、第８図は第
７図の半導体素子をＺ　Ｉ　Ｐ　（Ｚｉｇｚａｇ　ｉｎ
　−１ｉｎｅ　ｐａｃｋａｇｅ）に組立時のワイヤボン
ド後の正面図である。図において、半導体素子（１４１
はグイパッド（２）に固定され、半導体素子Ｃ１４１上
には、その内部の能動回路へ信号を出入するための正方
形で示した電極パッド（３）が設けられ、パッケージ外
へ１８号を伝達するため、インナーリード（４ンと金＾
細線（ツイヤ）（５）で配線されている。Figure 7 shows a conventional semiconductor device as an SOJ (SmallOJ).
utllne J-1eaded package
) Figure 8 is a front view of the semiconductor device shown in Figure 7 after the wiring board is assembled when the IC is assembled.
-1ine package) after wire bonding during assembly. In the figure, a semiconductor element (141
is fixed to the Gui pad (2), and an electrode pad (3) shown as a square is provided on the semiconductor element C141 for inputting and outputting signals to the internal active circuit, and for transmitting No. 18 to the outside of the package. , inner lead (4n and gold ^
Wired with thin wire (5).

次に動作について説明する。上記の様憂こ同一機能の半
導体素子Ｑ４）を５（ＪＪ、ＺＩＰのように異なるパッ
ケージに組立ることは、メモリＩｃにおいて多く行われ
るものであるが、近年、ますます高集積化が進み、半導
体素子Ｑ青の寸法が巨大化し、とりわけ、・ＳＯＪと１
．ＩＰｌこおいては、配線する電極パッド（３〕を便い
わけている。即ち、ＳＯＪの場合は、インナーリード（
４）が長辺側の２列に配列さｎる為、長辺に電極パッド
（３ンを設け、ＺＩＰの場合は、インナーリード（４）
が長辺側と短辺側の３列に配列される為、ＳＯＪで長辺
に設けていた電極パッド（３）と同一機能の電極パッド
（３）を短辺２列に設けている。Next, the operation will be explained. As described above, assembling semiconductor elements Q4) with the same function into different packages such as 5 (JJ, ZIP) is often done in memory ICs, but in recent years, with increasing integration, The dimensions of the semiconductor element Q blue have become huge, especially ・SOJ and 1
．． In IPl, the electrode pads (3) to be wired are separated.In other words, in the case of SOJ, the inner leads (3) are separated.
4) are arranged in two rows on the long side, electrode pads (3) are provided on the long side, and in the case of ZIP, inner leads (4) are arranged on the long side.
are arranged in three rows on the long side and short side, so electrode pads (3) having the same function as the electrode pads (3) provided on the long side in SOJ are provided in two rows on the short side.

この為、一方のパッケージでは、図に示すごとく斜線を
施した電極パッド（３）が、インナーリード（４）と配
線されない状態で残される。Therefore, in one package, the diagonally shaded electrode pad (3) as shown in the figure is left unwired with the inner lead (4).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の半導体装置は以上のように措成さ口ているので、
電極パッドの数が増えて、半導体素子の寸法が大きくな
るとともに、同一信号が異なる電極パッドから入出力さ
れる為、パッケージによって特性のばらつきが発生し、
更（こ、配線しない電極パッドの腐食は、配線した電極
パッドより速く進行する為、耐湿性の低下を引き起こす
なとの問題点があった。Conventional semiconductor devices are constructed as described above.
As the number of electrode pads increases and the dimensions of semiconductor elements become larger, the same signal is input and output from different electrode pads, resulting in variations in characteristics depending on the package.
Furthermore, corrosion of unwired electrode pads progresses faster than that of wired electrode pads, so there was the problem of not causing a drop in moisture resistance.

また、ＺＩＰに限り、短辺側と長辺側のインナーリード
を引き回す距離か違う為、インナーリードのインダクタ
ンスにより信号遅延の違いを発生させる問題もあっｔこ
。Also, with ZIP, the length of the inner leads on the short side and long side is different, so there is a problem that the inductance of the inner leads causes a difference in signal delay.

この発明は上記のような問題点を解消するためになさ口
だもので、第１の発明は、同一機能の電極パッドを複数
設けず一つのみとして半導体素子の寸法を小さ（して、
パッケージによる特性のばらつきを押え、耐湿性が低下
しない半導体装置を得ることを目的とする。This invention is an attempt to solve the above-mentioned problems, and the first invention is to reduce the size of a semiconductor element by providing only one electrode pad with the same function, instead of providing multiple electrode pads with the same function.
The purpose of the present invention is to suppress variations in characteristics depending on the package and to obtain a semiconductor device whose moisture resistance does not deteriorate.

さらに第２図の発明は、リードのインダクタンスを抑え
、信号遅延の少ない半導体装置を得ることを目的とする
。Furthermore, the invention shown in FIG. 2 aims to suppress lead inductance and obtain a semiconductor device with less signal delay.

〔課題を解決するための手段〕[Means to solve the problem]

第１の発明に係る半導体装置は、ＳＯＪ対応で、半導体
素子の長辺二辺に電極パッドを設け、ＺＩＰ対応で短辺
側に配列さｎるインナーリードへ、上記長辺の電極パッ
ドから半導体素子上にワイヤを走らせて配線するか、ま
たは、ＺＩＰ対応で、半導体素子の長辺−辺と短辺二辺
に電極パッドを設け、ＳＱＪ対応で長辺側に配列さｎる
インナーリードへ、上記短辺の電極パッドから半導体素
子上にワイヤを走らせて配線したものである。The semiconductor device according to the first invention is compatible with SOJ and has electrode pads on two long sides of the semiconductor element, and is compatible with ZIP and connects the semiconductor device from the electrode pads on the long sides to n inner leads arranged on the short side. Either run wires on the device for wiring, or use ZIP compatible to provide electrode pads on the long side and two short sides of the semiconductor device, and connect to inner leads arranged on the long side for SQJ compatible. Wires are run from the short-side electrode pads onto the semiconductor element.

さらに第２の発明は、ＳＯＪ対応で、半導体素子の長辺
二辺に電極パッドを設け、インナーリードを長辺−辺に
配列したＺＩＰ対応に、反対側の長辺の電極パッドから
半導体素子上にワイヤを走らせて配線したものである。Furthermore, the second invention is compatible with SOJ, and is compatible with ZIP in which electrode pads are provided on two long sides of the semiconductor element and inner leads are arranged from long side to side, and the electrode pads on the opposite long side are placed on the semiconductor element. The wiring was done by running wires through the.

〔作用〕[Effect]

この発明における金属細線（ワイヤ）は、電極パッドに
ボンディングされたボールから始り、半導体素子の土を
通り、電極パッドの設けられている辺の隣辺または対辺
に配列されているインナーリードへ配線さね、インナー
リード近くの辺に電極パッドを設けた場合と同様に配線
を行なう。The thin metal wire (wire) in this invention starts from the ball bonded to the electrode pad, passes through the soil of the semiconductor element, and is wired to the inner lead arranged on the side adjacent to or opposite to the side where the electrode pad is provided. Wiring is done in the same way as when electrode pads are provided on the sides near the inner leads.

〔実施例〕〔Example〕

以下、この発明の第１の発明の実施例を図について説明
する。第１図は、長辺二辺に電極パッドを設けた半導体
素子をＳＯＪに組立時のワイヤボンド後の正面図で、第
２図は、第１図の半導体素子をＺＩＰに組立時のワイヤ
ボンド後の正面図である。また第３図は、長辺−辺と短
辺二辺に電極パッドを設けた半導体素子をＺＩＰに組立
時のワイヤボンド後の正面図で、第４図は、第３図の半
導体素子をＳＯＪに組立時のワイヤボンド後の正面図で
ある。Embodiments of the first aspect of the present invention will be described below with reference to the drawings. Figure 1 is a front view after wire bonding when assembling a semiconductor element with electrode pads on two long sides into an SOJ, and Figure 2 is a front view after wire bonding when assembling the semiconductor element in Figure 1 into a ZIP. It is a rear front view. Fig. 3 is a front view of a semiconductor element with electrode pads provided on the long side and two short sides after wire bonding when assembled in a ZIP, and Fig. 4 is a front view of the semiconductor element in Fig. 3 in an SOJ. FIG. 3 is a front view after wire bonding during assembly.

次１こ、第２の発明の一実施例を図について説明する。Next, an embodiment of the second invention will be described with reference to the drawings.

第５図は、長辺二辺に電極パッドを設けた半導体素子を
ＳＵＪに組立時のワイヤボンド後の正面図で、第６図は
、第５図の半導体素子をリードのインダクタンスを抑え
たＺＩＰに組立時のワイヤボンド後の正面図である。Figure 5 is a front view after wire bonding when assembling a semiconductor element with electrode pads on two long sides to SUJ, and Figure 6 is a ZIP that suppresses the lead inductance of the semiconductor element in Figure 5. FIG. 3 is a front view after wire bonding during assembly.

図において、（２）〜（５）は第７図の従来例に示した
ものと同等であるので説明を省略する。αυ、（２）。In the figure, (2) to (5) are the same as those shown in the conventional example of FIG. 7, so their explanation will be omitted. αυ, (2).

備は半導体素子である。The equipment is a semiconductor element.

次に動作について説明する。この発明を実現させたのは
、近年のワイヤボンド技術の向上による所が大である。Next, the operation will be explained. This invention was made possible largely due to improvements in wire bond technology in recent years.

一般的（こ、従来ワイヤボンドできるワイヤ長はワイヤ
径３０μｍで約３ｍが限界であり、その為、パッケージ
のインナーリード近くζこｆＬ極パッドを設けなけれは
ならす、１辺が１０１ｒｌを超えるメモリＩＣは、パッ
ケージ対応で同一機能の電極パッドを複数設けることが
必要でめった。General (Conventionally, the wire length that can be wire bonded is limited to about 3 m with a wire diameter of 30 μm, so it is necessary to provide a ζ fL pole pad near the inner lead of the package. Memory ICs with one side exceeding 101 rl) In this case, it was necessary to provide multiple electrode pads with the same function for each package.

しかしワイヤ径３０μｍで５〜６ｔｎ！のワイヤ長が安
定して性成出来る装置が出現した。However, with a wire diameter of 30 μm, it is 5 to 6 tn! A device has appeared that can produce wires with a stable wire length.

第１図は５（ＪＪ対応で設計さ０た半導体素子α時で、
上記の装置を使用すれば、第２図のＺＩＰの配線が容易
に実現し、また、第３図はＺＩＰ対応で設計された半導
体素子（６）で、上記の装置を使用すれば、第４図のＳ
ＯＪの配線が容易に実現する。Figure 1 shows the case of a semiconductor device α designed to correspond to 5 (JJ).
If the above device is used, the ZIP wiring shown in FIG. S in the diagram
OJ wiring can be easily realized.

更に、従来のＺＩＰのリード長の違いによるインダクタ
ンスのばらつきを抑える為、リード長がほぼ等しくなる
５ＺＩＰ　（Ｓｗａｌｌ　Ｚ　Ｉ　Ｐ　）が考えらｎる
ので、第５図のＳＯＪ対応で設計さｎた半導体素子時も
、と記の装置により、第６図のＺＩＰの配線が容易に実
現できる。Furthermore, in order to suppress variations in inductance due to differences in the lead lengths of conventional ZIPs, we can consider 5ZIPs (Swall Z I P ) in which the lead lengths are almost equal, so the semiconductor designed for SOJ in Figure 5 Even in the case of an element, the ZIP wiring shown in FIG. 6 can be easily realized using the apparatus described below.

なお、上記実施例ではＳＯＪとＺＩＰの二つのパッケー
ジについて示したが、ＳＯＪの代わりにＤ　Ｉ　Ｐ　（
Ｄｕａｌ　　Ｉｎ−１ｉｎｅ　Ｐａｃｋａｇｅ）、Ｓ　
ＯＰ　（ＳｍａｌｌＯｕｔｌｉｎｅ　Ｐａｃｋａｇｅ）
、ＬＩＳＯＰ　（Ｌ］ｌｔ、ｎａ　Ｓｍａｌｌ　０ｕｔ
ｌｉｎｅ　　Ｐａｃｋａｇｅ）でもよく、またＺＩＰの
代わりにＳ　Ｉ　Ｐ　（Ｓｉｎｇｌｅ　　Ｉｎ−１ｉｎ
ｅ　Ｐａｃｋａｇｅ）　、　ＴＳＯＰ　（Ｔｈｉｎ　　
Ｓｍａｌｌ　　０ｕｔｌｉｎｅ　Ｐａｃｋａｇｅ）でも
よい。In the above embodiment, two packages, SOJ and ZIP, were shown, but DIP (DIP) was used instead of SOJ.
Dual In-1ine Package), S
OP (Small Outline Package)
, LISOP (L]lt, na Small 0ut
Line Package) may also be used, and SIP (Single In-1in) may be used instead of ZIP.
ePackage), TSOP (Thin
Small Utline Package) may also be used.

また、金属細線（５）は、一般的にＡｕワイヤであるが
Ｃｕワイヤを使用することで、ワイヤリングできる電極
パッド（３）とインナーリード（４）の距離を長くする
ことができる。Further, the thin metal wire (5) is generally an Au wire, but by using a Cu wire, the distance between the electrode pad (3) and the inner lead (4) that can be wired can be increased.

〔発明の効果〕〔Effect of the invention〕

以上のように、第１の発明によれば、１つのパッケージ
対応で設計された半導体素子でもう１つのパッケージの
組立が出来る為、半導体素子の寸法を抑えることができ
、パッケージによる特性のばらつきや、耐湿性の低下を
防ぐことができる効果がある。As described above, according to the first invention, a semiconductor element designed for one package can be assembled into another package, so the dimensions of the semiconductor element can be suppressed and variations in characteristics depending on the package can be reduced. This has the effect of preventing a decrease in moisture resistance.

さらに第２の発明によれば、リード長を等しくしたＺＩ
Ｐを得るとともに、第１の発明と同様、ＳＯＪ対応で設
計された半導体素子をこのＺＩＰに組立てることにより
、特性の向上を得ら口る効果がある。Furthermore, according to the second invention, ZI with equal lead lengths
In addition to obtaining P, as in the first invention, by assembling a semiconductor element designed for SOJ into this ZIP, it is possible to obtain an improvement in characteristics.

【図面の簡単な説明】[Brief explanation of drawings]

第１図な、いし第４図は第１の発明に係る半導体素子の
実施例を示すもので、第１図は長辺二辺に電極パッドを
設けた半導体素子をＳＯＪに組立てた状況を示す正四図
、第２図は第１図の半導体素子をＺＩＰに組立てた状況
を示す正面図、＠３図は長辺−辺と短辺二辺に電極パッ
ドを設けた半導体素子をＺＩＰに組立てた状況を示す正
面図、第４図は第３図の半導体素子をＳＯＪに組立てた
状況を示す正面図、第５図は第２の発明に係る半導体素
子の実施例を示すもので、第５図は長辺二辺に電極パッ
ドを設けた半導体素子をＳＯＪに組み立てた状況を示す
正面図、第６図は第５図の半導体素子をＺＩＰに組立て
た状況を示す正面図、第７図は従来の半導体素子をＳＯ
Ｊに組立てテコ状況を示す正面図、第８図は第７図の半
導体素子をＺＩＰに組立てた状況を示す正面図である。 図において、（２）はグイパッド、（３）は電極パッド
、（４）はインナーリード、問は金属細線、（ロ）、（
６）、叫は半導体素子である。 なお、図中、同一符号は同一、又は相当部分を示す。 １Ｍ３１！１Figures 1 to 4 show examples of the semiconductor element according to the first invention, and Figure 1 shows a semiconductor element with electrode pads on two long sides assembled into an SOJ. Figure 4 and Figure 2 are front views showing the semiconductor device in Figure 1 assembled in a ZIP, and Figure @3 is a semiconductor device with electrode pads provided on the long side and two short sides assembled in a ZIP. FIG. 4 is a front view showing the situation in which the semiconductor device shown in FIG. 3 is assembled into an SOJ, and FIG. is a front view showing a semiconductor device with electrode pads on two long sides assembled in an SOJ, FIG. 6 is a front view showing a situation in which the semiconductor device in FIG. 5 is assembled in a ZIP, and FIG. 7 is a conventional Semiconductor elements of SO
FIG. 8 is a front view showing the state in which the semiconductor device of FIG. 7 is assembled in a ZIP. In the figure, (2) is the Gui pad, (3) is the electrode pad, (4) is the inner lead, Q is the thin metal wire, (B), (
6) The device is a semiconductor device. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. 1M31!1

Claims (1)

【特許請求の範囲】[Claims] 同一機能の半導体素子を異なる数種類のパッケージに組
立る時、半導体素子の長辺側に設けられた電極パッドを
短辺の対向に配列されたインナーリードに配線するか、
または、短辺側に設けられた電極パッドを長辺の対向に
配列されたインナーリードに配線したことにより、半導
体素子の短辺と長辺の両辺に同一機能の電極パッドを設
けないことを特徴とする半導体装置。When assembling semiconductor elements with the same function into several different types of packages, it is necessary to wire the electrode pads provided on the long side of the semiconductor element to inner leads arranged opposite to the short side.
Another feature is that electrode pads provided on the short side are wired to inner leads arranged opposite to the long side, so that electrode pads with the same function are not provided on both the short and long sides of the semiconductor element. semiconductor device.
JP2032797A 1990-02-13 1990-02-13 Semiconductor device Pending JPH03235339A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2032797A JPH03235339A (en) 1990-02-13 1990-02-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2032797A JPH03235339A (en) 1990-02-13 1990-02-13 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH03235339A true JPH03235339A (en) 1991-10-21

Family

ID=12368840

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2032797A Pending JPH03235339A (en) 1990-02-13 1990-02-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH03235339A (en)

Similar Documents

Publication Publication Date Title
US6297547B1 (en) Mounting multiple semiconductor dies in a package
US6232148B1 (en) Method and apparatus leads-between-chips
US7309915B2 (en) Semiconductor chip having pads with plural junctions for different assembly methods
JPH06283567A (en) Method and apparatus for subjecting lead frame to lead-on-chip type inner lead bonding
JPH04307943A (en) Semiconductor device
US6531761B1 (en) High density direct connect LOC assembly
JP2001156251A (en) Semiconductor device
JPH04221837A (en) Semiconductor device
JPH03235339A (en) Semiconductor device
JPH0783035B2 (en) Semiconductor device
JPH03166755A (en) Lead frame for semiconductor integrated circuit
JPH10275887A (en) Semiconductor device
JPH0582582A (en) Semiconductor device
US6465891B2 (en) Integrated-circuit package with a quick-to-count finger layout design on substrate
JP2879787B2 (en) Semiconductor package for high density surface mounting and semiconductor mounting substrate
JP2896223B2 (en) Resin-sealed semiconductor device
JPS6141246Y2 (en)
JPH0621329A (en) Resin sealed semiconductor device
KR100280393B1 (en) Semiconductor package
JPH04151842A (en) Semiconductor device
US9252115B1 (en) Method for forming semiconductor layout
JP2000058704A (en) Lsi package and method for wiring its inner lead
JPH0327563A (en) Semiconductor device
JPS6081852A (en) Semiconductor device
JPH06204395A (en) Semiconductor device