JPH03234057A - Forming method for semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To realize high integration and high speed operation by employing a double drain structure in a drive MISFET, introducing two types of impurity through a sheet of mask, and forming the gate isolation films of drive and transfer MISFETs independently. CONSTITUTION:A gate electrode 7 is formed through a gate isolation film 6 on the main surface part of the region in a p<->-type well region for forming a drive MISFET Qd and two types of n-type impurities having different diffusion rate are introduced into the main surface part, while being self-aligned to the gate electrode 7, thus forming a drive MISFET Qd having double drain structure. A gate electrode 13 is formed through a gate isolation film 12 on the main surface part of the p<->-type well region for forming a transfer MISFET Qt and an n-type impurities are introduced with low density into the main surface part, while being self-aligned to the gate electrode 13, thus forming a side wall spacer 16 on the side wall of the gate electrode 13 and then an n-type impurities are introduced with high density, while being self-aligned to the side wall spacer 16, thus forming a transfer MISFET Qt of LDD structure.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and in particular, to a semiconductor integrated circuit device.
A M (Static Random Acc
Semiconductor integrated circuit with ess Memory)
It relates to techniques that are effective when applied to devices. [Prior art] SRAM, which is a volatile semiconductor memory device, uses complementary data
Memory cells are arranged at intersections between data lines and word lines. Mail
Morisel has a flip-flop circuit and two transfer MIs.
Consists of SFET. The transfer MISFET is a flip
Connect one semiconductor area to the input/output terminal of the flop circuit
and connect the other semiconductor region to the complementary data line. child
The transfer MISFET has its gate electrode connected to the word line.
This word line controls conduction and non-conduction. flip
The flop circuit is configured as an information storage section and has two drivers.
Consists of a dynamic MISFET and two load resistance elements.
Ru. The driving MISFET is one of the transfer MISFETs.
Connect the drain region to one semiconductor region of
Connect the source region to g (source line). Drive MIS
The gate electrode of the FET is connected to one of the other transfer MISFETs.
connected to the semiconductor region of The load resistive element is
Connect one end to one semiconductor area of the transfer MISFET
and connect the source area to the power supply voltage wiring (source line)
. This type of SRAM memory cell is a driving MISFE
A load resistor element is placed above the T, and the memory cell is occupied.
Since the area can be reduced, the SRAM can be highly integrated. A memory cell can store 1 [bit] of information. SRAM is being used in high density memory for the purpose of increasing the capacity of information.
Accumulation is done. The most suitable technology for this highly integrated SRAM
is described in JP-A-63-193558. this
The technology is that one of the transfer MISFETs on one side of the memory cell.
semiconductor region and the drain region of one driving MISFET
The area is integrated with the area. One transfer MISFET, one
The gate length direction of each driving M I S FET is
matched. Similarly, the other transfer MIS of the memory cell
One semiconductor region of the FET and the other driving MISFET
The drain region of is constructed integrally. Other transfer MI
The SFET is connected to one drive MISFET with its gate width
They are arranged to face each other in the direction. MIS for the other drive
The FET is connected to one of the transfer MISFETs in the gate width direction.
are arranged facing each other. In other words, the memory cell
, one transfer MISFET and drive MISFET,
The other transfer MIS FET and drive MISFE
The planar shapes of T are mutually aligned with respect to the center point between them.
It is composed of a point-symmetric shape. One drive MISFET
The gate electrode has one end extending in the gate width direction and the other end extending in the gate width direction.
One semiconductor region of the transfer MISFET and the other drive region
Connected to the drain region of the active MISFET. similarly
, the gate electrode of the other quick-acting MISFET is at one end.
extends in the gate width direction, and one of the transfer MISFETs
One semiconductor region and one drive MISFET drain
connected to the in area. One drive MISFET, etc.
The gate electrodes of the drive MISFETs have the same conductivity.
Consists of layers (same manufacturing step in the manufacturing process)
. These connection structures constitute a cross-wiring structure within the memory cell.
to be accomplished. MISFET for one transfer, for the other transfer
Each gate electrode of MISFET is made of the same conductive layer.
and a separate upper layer from the gate electrode of the driving MISFET.
(in a separate manufacturing step in the II manufacturing process)
Ru. The word line connected to the memory cell is MISF for transfer.
It is composed of the same conductive layer as the gate electrode of ET, and
Composed in the body. This word line is used between memory cells.
MISFET for memory cell transfer, MISF for drive
It extends in the same direction as the width direction of each gate of the ET. memo
MISFET for transfer on one side of recell, MI for transfer on the other side
Since the SFETs are arranged point-symmetrically with respect to each other, the
The power line crosses the extending direction within the memory cell.
It is routed in the direction in which the gate is inserted (gate length direction). This word line is used for one transfer MISFET and drive
MISFET and the other transfer MISFET and drive M
It extends over the element isolation insulating film between the ISFET and the ISFET. The technology described in this publication is an MI for driving memory cells.
Separate conductive layers for SFET gate electrode and word line
1 and 2 are stacked on top of each other, so the memory cell occupancy is
The available area can be reduced and the SRAM can be highly integrated. [Problem to be solved by the invention] Prior to the development of SRAM, the inventor discovered that the following problems had arisen.
I discovered that (1) The word lines are cross-wired within the memory cell.
One of the gate electrodes of the driving MISFET that constitutes a line structure
Intersects the end extension. However, memory cells
One of the transfer MISFET and drive MISFET
With the other transfer MISFET and drive MISFET
An area for routing the word line is required between them. this
Therefore, the area corresponding to the area where word lines are routed within the memory cell is
SRAM
The degree of integration decreases. (2) Also, the word line extends between memory cells.
The directions and the directions in which they are routed within the memory cells are different. Therefore, the word line extending the memory cell array
Effective length increases, word line resistance increases
Therefore, memory cell information write operation and information read operation
becomes slow, and the operating speed of SRA and M decreases. (3) In addition, the memory cell usually achieves a β ratio.
For the purpose, the drive width is smaller than the gate width of the transfer MISFET.
The gate width of the dynamic MISFET is increased. Mail
Inside the Mori cell, one of the transfer MISFETs and the driver
Active MISFET, other transfer MISFET and drive
The separation dimension in the gate width direction of each MISFET for
MISFE for driving one side and the other side have a large width dimension.
It is determined by the distance between T. In other words, the drive MISF
- one side, the other side corresponds to the difference with the gate width dimension of ET.
Wasted empty space within the distance between each transfer MISFET
area occurs. This increases the area occupied by memory cells.
However, the degree of integration of the SRAM decreases. (4) The memory cell also includes a transfer MISFET,
IF! Separate gate electrodes of each active MISFET
Since it is composed of a conductive layer, the step shape becomes large. This stage
The difference shape is determined by the upper conductive layer, for example, the underlying insulating film of the data line.
It grows as a step shape on the surface. This may cause disconnection or sheet failure in the data line.
The electrical reliability of RAM decreases. (5) Also, the memory cell is a transfer MISFET, M
Separate manufacturing process for each gate electrode of active MISFET
, the overall SRAM manufacturing process increases.
do. The objects of the present invention are as follows. (1) In a semiconductor integrated circuit device having an SRAM,
Our aim is to provide technology that can improve the degree of integration.
Ru. (2) In a semiconductor integrated circuit device having an SRAM,
To provide technology that can increase operating speed.
It's there. (3) In a semiconductor integrated circuit device having an SRAM,
Provide technology that can improve operational reliability
There is a particular thing. (4) In a semiconductor integrated circuit device having an SRAM,
To provide technology that can reduce power consumption
be. (5) In a semiconductor integrated circuit device having an SRAM,
Providing technology that can improve soft error resistance
It's about doing. (6) In a semiconductor integrated circuit device having an SRAM,
To provide technology that can improve electrical reliability.
It's there. (7) In a semiconductor integrated circuit device having an SRAM,
Provide technology that can improve electrostatic breakdown voltage
There is a particular thing. (8) In a semiconductor integrated circuit device having an SRAM,
Technology that can improve yields in manufacturing processes
It is about providing. (9) In a semiconductor integrated circuit device having an SRAM,
Technology that can reduce the number of manufacturing steps in the manufacturing process
Our goal is to provide the following. (10) Two or more of the purposes listed in (1) to (9) above.
To provide technology that can simultaneously achieve the objectives of
It's there. The above and other objects and novel features of the present invention are accomplished by the present invention.
It will become clear from the description of the specification and the attached drawings.
cormorant. [Means for solving the problem] Outline of one typical invention disclosed in this application.
A brief explanation of the main points is as follows. (1) Transfer MISFET and drive MISFET
Semiconductor integrated circuit with SRAM configured with Moricell
In the device formation method, the drive MISFET of the substrate is
A first gate is formed on the main surface of the formation region with a gate insulating film interposed therebetween.
A step of forming a substrate electrode and a MISF for driving the substrate.
An enlarged conductivity type opposite to that of the substrate is provided on the main surface of the ET formation region.
Two types of impurities with different diffusion rates are applied to the first gate electrode.
The driving M of the double drain structure is introduced in self-alignment to the
Process of forming ISFET and MIS for transfer of the substrate
A gate insulating film is interposed on the main surface of the FET formation region.
a step of forming a second gate electrode, and a step for transferring the substrate.
A conductor opposite to the substrate is provided on the main surface of the MISFET formation region.
A low concentration impurity of a type is automatically applied to the second gate electrode.
A step of introducing self-alignment, and a step of introducing on the sidewall of the second gate electrode.
Form a sidewall spacer with self-alignment
and the formation area of the transfer MISFET on the substrate.
A highly concentrated impurity of the opposite conductivity type to the substrate is placed on the main surface of the substrate.
Introduced in self-alignment to the sidewall spacer.
, and the process of forming a transfer MISFET with an LDD structure.
Be prepared. (2) Double drain of the driving M5FET of the means (1)
In the source region of the in-structure, the transfer MI 5FET
The source line formed in the same manufacturing process as the second gate electrode of
Connect. (3) MI for driving with the double drain structure of the means (1)
The step of forming the SFET includes forming the first gate electrode.
After that, the sidewall of this first gate electrode is self-contained.
Form the sidewall spacers by self-alignment, and then
Two types of impurities having different diffusion rates are added to the first gate voltage.
This is a process of introducing self-alignment to the poles. (4) For transferring the LDD structure of the means (1) or (3) above.
In the step of forming the MISFET, the second gate electrode is
After the formation, the low concentration impurity is introduced, and this introduced
After annealing to stretch and diffuse the impurities,
forming the side wall spacer, and then forming the height
This is a process of introducing impurities at a high concentration. (5) Transfer MISFET and software controlled by word line
The memory cell is connected to the drive MISFET connected to the ground line.
Formation of semiconductor integrated circuit device having structured SRAM
In the method, the MISFET for driving the memory cell is
A step of forming a first gate electrode, and a step of forming a first gate electrode.
The second gate of the MISFET for memory cell transfer is in the upper layer of
In addition to forming an electrode, the second gate electrode is formed in the same layer as the second gate electrode.
forming word lines and source lines. (6) The gate electrode of I@dynamic MISFET is the first electrode.
A dielectric film is interposed on this first electrode to store information.
A capacitive element with a second electrode connected to a node is a memory
Semiconductor integrated circuit device having SRAM arranged in cells
In the forming method, the first electrode or the second electrode is made of C.
Deposited by VD method and reduces resistance value during this deposition
It is formed from a polycrystalline silicon film into which impurities are introduced. (7) Use the gate electrode of the driving MISFET as the first electrode.
, an information storage node is formed by interposing a dielectric film on this first electrode.
A capacitive element with a second electrode connected to the memory cell
A shape of a semiconductor integrated circuit device having an SRAM arranged in
In the method, the first electrode or the second electrode is
Polycrystalline silicon deposited by CVD method using carbon as a source gas
Formed by a membrane. (8) Use the gate electrode of the drive MISFET as the first electrode.
, an information storage node is formed by interposing a dielectric film on this first electrode.
A capacitive element with a second electrode connected to the memory cell
A shape of a semiconductor integrated circuit device having an SRAM arranged in
In the formation method, a polycrystalline silicon film deposited by CVD method is used.
a step of forming the first electrode; and a step of forming a CV on the first electrode.
A step of forming a dielectric film using a silicon oxide film deposited by the D method.
Equipped with (9) The first electrode or the second electrode of the means (8) is a CV
Impurities deposited by D method and reducing resistance during this deposition
A polycrystalline silicon film containing a substance or disilane as a source gas
It is formed from a polycrystalline silicon film deposited using the CVD method.
. (10) A first semiconductor region in one semiconductor region of the transfer MISFET.
One semiconductor region of the driving MISFET and the second driving MISFET
The gate electrode of the MISFET is connected to the first drive
The first electrode is the gate electrode of the MISFET, and the first MI for driving is connected to the gate electrode of the MISFET.
Each of the second electrodes is connected to one semiconductor region of the SFET.
It has an SRAM in which a capacitive element is configured as a memory cell.
In the method for forming a semiconductor integrated circuit device, the first drive
MI 5FET and second drive MISFET are formed.
and the gate electrode of the first driving MISFET.
a step of forming a first electrode of a capacitive element; and a step of forming a first electrode of a capacitive element;
One semiconductor region is connected to one semiconductor region of MISFET.
a step of forming connected transfer MISFETs;
A capacitive element is formed by interposing a dielectric film on the first electrode of the capacitive element.
At the same time, a part of this second electrode is used to form a second electrode.
One semiconductor region of the MISFET for data transfer and the second drive region
and a step of connecting gate electrodes of MISFETs. (11) The first electrode or the first electrode of the capacitive element of the means (10)
The two electrodes are deposited by CVD using disilane as the source gas.
polycrystalline silicon film deposited by CVD method and this
Polycrystalline silicon with impurities introduced to reduce resistance during deposition
Formed by a membrane. (12) Gate electrode of MISFET for memory cell transfer
A semiconductor having an SRAM with word lines integrated into the
In a method of forming an integrated circuit device. Formation area of the transfer MISFET of the memory cell on the substrate
The process of forming a gate insulating film on the main surface of the
This film is deposited by CVD on the entire surface of the substrate including the insulating film.
Polycrystalline silicon with impurities introduced to reduce resistance during deposition
The process of forming an elementary film and the substrate including this polycrystalline silicon film
The process of depositing a high melting point metal silicide film on the entire surface and this high melting point
Patterning each of the metal silicide film and the polycrystalline silicon film
The remaining polycrystalline silicon film and high melting point metal silicide film
A gate of the transfer MISFET is formed on the gate insulating film.
Process for forming electrodes and word lines integrally connected to them
Prepare for the process. (13) The transfer MISFET gate of the means (12)
polycrystalline silicon layer below the word line connected to the gate electrode and the word line connected to it.
The elementary film is deposited by CVD using disilane as a source gas.
It will be done. (14) MIS for transfer of the means (12) or (13)
Under the FET gate electrode and the word line connected to it
The polycrystalline silicon film of the layer is 5 [nm1 or more and 100 [n ml
It is formed with the following film thickness. (15) Transfer MISFET and source area are source lines
The memory cell is composed of a driving MISFET connected to
A method for forming a semiconductor integrated circuit device having an SRAM
, on the main surface of the driving MISFET formation region of the substrate.
A first gate electrode is formed on the main surface of the first gate electrode.
forming a bus region and a drain region, and forming a driving MISFET.
and the formation area of the transfer MISFET on the substrate.
The process of forming a gate insulating film on the main surface of the
a step of depositing a silicon film over the entire surface of the substrate including the top insulating film;
the silicon film on the source region of the driving MISFET;
The underlying insulating film is removed one by one to form a connection hole.
and the contacting process is performed on the entire surface of the substrate including the silicon film.
Connected to the source region of the drive MISFET through the through hole.
The process of forming a high melting point metal silicide film and the process of forming a high melting point metal silicide film.
Patterning is applied to each of the silicide film and silicon film in sequence,
A silicon film and a high melting point metal silicide film are formed on the gate insulating film.
and forming a second gate electrode. Source line connected to the source region of the driving MISFET
and a step of forming. (16) Transfer MISFET and drive MISFET
Semiconductor integrated circuit having SRAM in which memory cells are configured
In the method for forming a circuit device, a MISFET for driving a substrate
a step of forming a first gate insulating film on the main surface of the formation region;
Then, a silicon film is formed on the entire surface of the substrate including the first gate insulating film.
Each of the first insulating film and the second insulating film as an oxidation-resistant mask
This step of sequentially forming the second. First insulating film, silicon film
Each pattern is sequentially patterned with substantially the same pattern.
The first gate electrode of the driving MISFET is formed using the silicon film.
A process of forming a sidewall on the sidewall of this first gate electrode.
Process of forming wall spacers and MI for board transfer
A second gate isolation layer is formed on the main surface of the SFET formation region by thermal oxidation.
The process of forming an edge film and the transfer on this second gate insulating film
forming a second gate electrode of the MI 5FET;
Etching is performed on the entire surface of the substrate to form the first gate electrode.
and a step of sequentially removing each of the upper second and first insulating films.
I can do it. (17) The first drive MISFET of the means (16)
The gate electrode is used as the first electrode of the capacitive element, and the gate electrode is used as the first electrode of the capacitor.
On the first gate electrode from which each of the first and second insulating films has been removed
A second electrode of the capacitive element is formed with a dielectric film interposed between the capacitive element and the capacitive element.
It will be done. (18) Drive to one semiconductor region of transfer MISFET
A memory cell to which the gate electrode of MISFET is connected.
Formation of semiconductor integrated circuit device having structured SRAM
In the method, the formation area of the quick-acting MISFET of the substrate is
a first gate electrode on the main surface of the region and a first insulating film on top of the first gate electrode;
and the shape of the transfer MISFET on the substrate.
A second gate electrode is formed on the main surface of the formation region and the second gate electrode is formed on the main surface of the formation region.
While forming a second insulating film that is thicker than the first insulating film,
Then, on the main surface of the transfer MISFET formation region, the above-mentioned
a step of forming one semiconductor region; a first insulator on the first gate electrode of the driving MISFET;
While removing a part of the film, one side of the transfer MISFET
a contact hole that exposes at least a portion of the surface of the semiconductor region of the
and through this connection hole, the transfer M.
One semiconductor region of ISFET, drive MISFET
each of the first gate electrodes is connected to the first and second gate electrodes.
and a step of connecting with a conductive layer formed on the upper layer.
. (19) Drive to one semiconductor region of transfer MISFET
The memory cell to which the gate electrode of MISFET is connected is
and the other of the transfer MISFET of this memory cell.
A semiconductor region that has an SRAM with data lines connected to it.
In the method for forming a conductor integrated circuit device, the driving of the substrate
A first gate electrode is formed on the main surface of the MISFET formation region.
Forming process and formation of the transfer MISFET on the substrate
A second gate layer above the first gate electrode is formed on the main surface of the region.
In addition to forming the gate electrode, the transfer MISFET
The one semiconductor region and the other half are formed on the main surface of the formation region.
The step of forming a conductor region and the step of forming the transfer MISFET.
One semiconductor region, the first gate voltage of the driving MISFET
each of the electrodes is formed in a layer above the first and second gate electrodes;
The same layer as this conductive layer is connected to the
An intermediate conductor is placed on the other semiconductor region of the transfer MISFET.
The process of forming the layer and the process of forming the previous
Connect the data line to the other semiconductor area of the MISFET for data transfer.
and a step of connecting. (20) Drive MISFET and load MISFET
Semiconductor integrated circuit having SRAM in which memory cells are configured
In the method for forming a memory cell of a substrate,
This driving MISFET is placed on the main surface of the region where the driving MISFET is formed.
SFET first gate electrode, source region and drain region
The process of forming the region and the first gate of this driving MISFET.
A dielectric film is interposed on the load electrode to
While forming the second gate electrode of the ET, this second gate electrode is
Connect the top electrode to the drain region of the driving MISFET.
process and the second gate voltage of this MI 5FET for load.
MISFE for this load by interposing a gate insulating film on top.
The channel formation region, source region and drain region of T
and a step of forming. (21) The second load MISFET of the means (20)
The gate electrode was formed using the CVD method using disilane as the source gas.
Polycrystalline silicon film deposited or deposited by CVD method
Polycrystalline with impurities introduced to reduce resistance during this deposition
It is made of silicon film. (22) The channel of the load MISFET of the means (21)
The channel forming area is 5 [nm1 or more and 50 [nm1 or less]
Formed with a film thickness. (23) The gate of the load MISFET of the means (21)
The insulating film is formed of a silicon oxide film deposited by CVD method.
Ru. (24) Load MIS of the means (21) to (23)
The thickness of the FET gate insulating film is 10 [nm1 or more and 50 [nm] or more.
It is formed with a size of 1 nm or less. (25) Upper layer with an interlayer insulating film interposed on the upper layer of the lower layer wiring
Semiconductor integrated circuit device with multilayer wiring structure that forms wiring
In the method for forming a first wiring layer, a first wiring layer, which is a lower wiring layer, is formed on a substrate.
A step of forming each of the lines and the second wiring at predetermined intervals.
Then, the entire surface of the board including this lower layer wiring is coated with tetraethoxy.
Uses plasma CVD method using silane gas as the source gas
However, the distance between the first wiring and the second wiring of this lower layer wiring is
a step of depositing a first silicon oxide film having a thickness of one-half or more;
, spin-on is applied to the entire surface of the substrate including the first silicon oxide film.
A second silicon oxide film is applied using the glass method, and then a second silicon oxide film is applied.
The step of baking the silicon film and the entire surface of this second silicon oxide film
etching is performed on the first wiring and the first wiring of the lower layer wiring.
In addition to removing the second silicon oxide film on the second wiring,
A step of leaving the second silicon oxide film in the region of
The entire surface of the substrate, including the second silicon oxide film, is coated by CVD.
a step of depositing a third silicon oxide film;
removing the third silicon oxide film on the first wiring or the second wiring,
a step of forming a contact hole, and a step of forming a contact hole on the third silicon oxide film;
The upper part is connected to the first wiring or the second wiring through the connection hole.
and a step of forming layer wiring. (26) Element isolation insulating film formed in the non-active region of the substrate
on the main surface within an active area defined by . Memory with MrSFET for transfer and MIS for drive, FET
Semiconductor integrated circuit device having SRAM in which cells are configured
In the method of forming the active region of the substrate, the main surface of the active region forming region is
The planar shape is ring-shaped, spaced apart from each other and regularly.
The process of arranging a plurality of oxidation masks formed in the shape of
on the main surface of the non-active area of the substrate using an oxidation mask of
and a step of forming an element isolation insulating film using a selective oxidation method.
Ru. (27) The oxidation mask of the means (26) is used to activate the substrate.
on the main surface of the region forming region, spaced apart from each other and in the first direction.
A plurality of pieces are arranged in a row at the same pitch, and this arrangement
In the next row in the second direction intersecting the first direction of the row,
at the same pitch in the first direction, and at the same pitch in the first direction.
Shifted by 1/2 pitch from the array, multiple pieces are arranged in a row.
Arranged. (28) The memory cell of the means (27) is for two transfers.
Consists of MISFET and two drive MISFETs
, the ring shape of the oxidation mask is. Two memory cells adjacent in the first direction and these two memory cells
Mori cell and two memory cells adjacent in the second direction, total
in each of the four memory cells. 1 transfer MISFET and 1 drive MISFE
T, total of 4 transfer MISFETs, 4 drive MIs
It is formed in a shape in which SFETs are connected in series. (29) Regular arrangement of the means (26) to (28)
Of the oxidation masks placed at the end of the memory cell array,
The oxide masks to be arranged are formed based on the layout rules.
formed by a portion of the ring shape, and an array is formed at the end of the ring shape.
The oxidation mask is the one where the ring-shaped pattern extends.
The boundary area with the non-active area in the direction is at least bird's beak.
It is formed larger than the corresponding size. [Function] According to the above-mentioned means (1), hot carrier countermeasures are aimed at.
The target is transfer MISFET and drive MISFET.
Compared to the LDD structure (using a total of 4 masks)
In addition, countermeasures against hot carriers and increase in unit conductance are
The drive MISFET has a double drain structure for the purpose of
Since two types of impurities are introduced with one mask,
(Reducing the number of masks by one, using a total of three masks)
. The number of manufacturing steps can be reduced in the SRAM manufacturing process.
Ru. In addition, the gate insulating film of the driving MISFET, the transfer
Separate manufacturing processes are used for each gate insulating film of the transmission MISFET.
The thickness of each gate insulating film can be adjusted independently.
Optimized 0 For example, gate insulation of drive MISFET
The thickness of the film is the same as that of the gate insulating film of the transfer MISFET.
When formed thinner than that, the unit cost of the drive MISFET is
Increase the inductance and increase the β ratio of memory cells
Ru. According to the above-mentioned means (2), this source under the source line
Connect the ground line and the source region of the driving MISFET
Semiconductor area for connection (semiconductor area for extracting reference power supply)
Semiconductor with double drain structure of MIS FET for driving
Since it can be formed in the process of forming the body region, the connection
The manufacturing process of SRAM is equivalent to the process of forming the semiconductor region.
The number of manufacturing steps in the manufacturing process can be reduced. According to the above-mentioned means (3), the sidewall spacer
The half of the driving MISFET is
Reduces the amount of wraparound of the conductor region toward the channel formation region.
Wear. As a result, the gate length of the drive MISFET is
drive MISFET by ensuring and preventing short channel effect.
Since the area occupied by the memory cell can be reduced, the area occupied by the memory cell can be reduced.
Reduce. The degree of integration of SRAM can be improved. According to the above-mentioned means (4), the transfer MISFET
A semiconductor formed by introducing a low concentration of impurities into the LDD structure of
The amount of diffusion toward the channel forming region side of the body region is determined by the annealing process.
It can be increased by adding . As a result, the transfer MISFET
The gate electrode and the half formed by introducing the low concentration impurity.
Increase the amount of overlap (overlap amount) with the conductor area,
The electric field strength generated near the drain region can be weakened.
By reducing the amount of hot carriers generated, MISF for transfer
Reduces the deterioration of threshold voltage of ET over time and improves SRAM
can improve electrical reliability. According to the above-mentioned means (5), for transfer of the memory cell
In the process of forming the second gate electrode of MISFET, the word
Now that we have formed the line and source line. This corresponds to the process of forming word lines and source lines.
, the number of manufacturing steps in the SRAM manufacturing process can be reduced. According to the above-mentioned means (6), after depositing by CVD method,
Compared to polycrystalline silicon films that have lower resistance by introducing impurities,
The surface of the polycrystalline silicon film on the side that contacts the dielectric film, that is, the first
The surface of the electrode or the second electrode can be flattened. As a result, before
Electric field generated between the first electrode and the second electrode of the storage capacitive element
Prevents concentration and improves the dielectric strength of the dielectric film of the capacitive element.
Therefore, the electrical reliability of the SRAM can be improved. Also
, since the dielectric strength of the dielectric film of the capacitive element can be improved.
, by making the dielectric film thinner and reducing the amount of charge accumulated in the capacitive element.
Therefore, the size of the capacitive element can be reduced and the memory cell can be increased.
It is possible to reduce the area occupied by the memory card and improve the degree of SRAM integration.
. Furthermore, the amount of charge accumulated in the capacitive element can be increased.
This improves the stability of information retention in memory cells, and improves the stability of information retention in memory cells.
It can improve the foot error resistance. According to the above-mentioned means (7), it is possible to simply deposit by CVD method.
Compared to polycrystalline silicon film (doped polysilicon),
The surface of the crystalline silicon film that comes into contact with the dielectric film, that is, the first electrode
Alternatively, the surface of the second electrode can be flattened. As a result, the above hand
The same effect as stage (6) can be achieved. According to the above-mentioned means (8), the polycrystalline silicon which is the first electrode
A dielectric material is a silicon oxide film formed by thermal oxidation on the surface of an elementary film.
Compared to forming a film, the surface of the underlying polycrystalline silicon film
Crystal planes of crystal grains (multiple different crystal planes)
exist, and the thermal oxidative growth rate is different for each crystal plane)
A silicon oxide film can be deposited on the dielectric.
Since the thickness of the film can be made uniform, the thickness of the first and second electrodes can be made uniform.
The dielectric breakdown voltage of the dielectric film is increased by preventing the electric field concentration generated between the
The electrical reliability of the SRAM can be improved. Also,
Similar to the effect of the above means (6), the size of the capacitive element can be reduced.
SRA is small and can reduce the area occupied by memory cells.
The degree of integration of M can be improved. It also improves the stability of information retention in memory cells and
It can improve the foot error resistance. According to the above-mentioned means (9), the effect of the above-mentioned means (8) is
In addition, the effect of the above means (6) or (7) is achieved.
I can do it. According to the above-mentioned means (10), the first voltage of the capacitive element is
The pole was formed by the gate electrode of the first driving MISFET.
Then, the amount of SRA corresponding to the step of forming the first electrode is
In addition to reducing the number of manufacturing steps in the M manufacturing process,
In the process of forming the second electrode of the storage capacitor (same as the second electrode)
one semiconductor of the transfer MISFET (using one conductive layer)
Connect the body region and the gate electrode of the second drive MISFET
Therefore, the amount of S required for the process of connecting the two
The number of manufacturing steps in the RAM manufacturing process can be reduced. According to the above-mentioned means (11), the effect of the above-mentioned means (10) is
In addition to the above effects, the effect of the above means (6) or (7) is achieved.
be able to. According to the above-mentioned means (12), the transfer MISFE
The polycrystalline silicon film below the gate electrode of T is contaminated with impurities during deposition.
The thermal diffusion process of P after deposition was abolished and this thermal diffusion process was introduced.
Phosphorous glass film formed on the surface of polycrystalline silicon film by scattering process
Since we have abolished the use of boiling acid for the removal of
Depositing the film quality of a polycrystalline silicon film into which impurities are introduced during deposition.
Dense compared to polycrystalline silicon film, where no impurities are introduced during deposition.
Since the polycrystalline silicon film can be formed in
Deterioration of the dielectric strength voltage of the gate insulating film due to crowding can be reduced.
. As a result, the resistance value is reduced and the operating speed of SRAM is increased.
Polycrystalline silicon in the lower layer of a two-layer word line for speed-up
The film thickness of the base film is reduced to about half (about half), and the
Since the overall film thickness of the word line can be reduced,
The flatness of the underlying surface of conductive layers (e.g. data lines) placed on
It can be used as a carrier. According to the above-mentioned means (13), the gate of the polycrystalline silicon film is
The surface of the gate insulating film side is flattened, and the contact between the substrate and gate electrode is
Since it is possible to prevent electric field concentration from occurring between
Reduces deterioration of dielectric strength voltage of gate insulating film of MISFET
can. According to the above-mentioned means (14), the transfer MISFE
It is possible to reduce the thickness of the gate electrode of T, and also to reduce the thickness of the gate electrode.
Deterioration of dielectric strength voltage of the insulating film can be reduced. According to the above-mentioned means (15), the transfer MISFE
After forming the gate insulating film of T,
A silicon film (lower layer of the second gate electrode) is formed directly on the
After that, the silicon film and the underlying insulating film are removed and the silicon film is driven.
Forming a connection hole on the surface of the source region of an active MISFET
Therefore, a photoresist mask is used to form this connection hole.
does not directly touch the gate insulating film of the transfer MISFET,
Dielectric strength voltage of gate insulating film of MISFET for transfer due to contamination, etc.
deterioration can be reduced. According to the above-mentioned means (16), the driving MI 5F
Oxidation of the corner part of the first gate electrode of ET compared to the surface part
Based on the phenomenon that the speed is slow, the second gate insulating film is formed.
The first gate electrode of the driving MISFET is
The phenomenon of the end portion turning up can be prevented by using the first gate electrode on the first gate electrode.
Since it can be reduced with an insulating film, the second gate electrode on the first gate electrode
The thickness of the insulating film can be made uniform, and this second insulating film removal process
The amount of etching can be reduced. Further, the second insulating film
In the removal process, the first insulating film on the first gate electrode is removed.
Used as an etching stopper film to prevent insufficient etching.
Etching controllability as excessive etching can be reduced
can be improved. Further, the second gate insulating film is formed.
In the thermal oxidation process, the first insulating film on the first gate electrode is
Used as a heat-resistant oxidation mask to cover the surface of the first gate electrode.
Since the growth of crystal grains in the surface silicon film can be reduced, the first
The surface of the base electrode can be made flat. According to the above-mentioned means (17), the first voltage of the capacitive element is
During the thermal oxidation process, the surface of the first gate electrode, which is the pole,
Since it is covered with the first insulating film and the surface is flattened, the capacitance is
The electric field concentration generated between the first and second electrodes of the element is
The dielectric strength of the dielectric film of the capacitive element can be improved. According to the above-mentioned means (18), the driving MISFE
Compared to the film thickness of the first insulating film on the first gate electrode of T.
The second insulating film on the second gate electrode of the sending MI 5FET
The film is formed thickly, and the second gate is formed when forming the connection hole.
Since the second insulating film was left on the gate electrode, the second gate electrode
This prevents short circuits between the electrode and the conductive layer, and improves the manufacturing process.
The yield can be improved. According to the above-mentioned means (19), the transfer MISFE
One semiconductor region of T and the first gate of the driving MISFET
In the step of forming a conductive layer connecting the
Since a conductive layer can be formed, the process for forming this intermediate conductive layer is
The number of manufacturing steps in the SRAM manufacturing process is equivalent to
can be reduced. According to the above-mentioned means (20), the driving MISFE
In the process of forming the first gate electrode of T,
The first electrode of the capacitive element inserted into the MI 5FE for load
In the process of forming the second gate electrode of the capacitive element,
Since each of the two electrodes can be formed, the capacitive element can be formed easily.
The manufacturing process of SRAM is equivalent to the process of
The number of degrees can be reduced. Further, the MI for driving the memory cell
On the SFET, the load MISFET, the husband of the capacitive element
Since I have superimposed the
Reduces the area occupied by recells and improves the degree of SRAM integration.
Wear. According to the above-mentioned means (21), after depositing by CVD method,
Compared to polycrystalline silicon films, which have lower resistance by introducing impurities into
, the surface of the polycrystalline silicon film in contact with the gate insulating film.
flatten the surface of the second gate electrode or channel forming region.
can. As a result. The second gate electrode and channel shape of the load MISFET
electric field concentration generated between the source region (or source region).
This prevents negative
The thickness of the gate insulating film of load MISFET can be reduced.
. Thinner gate insulating film of load MIS FET
, electrical characteristics such as ON characteristics can be improved. According to the above-mentioned means (22), the load MISFE
Leakage current in the T channel formation region can be significantly reduced.
, the voltage supplied from the power supply to the information storage node of the memory cell.
Battery backup is possible because the amount of useless current can be reduced.
The amount of standby current of SRAM using this method can be reduced.
Ru. According to the above-mentioned means (23), the load MISFE
Flatten the surface of the gate insulating film side of the second gate electrode of T.
The dielectric breakdown voltage of the gate insulating film can be improved.
The thickness of the insulating film can be reduced. As a result, M for load
The electrical characteristics of ISFET can be improved. According to the above-mentioned means (24), the load MISFE
Since the thickness of the T gate insulating film has been reduced, the load MI
The electrical characteristics of SFET can be improved. According to the above-mentioned means (25), the first silicon oxide film
By making the film thickness uniform in flat parts and stepped parts,
The first silicon oxide film is formed in the region between the wiring and the second wiring.
Since the occurrence of nests based on the overhang shape can be reduced,
Penetration of cavities when etching the entire surface of the second silicon oxide film
Reduces insulation defects in interlayer dielectric films, such as prevention, and improves semiconductor integrated circuits.
The yield in the manufacturing process of road devices can be improved. Also,
The second silicon oxide film eliminates the steep slopes on the surface of the first silicon oxide film.
Easing the step shape and flattening the surface of the third silicon oxide film
This reduces disconnection defects in upper layer wiring and improves semiconductor integrated circuits.
The yield in the manufacturing process of road devices can be improved. Also,
The entire surface area is provided in the connection hole between the lower layer wiring and the upper layer wiring.
Since the second silicon oxide film does not remain due to tucking, this second silicon oxide film does not remain.
Prevents corrosion of upper layer wiring due to moisture contained in silicon oxide film.
and improve the yield in the manufacturing process of semiconductor integrated circuit devices.
You can improve. Further, the lower layer of the second silicon oxide film is coated with the first acid.
The upper layer of the silicon oxide film is covered with a second silicon oxide film.
Reduces moisture absorption in the base film and improves the film quality of the second silicon oxide film.
It can be used to prevent cracks in the second silicon oxide film, etc.
Yields in the manufacturing process of integrated circuit devices can be improved. According to the above-mentioned means (26), the planar shape is a ring.
The oxide mask formed by the shape separates the active area and non-active area.
The boundary area is a ring-shaped inner frame side and an outer frame side facing each other.
It exists on the frame side, and element isolation is performed in this boundary area using selective oxidation.
Activation based on the generation of bird's beak when forming an insulating film
The ring shape of the oxide mask reduces the area occupied by the
The direction in which the pattern other than the inner frame side and outer frame side extends
indicates that the pattern is closed, i.e., the pattern has no termination and the previous
Based on the occurrence of bird's beak, since there is no boundary area
Therefore, the area occupied by the active region decreases less;
However, in the SRAM manufacturing process, the active region
The amount of turn dimension conversion can be reduced. According to the above-mentioned means (27), the arrangement of the oxidation mask
are arranged in a staggered manner, and in each of the first direction and the second direction.
Uniform and minimize the separation between adjacent oxide masks
The arrangement density of the oxide mask can be increased.
. In other words, the area occupied by the element isolation insulating film between the oxidation masks
Reduce the product. The degree of integration of SRAM can be improved. According to the above-mentioned means (28), the first direction and the second direction
Out of a total of four memory cells adjacent to each direction, four
transfer MISFET and four drive MISFETs,
One semiconductor region of each of a total of eight MISFETs is
is formed integrally with the other semiconductor region of the MISFET, and
Can be used for both purposes. As a result, the memory area corresponding to the dual-purpose semiconductor area is
Reduces the area occupied by recells and improves the degree of SRAM integration.
Wear. According to the above-mentioned means (29), the memory cell array
A margin dimension is formed in advance on the oxide mask arranged at the end of the
Therefore, in the SRAM manufacturing process, the memory cell
The active area in the center of the memory cell array and the end of the memory cell array.
Reduces the difference in pattern dimension conversion between the edge active area and the active area.
Wear. In other words, within the memory cell array (center and
(including
, the electrical reliability of SRAM can be improved. Below is a memo of the complete CMO5 structure regarding the configuration of the present invention.
An implementation in which the present invention is applied to an SRAM configured with recells
Explain with examples. Note that all the figures for explaining the embodiments have the same functions.
Those with the same symbol are given the same symbol, and the repeated explanation is as follows.
Omitted. [Embodiment of the Invention] The overall schematic configuration of an SRAM that is an embodiment of the present invention will be described below.
31i! It is shown as I (chip layout diagram). SRAM (semiconductor pellet) 1 shown in Fig. 3 is 512
[Kbit] X 8 [bit] 4[
It has a large capacity of MMt]. This SRAM1 is
Although not shown, the two sides where the leads face each other, such as DIP, SOJ, etc.
Resin sealing that adopts a dual in-line system arranged in
It is sealed with a sealed semiconductor device. The planar shape of SRAM1 is
Consists of a slim rectangular shape. For example, SRAMI has a rectangular shape with long sides of 17 mm and short sides.
The side consists of 7 mm. Along the mutually opposing long sides of the rectangular shape of the SRAMI
Each peripheral area has multiple external terminals (pounding
Pad) BP is placed. This external terminal BP is
Connected to the lead (inner lead). multiple external
Each of the terminals BP has an address signal, a chip selector, etc.
output enable signal, write enable signal,
Bull signal. Each of the input and output data signals is applied. Also, external terminal
Power supply voltage Vcc and reference voltage Vss are applied to BP.
be done. The power supply voltage Vcc is, for example, the operating voltage of the circuit 5 [V
], the reference voltage Vss is, for example, the circuit ground voltage 0 [V].
be. There are four memory blocks LMB in the center of SRAMI.
Placed. Each of these four memory blocks LMB is
Along the long side of the rectangular shape of SRAMI (left side in Figure 3)
(in column direction) from the short side to the right short side. Each of the four memory blocks LMB is as shown in FIG.
It is divided into four memory blocks MB. This 4
The memory block MB divided into memory blocks L
They are arranged in columns within the MB. In Figure 3, four memory blocks LMB of SRAMI
A load circuit LOAD is arranged above each of the two. 4 pieces
There is a Y decoder circuit on the bottom side of each memory block LMB.
YDEC, Y switch circuit y-sw, sense amplifier circuit
Each road SA is arranged. 4 memory blocks LM
Of B, 2 located on the left side of the rectangular shape of SRAM1
There is an X decoder circuit XDE between the memory blocks LMB.
C is placed. Similarly, the two notes placed on the right side
An X decoder circuit XDEC is placed between the reblock LMB.
be done. Among the four memory blocks LMB, SRAMI
On the right side of the memory block LMB located on the rightmost side,
A redundant circuit SMB is arranged. A memory block obtained by dividing the memory block LMB into four parts.
Each block MB is shown in Figure 4 (enlarged block diagram of main parts).
It is composed of four memory cell arrays MAY as shown in FIG.
. Each of these four memory cell arrays MAY has a memory block.
They are arranged in the column direction in the lock MB. In other words, S.R.
AM1 connects each of the four memory blocks LMB to four
Divide into memory blocks MB, and divide these four memory blocks into MB.
Each block MB is configured with four memory cell arrays MAY.
Therefore, a total of 64 memory cell arrays MAY be arranged.
do. This 64 memory cell array MAY is arranged in the column direction.
Arranged. The one memory cell array MAY is shown in FIG.
4 more memory cells as shown in the large block diagram)
It is divided into array SMAY. This four-part menu
Each of the Mori cell arrays SMAY is arranged in a column direction. The memory cell array SMAY is arranged in the column direction (word line extending direction).
) consists of 16 memory cells MC. In other words, one memory cell array MAY has one memory cell array in the column direction.
4 memory cell arrays with 6 memory cells MC arranged
In total, 64 pieces (64 [bi
t]) memory cells MC are arranged. Also, one note
The recell array MAY operates in the row direction (the direction in which the complementary data lines extend).
1028 (1028 [bitl)] memory cells in
Arrange the MCs. 1028 menus arranged in row direction
Of Morisel MC, 1024 pieces (1024[bit]
) are configured as regular memory cells MC, and four (4[b
it]) is configured as a redundant memory cell MC.
. As shown in FIG. 4, the left side in the memory block MB
2 memory cell arrays MAY and 2 memories on the right side
A word decoder circuit WDE is connected between the cell array MAY and the cell array MAY.
C is placed. Placed on the left side of SRAMI shown in Figure 3
2 memory blocks LMB, totaling 8 memories
The word decoder circuit WDEC of block MB is
X decoder circuit arranged between memory blocks LMB
Selected by path XDEC. Similarly, 2 placed on the right side
memory blocks LMB, total of 8 memory blocks
MB's word decoder circuit WDEC uses these two notes.
X decoder circuit XDE placed between rib blocks LMB
Selected by C. In other words, one X decoder circuit XDE
C is a total of 8 word decodes of 8 memory blocks MB.
select one of the reader circuits WDEC. As shown in Figure 6, the word decoder circuit WDEC is
in the X decoder circuit XDEC via the inword line MWL.
selected. Also, the word decoder circuit WDEC is
It is selected by address signal lines AL arranged respectively. Said
The main word line MWL runs on the memory cell array MAY.
4 (4 [bit]) memory cells extending in the column direction
A plurality of them are arranged in the row direction for each MC. In other words, the main
The code line MWL is in one memory block MB.
Two mem- bers placed on the right side of the word decoder circuit WDC
512 memory cells MC1 left of Mori cell array MAY
512 of two memory cell arrays MAY arranged on the side
memory cells MC1 total 1024 memory cells MC
Select. The address signal line AL extends in the row direction,
Multiple pieces are arranged in the column direction. The address signal line AL is
In the moly block MB, the word decoder circuit WDE
of the two memory cell arrays MAY placed on the right side of C.
Eight lines are placed on the left side to select memory cells MC.
Two memories arranged in two memory cell arrays MAY
8 to select memory cell MC of recell array MAY
A total of 16 books are arranged. As shown in FIGS. 4 and 6, the memory block M
In B, the word decoder circuit WDEC has four mem- bers.
One memory cell array among the memory cell arrays MAY
A first word line WLI and a second word line MAY extend on
Select line WL2. The first word line WLI and the second word line WL2 are memory cells.
For each memory cell array MAY (every 4 memory cell arrays SMAY)
). First word line WL1, second word line W
L2 are spaced apart from each other and run substantially parallel in the column direction.
extends to This first word line WLI and the second word line
WL2 is for each memory cell MC arranged in the row direction.
Placed. In other words, one memory cell MC has the same selection.
The two word lines WLI and the second word line WLI to which the selection signal is applied
6 word line WL2 extends 2 arranged on the right side of the word decoder circuit WDEC
of the memory cell array MAY, the word decoder circuit
The first memory cell array MAY extending on the WDEC side
The word line WLI and the second word line WL2 are connected to the second subword line WLI and the second word line WL2.
Selected by word decoder circuit WDEC via code 1sWL2
selected. Notes apart from word decoder circuit WDEC
A first word line WLI extending the recell array MAY and
The second word line WL2 is connected to the first sub-word line 5WL1.
and is selected by the word decoder circuit WDEC. 1st sub
Each of the word line 5WLI and the second sub-word line 5WL2 is
They are spaced apart from each other and extend parallel to each other in the column direction. 1st sub
The word line 5WLI and the second sub-word line 5WL2 are
Similarly to the first word line WLI and second word line WL2.
, arranged for each memory cell MC arranged in the row direction.
It will be done. The first sub-word line 5WL1 corresponds to one memory.
extends over the cell array MAY and connects to other memory cell arrays.
The first word line WL1 and the second word line
Connect the word decoder circuit WDEC to the word decoder circuit WDEC.
. Two pieces placed on the left side of the word decoder circuit WDEC
Similarly to the right side, each of the memory cell arrays MAY has a first
A word line WL1 and a second word line WL2 are arranged. The first word line WLI and the second word line WL2 are connected to the first word line WLI and the second word line WL2.
Subword line 5WLI or second subword 1sWL2
It is connected to the word decoder circuit WDEC via the word decoder circuit WDEC. In addition
, the present invention provides that the length of the second subword 1iASWL2 is
Since it is shorter than 1 subword 1IAsWL1, this
The second sub-word line 5WL2 is abolished and the first word line WLI
and the second word line WL2 is directly connected to the word decoder circuit WD.
It may also be connected to EC. As shown in FIG. 4, in the memory block MB
, on the upper side of each of the four memory cell arrays MAY.
A divided load circuit LOAD is arranged for each. 4 pieces
Under each of the memory cell arrays MAY, there are
Divided Y decoder circuit YDEC and Y switch circuit y
-sw is placed. In addition, four memory cell arrays M
Under each of AY, there is a sense amplifier divided into each
A circuit SA is arranged. This sense amplifier circuit SA is
Four are arranged for one memory cell array MAY,
4 [bitl information can be output at once. A controller is provided below the word decoder circuit WDEC.
A loop circuit CC is arranged. Also, the memory block shown in Figure 4
In lock MB, the left side of word decoder circuit WDEC
Two memory cell arrays M arranged on the side and right side, respectively.
Although not shown, between AY and memory cell array MAY,
Connecting cells are placed to connect the two. As shown in the fourth time and FIG. 6, the memory block M
In B, the memory cell array MAY contains complementary data.
A line DL is placed. The complementary data line DL is connected to the
word line MWL, sub word line SWL, word line WL
in the row direction that intersects (substantially perpendicular to) the respective extension directions of
extend. Complementary data lines DL are spaced apart and parallel to each other.
A first data line DLL and a second data line extending in the row direction.
It is composed of two lines DL2. This complementary data line DL
As shown in FIG. 6, the memory cells are arranged in columns.
It is arranged for each MC. The upper side of the complementary data line DL
The end side is connected to a load circuit LOAD circuit. complementary de
The other end of the lower side of the data line DL is the Y switch circuit y-sw times.
It is connected to the sense amplifier circuit SA via a line. The memory block LMB of SRAMI shown in FIG.
In the redundant circuit SMB located on the right side. As shown in Figure 5 (enlarged block diagram of main parts),
A Mori cell array MAYS is arranged. This redundant memo
The recell array MAYS includes the above-mentioned memory cell array MAYS.
Memory cell with the same structure as memory cell MC arranged in Y
A plurality of MCs are arranged. Although not limited to this, redundant memory cell array MAY
S has 32 (32[bitl) memory cells in the column direction.
MCs are arranged in one row direction (1028 [bi
tl) memory cells MC are arranged. The fifth redundant memory cell array MAYS is located above the redundant memory cell array MAYS.
A redundant load circuit LOAD is arranged as shown in the figure.
. A redundant memory cell array is installed on the left side of the redundant memory cell array MAYS.
A code decoder circuit WDEC8 is arranged. Redundant memo
Redundant Y switch circuit on the bottom of the recell array MAYS
y-sw is placed. Memory cells M arranged in the memory cell array MAY
C is connected to the word line WL as shown in FIG. 7 (circuit diagram).
It is arranged at the intersection with the complementary data line DL. In other words,
Memory cell MC is connected to the first word line WLI and the second word line
WL2, first data line DLL and second data 4! DL2
located at the intersection with Memory cell MC is a flip
drop circuit and two transfer MISFETs Qtl and Qt
It consists of 2. Flip-flop circuit is an information storage section
This memory cell MC is configured as 1 [bit]
tt 1 + or at On information is stored. Two transfer MISFETs Qt1 of the memory cell MC
．． Each of Qt2 is a pair of input and output of a flip-flop circuit.
One semiconductor region is connected to each of the terminals. MI for transfer
The other semiconductor region of SFETQtl is connected to the data line DLL.
connected, and the gate electrode is connected to the first word line WLI.
Ru. The other semiconductor region of transfer MISFETQt2 is
data line DL2, and the gate electrode is connected to the second word line W.
Connected to L2. These two transfer MISFEETQ
Each of tl and Qt2 is an n-channel type. The flip-flop circuit includes two driving MISFETs.
Qd1 and Qd2 and two load MISFETs Qpl and
and Qp2. Drive MISFETQd1.
Each of Qd2 is configured as an n-channel type. MI for load
SFETQp1. Each of Qp2 is composed of P channel type.
It will be done. In other words, the memory cell MC of SRAMI in this embodiment
is composed of a completely 0MO5 structure. The drive MISFETQd1, the load MISFETQ
p1 connects each other's drain regions and connects each other's drain regions.
The two gate electrodes are connected to form a CMOS. similarly
, drive MI 5FETQd 2, load MISFET
Qp2 connects each other's drain regions and connects each other's drain regions.
The two gate electrodes are connected to form the CMO8. For driving
MISFETQd1 and load MISFETQpl, respectively.
The drain region (input/output terminal) of the transfer MISFET
Connected to one semiconductor region of Qt1 and used for driving
MISFETQd2, husband of MI5FETQp2 for load
connected to each gate electrode. Drive MISFETQd
2. Each drain region of load MISFET Qp2 (
input/output terminal) is one half of the transfer MISFET Qt2.
It is connected to the conductor region and also includes a driving MISFETQd.
1. Each game of MISF E T Q p 1 for load
connected to the ground electrode. Source regions of drive MISFETs Qd1 and Qd2
is connected to a reference voltage Vss (eg, O[V]). negative
The source regions of the load MISFETs Qpl and Qp2 are
It is connected to the power supply voltage Vcc (for example, 5 [V]). A pair of inputs of the flip-flop circuit of the memory cell MC
There is no capacity between the output terminals, that is, between the two information storage node areas.
A quantum element C is configured. Capacitive element C has one electrode connected to
The information storage node area of one electrode is connected to the information storage node area of the other side.
Connect each to the product node area. This capacitive element C is basically
Specifically, by increasing the amount of charge accumulated in the information storage node region,
Constructed for the purpose of increasing soft error resistance. Also, capacity
The quantum element C connects each electrode to two information storage node regions.
Since each of the two information storage node areas is connected between
Approximately half the cost compared to configuring two capacitive elements independently.
It can be constructed from the plane product of minutes. In other words, this capacitive element C is
, since the area occupied by memory cells MC can be reduced, SRA
The degree of integration of M1 can be improved. SRAMI configured in this way is shown in FIGS. 3 and 4 above.
As shown in Figures and Figure 6, the X decoder circuit XDEC
of memory block LMB via main word line MWL.
Word decoding arranged in multiple memory blocks MB
Select one of the circuits WDEC and select this selected
Memory cell array MAY be used in word decoder circuit MWDEC
Select the first word line WLI and the 27th word line gWL2.
RU, Tsumari, SRAM11*, 1st word! WLI and
and the second word line WL2 is divided into a plurality of parts in its extending direction,
One set of first word lines WL among the plurality of divided
I and the 27th node 1WL2 are connected to the word decoder circuit WDE.
C and X decoder circuit XDEC selects the divider
Adopts a backward line method. In addition, SRAMI is as shown in Figures 4 and 6 above.
is arranged at one end side of the word decoder circuit WDEC.
Extend one of the two memory cell arrays MAY
The first word line WLI and the second word line WL2 are
Word decoder circuit WD via sub word line 5WL2
Connect to EC and extend the other memory cell array MAY
The first word line WLI and the 27th word line JIIWL2 are
Word decoder circuit W via 1 sub-word line 5WL1
Connect to DEC. In other words, SRAMI is a memory cell
Word lines WL and segments divided into arrays MAY
Sub-word that connects multiple divided word lines WL
Adopts a double word line method for arranging line SWL.
Ru. In this way, (A to 9) are arranged in memory cell array MAY.
The memory cell MC connected to the
In the SRAMI selected by the coder circuit XDEC,
X decoder circuit XDEC and this X decoder circuit XDE
connected to C via the main word line MWL and selected.
selected, arranged in the extending direction of the main word line MWL
word decoder circuit WDEC and this word decoder circuit WDEC.
The first word line WL (WLI and W
L2) or second sub-word line 5WL2,
connected with each of the first word lines WL interposed in sequence.
A first memory cell in which selected memory cells MC are arranged.
array MAY, and the word decoder circuit WDEC.
a first word line on the first memory cell array MAY;
WL or extends in the same direction as the second sub-word line 5WL2.
The first sub-word line 5WL1. Second word line WL
(WLI and WL2) are connected sequentially.
and a second memory in which selected memory cells MC are arranged.
A cell array MAY is provided. With this configuration, the X
Word decoder circuit selected by decoder circuit XDEC
of the first memory cell array MAY connected to the path WDEC.
of the first word line WL or the second memory cell array MAY.
A device that selects (starts up) only the second word line WL
Since we adopted the deadword line method, this selected
By reducing the charging and discharging flow rate of word line WL, SRAMI
Achieves lower power consumption. In addition to this effect, the water
The first memory cell selected by the code decoder circuit WDEC
The first word line WL of the array MAY, the second memory cell
Each of the second word lines WL of the ray MAY is connected to a memory cell
It is divided into each ray MAY, and the first word line WL, the second word line
The length of each of the word lines WL is shortened and each of them is made into a subword.
Connected to word decoder circuit WDEC via line SWL
Adopting a double word line method, sub-word line
The word decoder circuit WDE corresponds to the code 1isWL.
C and the word line WL to reduce the resistance value between the selected
Increase the charging and discharging speed of the word line WL to increase the operating speed of SRAM1.
speed up. In the peripheral area of the memory cell array MAY of the SRAM1
Arranged X decoder circuit XDEC, Y decoder circuit Y
DEC, Y switch circuit y-sw, sense amplifier circuit S
A, load circuit LOAD, etc. constitute peripheral circuits. this
The peripheral circuit performs information write operation of memory cell MC,
Controls holding operations, information reading operations, etc. The external terminal BP of the SRAM1 and the input stage of the peripheral @path
A static electricity damage prevention circuit is installed between the circuit and the output stage circuit.
is placed. The configuration of the input stage side of SRAMI is shown in Figure 8 (
The configuration of the output stage side is shown in Figure 9 (equivalent circuit diagram).
) are shown respectively. As shown in FIG. 8, on the input stage side of SRAM1,
Between external terminal (external terminal for input) BP and input stage circuit ■
An electrostatic breakdown prevention circuit I is arranged. Input stage circuit■
are n-channel MISFET and p-channel MISFET
It is composed of a CMOS inverter circuit INC formed by
Ru. The electrostatic breakdown prevention circuit l includes the protective resistance element R and the clamp.
It is composed of MISFETQnl for tap. The protective resistance element
The child R is connected in series between the external terminal BP and the input stage circuit ■.
inserted. MISFETQnl for clamp is n-channel
It consists of two MISFETs. MISF for this clamp
ETQnl is each of the protective resistance element R1 input stage circuit H.
Connect the drain regions between them, the gate electrode, and the source.
Each of the regions is connected to a reference voltage Vss. electrostatic
The gas breakdown prevention circuit I protects against excessive current input to the external terminal BP.
It blunts the current and absorbs it to the reference voltage Vss side, and input
Static electricity damage to the stage circuit ■ can be prevented. As shown in FIG. 9, on the output stage side of SRAM1,
Between external terminal (external terminal for output) BP and output stage circuit ■
An electrostatic breakdown prevention circuit (■) is installed. Output stage circuit ■
are output n-channel MISFETQn2, Qn3
, resistance element R, n-channel MISFETQn6, CMO
Consists of S inverter circuit 0UTC. Output stage circuit ■
Drain region of output n-channel MISFETQn2
, Qn3 are connected to the external terminal BP.
Ru. Output n-channel M I S F E T Q n
The gate electrode of No. 2 is the input/output data signal D, and the source region is the
Each of the reference voltages Vss is applied. n channel for output
The gate electrode of MISFETQn3 is connected to the input/output data signal D.
, and the drain regions are applied with power supply voltage Vcc, respectively. The drain region of this output n-channel MISFETQn2
A resistor element connected in series is connected to the region and the source region of Qn3.
n-channel MISFET Qn6 connected in parallel with child R1
The CMOS inverter circuit ○UTC is
The connected 6n channel MISFETQn6 is connected to the drain
The input region is connected to the output n-channel MISFETQn2.
Connected to the rain region and the source region of Qn3, and connected to the gate voltage.
The pole and source regions are each connected to a reference voltage Vss. Silence
Electric breakdown prevention circuit ■ is MISFETQn4 for clamp
, Q n 5 and bipolar transistor BiT
be done. MIS for clamping this electrostatic breakdown prevention circuit■
Each of FETQn4 and Qn5 is composed of an n-channel type.
Ru. The drain region of MISFETQn4 for clamping and
The source region of Qn5 is the external terminal BP and the output stage circuit ■.
The drain region and
and Qn3 source regions, respectively.
Connected. Gate voltage of MISFETQn4 for clamp
Each of the pole and source regions is connected to a reference voltage Vss. Gate of M I S F E T Q n5 for clamp
The electrode is at the reference voltage Vss, and the drain region is at the power supply voltage Vc.
c. Bipolar transistor BiT
It is composed of npn type. bipolar transistor BiT
The emitter area is the external terminal BP, the clamp MIS
Drain region of F E T Q n 4 and Q n
5 source regions and connected to each other.
. An input/output data signal is applied to the base region. workman
A power supply voltage Vcc is connected to the transmitter region. This electrostatic
The gas breakdown prevention circuit ■ protects against excessive current input to the external terminal BP.
Absorb the current to the reference voltage Vss side or the power supply voltage Vce side.
, electrostatic damage to the output stage circuit ■ can be prevented. Next, the memory cell MC and memory cell of the SRAMI
The specific structure of array MAY will be explained. Memories
The planar structure of the completed LeMC is shown in Figure 2 (plan view).
The planar structure of each manufacturing process during the manufacturing process is shown in Figures 10 to 10.
Completion of memory cells MC shown in FIG. 14 (plan view)
The cross-sectional structure of the state is shown in Figure 1 (cut along the I-1 cutting line in Figure 2).
Also, in the memory cell array MAY
Stay. Planar structure of layers formed at each manufacturing step during the manufacturing process
are shown in FIGS. 15 to 20 (plan views). As shown in Figures 1 and 2, SRAMI is made of single crystal silicon.
It is composed of an n" type semiconductor substrate 1 consisting of an element.
A P-type well is formed on the main surface of a part of the semiconductor substrate 1.
Area 2 is configured. Other areas of n-type semiconductor substrate processing
An n-type well region 3 is formed on the main surface (Fig. 21).
reference). The p-type well region 2 is an n-channel MIS
FETQn formation area, that is, memory cell array
In the MAY formation area and some areas of the peripheral circuit,
will be accomplished. The n-type well region 3 is a p-channel MISFE
structure in the TQP formation area, that is, in other areas of the peripheral circuit.
will be accomplished. On the main surface of the non-active region of the p-type well region 2, there is a device.
An isolation insulating film (field oxide film) 4 is formed. Also
, the main surface of the inactive region of the p-type well region 2, that is, the element
A p-type channel stopper region 5 is constructed under the child isolation insulating film 4.
will be accomplished. Similarly, in the non-active region of the n-type well region 3,
An element isolation insulating film 4 is formed on the main surface (see Figure 21).
), the main surface of the inactive region of the π-type well region 3 is P゛
Compared to type well region 2, an inversion region is less likely to occur and the element
Separation is ensured, which simplifies the manufacturing process.
Therefore, basically no channel stopper region is provided. One memory cell MC of the SRAM1 is a p type well.
It is formed on the main surface of the active region of region 2. memory cell MC
Among them, the husbands of two drive MISFETs Qd1 and Qd2
as shown in Figures 1, 2, 10 and 16.
In the area defined around the element by the insulating film 4.
, is formed on the main surface of the p-type well region 2. Drive
Each of the dynamic MISFETs Qd1 and Qd2 is mainly p-
Type well region 2, gate insulating film 6, gate electrode 7, source
It consists of a source region and a drain region. Each of the drive MISFETs Qd1 and Qd2 has a gate
The length (Lg) direction and the column direction (the extending direction of the word line WL or
X direction). The element isolation insulating film 4 (and P-type channel stopper region
6) is mainly the husband of this drive MISFET Qd1 and Qd2.
configured at a position that defines each gate width (Lw) direction.
. The p-type well region 2 includes a driving MISFET Qd1,
Configure each channel forming region of Qd2. The gate electrode 7 is connected to the P-type well region 2 in the active region.
It is formed on the channel forming region with a gate insulating film 6 interposed therebetween.
Ru. At least one end side of the gate electrode 7 is
The element isolation isolation is equivalent to the mask alignment margin in
It protrudes on the lamina 4 in the row direction. Drive MISFETQd
The other end side of gate electrode 7 of No. 1 is connected to
and reaches above the drain region of drive MISFETQd2.
protrude in the opposite direction. Similarly, drive MI 5FETQd 2
The other end side of the gate electrode 7 is connected via the element isolation insulating film 4.
Row direction up to the drain region of drive MISFET Qd1
stand out. The gate electrode 7 is formed in the step of forming the first layer of gate material.
For example, it is formed of a polycrystalline silicon film having a single layer structure. this
The polycrystalline silicon film contains an n-type impurity such as P, which reduces the resistance value.
(or As) is introduced. The gate electrode 7 having a single layer structure has a thin film thickness.
The interlayer insulating film underlying the upper conductive layer can be
The surface can be made flat. The source region and the drain region each have a low impurity concentration.
High impurity provided in the type semiconductor region 10 and its main surface
It is composed of an n-type semiconductor region 11 having a chemical concentration. this impurity
Two types of n-type semiconductor regions 10 with different concentration of substances, n° type semi-concentration
Each of the conductor regions 11 extends along the gate length of the gate electrode 7.
This gate electrode 7 (more precisely, the gate
For electrode 7 and sidewall spacer 9) described later
Formed by self-alignment. In other words, the drive MISFETQ
The source and drain regions of d1 and Qd2 are
! ! W double drain (D D D : D double
It is composed of a 1ffused dryer structure.
. The source and drain regions of this double drain structure
In the main surface of the active region of the me-shaped well region 2,
, surrounded by a dashed line marked with the symbol DDD in Figure 10.
configured within the area. Each of the source region and drain region is an n-type semiconductor region.
10 is formed of an n-type impurity such as P. n. The n type semiconductor region 11 has a diffusion rate slower than that of the P type semiconductor region 11.
It is formed using a type impurity, for example, As. manufacturing process odor
In this way, two types of n-type can be manufactured using the same mask and the same manufacturing process.
When impurities are introduced, the Go-type semiconductor region 11 and the n-type semiconductor region 11
The respective diffusion distances in the body region lO are the distances of the two types of n-type impurities.
It is determined by the rate of diffusion of each species. Adopts a double drain structure
In each of the driving MISFETs Qd1 and Qd2,
, n-type between the Go-type semiconductor region 11 and the channel formation region
The substantial dimension of the semiconductor region 10 in the gate length direction is n-type.
From the diffusion distance of the semiconductor region 10, the n-type semiconductor region 11 is
Corresponds to the dimension minus the diffusion distance. This n-type semiconductor
The region 10 has a substantial dimension in the gate length direction L, which will be described later.
D D (Lightly Doped Drain
) structure with a low impurity concentration n-type semiconductor region (17).
It is small compared to the length direction of the seat, and has an LDD structure.
Impurity compared to the n-type semiconductor region (17) with low impurity concentration
In other words, the drive MISFET Qd1, Q
Each of d2 is a current path between the source region and the drain region.
, the parasitic resistance added to the n-type semiconductor region 10 is
It is smaller than the n-type semiconductor region (17) of the LDD structure.
A transfer MISFET that adopts an LDD structure, which will be described later.
Qt1. Driving ability (driveability) compared to each of Qt2
Tee) is high. A guide hole is provided on the side wall of the gate electrode 7 in the gate length direction.
A spacer 9 is constructed. side wall spacer
9 is formed in self-alignment with the gate electrode 7.
For example, it is formed of an insulating film such as a silicon oxide film. An upper conductive layer (13) above the gate electrode 7 is arranged.
Insulating films 8A and 8 are sequentially laminated in the exposed regions. The upper insulating film 8 mainly serves as the lower gate electrode 7. upper layer guidance
Each of the electrical layers (13) is electrically isolated, for example, using silicon oxide.
Formed by a membrane. The lower insulating film 8A is connected to the gate electrode 7.
It is configured as an oxidation mask to prevent surface oxidation.
For example, it is formed of a silicon nitride film. The memory cell MC is indicated by two points with the symbol MC in FIG.
Within the area defined by the rectangular planar shape surrounded by the chain line
It is located in. M for driving one of the memory cells MC
The planar shape of I5FETQd1 is inside the memory cell MC.
Driving M with respect to center point CP (intersection of diagonal lines of rectangle)
The planar shape of ISFETQd2 is configured with point symmetry. Na
The center point CP is a point shown for convenience of explanation.
, in terms of the actual formation in the SRAMI memory cell MC.
do not have. As shown in FIG. 16, the memory cell array MAY
For driving memory cells MC in a Mori cell MC array.
The planar shape of MISFETQd1 and Qc12 is one row.
Yl-Y3 between other memory cells MC adjacent in the direction
the other memory cell MC for the axis or the Y2-Y4 axis
Planar shapes of driving MISFETs Qd1 and Qd2
It is composed of a line symmetry of . Similarly, the drive of memory cell MC
Dynamic MISFET Qd1. The planar shape of each Qd2 is. Xl-X between other memory cells MC adjacent in the row direction
Said other memory cell M for two axes or X3-X4 axes
MI 5FET for driving C
It is composed of a line-symmetric surface shape. In other words, memory cell MC
The drive MISFETQd is connected in both the column and row directions.
It is constructed with a line-symmetrical shape. MI 5F for driving memory cells MC arranged in column direction
Of ETQd, MI for driving adjacent memory cell MC
The mutually facing source regions of each SFETQd are integral
It is composed of In other words, one adjacent memory cell MC
in the source region of the drive MISFETQd of the other memory.
Configures the source region of MISFETQd for driving cell MC
Then, the area occupied by the source region of the driving MISFETQd is
to shrink. Also, the driving MI of one memory cell MC is
5FETQd source area and the other side facing it
MrSFETQd (7) source region for driving recell MC
Since the element isolation insulating film 4 is not interposed between the
The area occupied by the memory cell MC corresponds to the child isolation insulating film 4.
The product can be reduced. Two transfer MISFETQtl of the memory cell MC
, Qt2 are shown in FIGS. 1, 2, 11, and 1, respectively.
As shown in Figure 7, the periphery is defined by an element isolation insulating film 4.
In the region formed on the main surface of the P-type well region 2,
It will be done. Each of the transfer MISFETs Qtl and Qt2 is
p-type well region 2, gate insulating film 12, gate electrode
13. It consists of a source region and a drain region. Each of the transfer MISFETs Qtl and Qt2 has a gate
Long direction and row direction (extending direction of complementary data line DL or Y
direction). In other words, each of the transfer MISFETs Qtl and Qt2
MI 5FET Qd l for gate length direction and drive. It intersects the gate length direction of Qd2 at almost a right angle. The element isolation insulating film 4 (and p-type channel stopper region)
5) is mainly MISFETQtl for this transfer. Position that defines each gate II (Lw) direction of Qt2
It is composed of The i-type well region 2 is connected to the transfer MISFET Qt1. Q
Each channel forming region of t2 is formed. The gate electrode 13 is connected to the me-shaped well region 2 in the active region.
Gate insulating film on the channel formation region! configured through 2
It will be done. The gate electrode 13 is formed in the second layer gate material formation process.
For example, a polycrystalline silicon film 1.3A and a
Laminated structure (polycide) with high melting point metal silicide film 13B
structure). The lower polycrystalline silicon film 13A has no resistance.
Introducing an n-type impurity such as P (or As) to reduce resistance value
be done. The upper layer high melting point metal silicide film 13B is made of, for example, WSi.
x (x is 2, for example). This gate electrode 13
The specific resistance value of the upper layer high melting point metal silicide film 13B is the lower layer.
Since it is smaller than the polycrystalline silicon film 13A, the signal transmission speed is
The speed can be increased. Further, the gate electrode 13 is made of polycrystalline silicon.
It has a laminated structure of an elementary film 13A and a high melting point metal silicide film 13B.
can increase the total cross-sectional area and reduce the resistance value.
Therefore, the signal transmission speed can be increased. Note that the high melting point metal silicide film 1 on the gate electrode 13
3B is MoSix, TiSix or
TaSix may also be used. The gate width dimension of the gate electrode 13 is the same as that of the driving MIS.
Smaller than the gate width dimension of gate electrode 7 of FETQd
It is composed of many parts. In other words, the transfer MISFETQt is
The drive capacity is smaller than that of dynamic MISFETQd.
, the β ratio can be earned, so the memory cell MC is
The information stored in the information storage node area can be stably maintained.
Ru. The source region and drain region each have a high impurity concentration.
゛-type semiconductor region 18 and between it and the channel formation region
The structure consists of an n-type semiconductor region 17 with a low impurity concentration provided in the
will be accomplished. Of these two types with different impurity concentrations, n-type
The semiconductor region 17 is a side portion of the gate electrode 13 in the gate length direction.
is formed in self-alignment with respect to this gate electrode 13.
It will be done. The n-type semiconductor region 17 has a p-type contact with the channel forming region.
N-type impurity with a gentle impurity concentration gradient at the n-junction
For example, it is made of P. The n-type semiconductor region 18 is a gate
A sidewall is formed on the side of the gate electrode 13 in the gate length direction.
It is formed in self-alignment with the spacer 16. n type
The semiconductor region 18 is located at the depth of the junction with the p-type well region 2.
For example, an n-type impurity that can reduce the junction depth (xj)
It is formed of As. In other words, the transfer MISFETQtl
, Qt2 are each configured with an LDD structure. This LDD
A transfer MI 5FET that adopts the structure Qt1. Qt2
Each can reduce the electric field strength near the drain region.
This reduces the amount of hot carriers generated and
Fluctuations in threshold voltage can be reduced. The side wall spacer 16 is on the side of the gate electrode 13.
Formed in self-alignment to the wall. side war
The spacer 13 is formed of an insulating film such as a silicon oxide film.
It will be done. An insulating film 15 is formed on the gate electrode 13 . The insulating film 15 mainly covers the lower gate electrode 13. Top layer conductivity
Each of the layers (23) is electrically isolated, for example by a silicon oxide film.
is formed. This insulating film 15 covers the gate electrode 7.
It is formed with a thicker film thickness than the insulating film 8 provided above.
Ru. One source region of the transfer MISFET Qtl or
As shown in FIG. 11, the drain region is connected to the driving MIS.
It is integrated with the drain region of FETQd1. transfer
MISFETQtl for driving, MI5FETQd for driving 1
Since each of them intersects the gate length direction, they can be constructed as one.
The active part of the drive MISFET Qd1 is focused on the completed part.
The transfer MI area is arranged in the column direction (gate length direction).
The active region of SFETQtl is in the row direction (gate length direction)
They are formed facing each other. In other words, the transfer MISFET
The active regions of Qtl and drive MISFET Qd1 are
The planar shape is approximately L-shaped. Similarly, one source of the transfer MISFETQt2
The region or drain region of the driving MISFET Qd2 is
Integrated into the drain region. That is, MISFETQt2 for transfer, MISF for drive
The planar shape of each active region of ETQd2 is approximately L-shaped.
Consists of. Planar shape of each of the transfer MISFETs Qtl and Qt2
In the memory cell MC, the drive MISF
Similarly to each of ETQd1 and Qd2, for the center point CP
It is constructed with point symmetry. In other words, as shown in Figure 11,
, the memory cell MC has a transfer MI 5FETQt 1
and the drive MISFETQd1 integrated with it, the transfer
Transmission MISFET Qt2 and its integrated drive
Each MISFETQd2 is point symmetrical with respect to the center point CP.
(Memory cell internal point symmetry) Memory cell MC is
, between the transfer MISFETs Qtl and Qt2.
MISFETQd1 and Qd2 are arranged for this drive.
MI 5FETQd1 and Qd2 are arranged facing each other.
place In other words, the MISFET for transfer of memory cell MC
Qtl and drive MISFET Qd1. MISF for transfer
Each of ETQt2 and drive MISFETQd2 is
Dynamic MISFET Qd1. , Qd2
The separation dimension is determined only by the law. This isolated area contains elements.
A separation insulating film 4 and a p-type channel stopper region 5 are arranged.
Ru. As shown in FIG. 17, the memory cell array MAY
In the Mori cell MC array, for transfer of memory cell MC
The planar shapes of MI 5FETQt1 and Qt2 are as follows:
Yl-Y between other memory cells MC adjacent in the column direction
The other memory cell M for three axes or Y2-Y4 axes
Each plane of MISFET Qt1 and Qt2 for transfer of C
It is composed of a line-symmetric shape. Similarly, memory cell MC
Transfer MISFETQt1. The planar shape of each Qt2 is
, Xl− between other memory cells MC adjacent in the row direction
The other memory cell for the X2 axis or the X3-X4 axis
MC transfer MI 5FETQt1, Qt2 each
It is composed of a planar shape with line symmetry. In other words, memory cell M
The transfer MISFETQt of C is arranged in the column direction and the row direction.
It is constructed with a line-symmetrical shape. MISFE for transferring memory cells MC arranged in the row direction
Of TQt, MIS for transfer of adjacent memory cell MC
The other mutually facing drain regions of each of the FETQts
Alternatively, the source region is configured integrally. That is, adjacent
The other of the transfer MISFETQt of one memory cell MC
in the drain region or source region of the other memory cell MC.
The other drain region of the transfer MISFETQt or the
The other side of the transfer MISFETQt
The area occupied by the rain region or source region is reduced. Also
, in addition to the transfer MISFETQt of one memory cell MC.
one drain or source region and the other facing
The other drive of transfer MISFETQt of memory cell MC
An element isolation insulating film 4 is provided between the rain region or the source region.
Since there is no intervening
, the area occupied by the memory cell MC can be reduced. As shown in FIG. 11, FIG. 15 to FIG. 17, respectively.
In the memory cell array MA, one column direction and one row direction
Some active regions of four memory cells MC adjacent to
It is composed of a ring-shaped planar shape. Ingredients
Physically, as shown in Figure 15, for example, $59 (X
I, Yl) are arranged in one column direction and are adjacent to each other.
Two memory cells MC and these two memory cells MC and
Two adjacent memory cells MC1 arranged in the row direction
In a total of 4 memory cells MC, 4 memory cells
One of the transfer MISFETQt and one of each of the MC.
Drive MISFETQd, total of 4 transfer MISFETs
The active regions of TQt and four driving MISFETQd are
A ring-shaped active region is formed (one unit).
), in other words, the four transfers mentioned above
MISFETQt for driving, 4 MISFETQd for driving
Each MISFET (total of 8 MISFETs) is
The source region or drain region is configured integrally and connected in series.
Consists of a ring shape. In other words, column direction, row direction
In the four memory cells MC adjacent to each
MISFETQt for transfer and drive of one side of recell MC
One L-shaped active region composed of MISFETQd
The regions are continuous with each other, and the direction in which the active region extends (gear
There is no termination in the length direction) and the active area pattern is closed.
Consists of a ring shape. The interaction of ring-shaped active regions
(MISFE for transfer)
Each gate width direction of TQt and driving MISFETQd
) is the element isolation insulating film 4 and the P-type channel.
It is defined by a stopper area 6. The four memory cells M
Each transfer MISFETQt of C runs in the gate length direction.
The drive MISFETQd is aligned with the gate direction.
Since the direction is the same as the column direction, the ring shape is flat.
It is composed of a square shape (rectangular shape). The ring-shaped active regions have the same shape in the column direction.
Multiple pieces are arranged in a shape and at the same pitch. Active regions adjacent to each other in the column direction are separated through an element isolation insulating film 4.
separated from each other. Row direction of this ring-shaped active area
The ring-shaped active region of the next stage adjacent to the array of the previous stage
Similarly, multiple pieces with the same shape and the same pitch in the column direction
At the same time, it is divided into two in the column direction with respect to the previous stage array.
They are arranged shifted by one pitch. That is, the ring
In the memory cell array MAY, the active region of the shape is
This results in a staggered arrangement as shown in FIG. The end of the memory cell array MAY, that is, the memory cell array
In the periphery, which is the boundary area with the peripheral circuit of iMAY,
The planar shape of the ring-shaped active region is shown in FIG.
As shown, the margin size is ensured. memory cell array
The ring-shaped active region at the end of the memory cell
Ring-shaped activities arranged in the central part of the array MAY
It is configured in a half-ring shape that is approximately half of the area. this
The half-ring shaped active area is simply a layout rule.
When the base is formed, as shown in FIG.
A region shared with the memory cell MC (for example, a source line or
is indicated by a dotted line E including the connection area with the complementary data line DL).
It is formed in the shape of Half-ring-shaped active area at the end of the memory cell array MAY
The area has an end in its extending direction (gate length direction),
Since the pattern of the active area is not closed, there is a
The above-mentioned margin dimension is larger than the shape indicated by dotted line E.
will be added. This margin dimension is determined during the manufacturing process.
Bird's beak generated when forming element isolation insulating film 4
Dimensions equivalent to or larger than the dimension in the gate length direction
Dimensions. Transfer MISFETs Qt1 and Qt of the memory cell MC
The respective gate electrodes 13 of FIGS.
As shown in Figures 11 and 17, in the gate width direction
and is connected to a word line (WL) 13. word 1
i13 is formed integrally with the gate electrode 13 and has the same conductivity.
Composed of layers. Among memory cells MC, transfer MI
The first word line (
WLI) 13 is connected, and the first word line 13 is connected as shown in FIG.
As shown in FIG.
Extend in a line. A second wire is connected to the gate electrode 13 of the transfer MISFET Qt2.
The word line (WL2) 13 is connected, and the second word line 13 is
As shown in Figure 17, it extends substantially in a straight line in the column direction.
Ru. In other words, one memory cell MC has
, and two first word lines extending in parallel in the same column direction.
13 and a second word lineman 3 are arranged. memory cell area
In the ray MAY, the first word line 13 and the second word line
The planar shape of the wire 13 is as described above in Y1. - Y 3-axis
, configured line-symmetrically in the column direction with respect to each of the Y2-Y4 axes.
be done. In addition, the first word line 13 and the second word line 13
The planar shape of is
In contrast, it is configured line-symmetrically in the one-row direction. The first word line (WLI) 13 is shown in FIGS.
As shown in FIG.
Element portion of gate electrode 7 of SFETQd1 in gate width direction
It intersects with the portion protruding onto the separation insulating film 4. Similarly, the second
The word line (WL2) is the gate of the driving MISFET Qd2.
On the element portion lIl insulating film 4 of the gate electrode 7 in the gate width direction.
Intersect with the protruding part. Further, a first word line (
WLI) 13, husband of the second word line (W L 2 ) 13
A reference voltage line (source line: Vss) 13 is placed between the
be done. Reference voltage line 13 is 1 in memory cell MC.
The MISFET Qd for driving the memory cell MC is arranged as shown in FIG.
1 and Qd2 as a common source line. base
The quasi-voltage line 13 is made of the same conductive layer as the word line 13.
separated from this word line 13 and provided with an element isolation insulating film.
4 in a substantially straight line and parallel to the column direction. memory
In the cell array MAY, the planar shape of the reference voltage line 13
is one row for each of Yl-Y3 axis and Y2-Y4 axis.
It is constructed with line symmetry in the direction. In addition, the plane of the reference voltage line 13
The shape is for each of the Xl-X2 and X3-X4 axes,
Constructed with line symmetry in the row direction. The reference voltage line 13 is shown in FIGS. 1, 2, and 11.
As shown, MISFETQd for driving memory cell MC
1. Elements in the gate width direction of each gate electrode 7 of Qd2
It intersects with the portion protruding onto the isolation insulating film 4. The reference voltage line 13 is shown in FIG. 1, FIG. 2, FIG.
As shown in FIG. 17, the driving MISFETs Qd1, Q
In contact with each source region (n' type semiconductor region 11) of d2.
Continued. Reference voltage line 13 is a gate insulator on the source region.
The connection hole 14 formed in the insulating film 12 in the same layer as the film 12 is
connected through. The reference voltage line 13 is connected to the lower layer of polycrystalline silicon.
The connection hole 14 formed in the film 13A and the insulating film 12
The upper layer high melting point metal passes through each of the formed connection holes 14.
The silicide film 13B is used as an n-type semiconductor region 11 as a source region.
directly follows. In this way, (A-1) is controlled by the word line (WL) 13.
MISFETQt for transfer and MISFET for drive
In SRAM1 where memory cells MC are configured with Qd
, the gate of the driving MISFETQd of the memory cell MC.
gate electrode 7, transfer MISFETQt gate electrode 13 and
Each of the word line 13 and the word line 13 is made of a different conductive layer.
Dynamic MISFETQd and transfer MISFETQt
are arranged so as to cross each other in the gate length direction, and the word
The line 13 is connected to the gate electrode 7 of the driving MISFET Qd.
MISFET Qd for driving
The gate electrode 7 intersects with a part of the gate electrode 7. With this configuration,
Occupied surface of MISFETQd for driving the memory cell MC
product, and overlap each part of the area occupied by the word line 13.
Then, the drive MISF corresponds to this overlapped area.
Occupancy of memory cell MC in the gate width direction of ETQd
Since the area can be reduced, the degree of integration of SRAMI can be improved.
Ru. (A-2) In addition to the above configuration (A-1), word
The line 13 is formed on the polycrystalline silicon film 13A and on the polycrystalline silicon film 13A.
Laminated structure (composite film) formed of high melting point metal silicide film 13B
), and the gate electrode 7 of the driving MISFET Qd
is composed of a single layer structure (single layer film) of polycrystalline silicon film. child
In addition to the above effects, the laminated structure also has the multilayer structure.
Compared to the single layer structure of crystalline silicon film, the specific resistance value is smaller (multi-crystalline silicon film).
The specific resistance value of the high melting point metal silicide film 13B is higher than that of the crystalline silicon film.
), and the resistance value of the word line 13 can be reduced.
Speeds up information writing and reading operations of Moricell MC
Therefore, the operating speed of the SRAM 1 can be increased. moreover,
The laminated structure has a higher cross-sectional area than the single layer structure of the polycrystalline silicon film.
The area can be increased and the resistance value of the word line 13 can be reduced.
Similarly, the operating speed of SRAMI can be increased. (A-3) 2 controlled by the word line (WL) 13
Memory cell MC is composed of transfer MISFETQt.
In the SRAMI, two of the memory cells MC are
Gate electrode 13 of transfer MISFET Qt 1, for transfer
Two gate electrodes are connected to each of the gate electrodes 13 of MISFETQt2.
1 word line (WLI) 13, 2nd word line (WL2) 1
Connect each of 3. With this configuration, the memory cell
Gate electrode work for MC's two transfer MISFETQtl
3. Each of the gate electrodes 13 of the transfer MISFET Qt2
The two 17th word lines 813 and the second word lines 13 are connected to each other.
Just by connecting, the gate of two transfer MISFETQtl
Electrode! 3. Gate electrode of transfer MISFETQt2
! Word line in memory cell MC connecting between each of 3.
In the case of 13 wiring lines and one word line per memory cell
) can be eliminated, so the two first word lines 13 and
Each of the two word lines 13 extends substantially straight and has a memory cell.
the length in the word line MAY be shortened, and the length in the first word line 13.
The resistance value of each second word line 13 can be reduced. This conclusion
As a result, write and read operations of information in memory cell MC
The operation speed of the SRAM 1 can be increased. Also, (A-4) is controlled by the word line (WL) 13.
Two transfer MISFETQt and reference voltage line 13 (so
Two driving MISFEs connected to ground line: Vss)
In SRAMI where memory cells MC are configured with TQd,
The two transfer MISFETQ of the memory cell MC
The respective gate electrodes 13 of tl and Qt2 are connected to each other.
Two first word lines (W
LI) 13, 27th-Do i! (WL2) Connect each of the 13
Subsequently, these two first word lines 13 and second word lines 13
The two drive MISFs are located within the area defined by each of the
While arranging ETQd1 and Qd2, the reference voltage line
Place 13. With this configuration, the configuration (A-3
) In addition to the effect of
By eliminating the rotation, the two lines in the memory cell MC
1st word #113, 2nd word line! The sky between each of the 3
The reference voltage line 13 is placed in the area (center of the memory cell MC).
Can be placed. As a result, two drive MISFETQd
1. Connection between each source region of Qd2 and reference voltage line 13
MISFET Qd1, Qd2 for driving
The float in the potential of each source region can be reduced.
Improved the stability of Morisel MC's information retention and
The operational reliability of the system can be improved. Furthermore, the memory cell
MC's two drive MI 5FETs Qd1 and Qd2
One reference voltage line 13 is placed between each
Voltage llA13 is applied to driving MISFETQd1. Qd2
Since it is used as a common wiring for each, one reference voltage line
The area occupied by the memory cell MC is reduced by an amount equivalent to 13.
, the degree of integration of SRAMI can be improved. Also, (A-5
) The two word lines (WL) of the configuration (A-4)
1, WL 2) 13. Each of the reference voltage lines 13 is the same
The conductive layer is made of a conductive layer and extends in the same column direction. this
Depending on the configuration, the reference voltage line 13 and the driving MISFET
Each of the Qd source regions (Go-type semiconductor region 11) is different.
The area occupied by the driving MISFET Qd is
Since the reference voltage line 13 can be extended within the
occupancy area, reference voltage line (source line) and driving MISF
Each element isolation region (element isolation insulating film 4) with ETQd
The area occupied by the memory cell MC can be reduced by an amount corresponding to
The degree of integration of SRAMI can be improved. Also, it is controlled by (A-6) word @ (W L )13.
2 transfer MISFETQt and 2 drive M
SRAM where memory cell MC is configured with ISFETQd
1, a transfer MISFET of the memory cell MC;
The first word line (WLI) 13 is connected to the gate electrode 13 of Qtl.
and the gate of transfer MISFETQt2.
The electrode 13 is spaced apart from and in the same direction as the first word line 13.
A second word line (WL2) 13 extending to the
First word line 13. between each of the second word lines 13;
A drain is connected to one semiconductor region of the MISFET Qtl for data transfer.
Drive MI 5FETQd1 and in area connected
and one semiconductor region of MI 5FETQt 2 for transfer.
Drive MISFET Qd2 with connected drain region
and relative to the center point CP of the memory cell MC. Transfer MISFETQtl and drive MISFETQd
The planar shape of 1 is connected to the transfer MISFETQt2 and the drive
The planar shape of the tISFETQd2 is point symmetrical. With this configuration, the inside of the memory cell MC, especially the transfer M
I 5FETQt 1 and MI 5FETQt 2 for transfer
between drive MISFETQd 1 and drive MISFET
Between each FETQd2, photolithography
Diffraction phenomenon during exposure of film technology (Halley Shimin),
The manufacturing process conditions, such as the circulation of the cooling liquid, can be made uniform.
, it is possible to reduce the variation in the dimensions of each element.
By reducing the size and occupying area of memory cell MC, S
The degree of integration of RAMI can be improved. (A-7) The transfer MIS of the configuration (A-6)
FETQt1. Each gate width dimension of Qt2 is for driving
Each gate width dimension of MI 5FETQdl, Qd2
It is configured smaller than the . With this configuration, the memo
Transfer MISFET Qtl and drive M in recell MC
ISFETQd1 and transfer MI 5FETQt2 and
The distance between the drive MISFET Qd2 and the drive MISFET Qd2 is
I 5FET Qd 1, Qd2 each element isolation region
Uniquely defined by dimensions, removing unnecessary dimensions (
Gate width dimensions of drive MISFETQd and transfer MIS
Empty area corresponding to the difference with the gate width dimension of FETQt)
Since it can be eliminated, the area occupied by the memory cell MC can be reduced,
The degree of integration of the SRAM 1 can be improved. In addition, (A-8) MISFETQt for transfer and reference voltage
Drive MISFETQ to which line (source line) 13 is connected
In SRAM1 in which memory cells MC are configured in d,
Gate of MISFETQd for driving the memory cell MC
Electrode 7. Each of the reference voltages, l1i13, is set using a different conductive layer.
and connect the reference voltage line 13 to the driving MISFET.
Extending in the gate length direction of the gate electrode 7 of Qd, and
Crosses a part of the gate electrode 7 of the driving MISFET Qd.
let With this configuration, for driving the memory cell MC,
The occupied area of MISFETQd and the occupied area of the reference voltage line 13
Superimpose each part of the area, and in this superimposed area
The corresponding amount is in the gate width direction of the drive MISFETQd.
Since the area occupied by memory cell MC can be reduced in S
The degree of integration of RAM1 can be improved. Also, (A-13) the memory cell of the above configuration (A-6)
MC is connected to the first word line (W L ) 13 and the second word line (W L ) 13 .
are arranged in the column direction in which the code lines (W L ) 13 extend.
The first and second memory cells MC between adjacent other first memory cells MC
and the 18th axis (Yl-Y3 axis) that intersects the second word line 13.
or Y2-Y4 axis), the first memory cell M
It is composed of a planar shape line-symmetrical to the planar shape of C, and the memo
The recell MC includes an extension of the first and second word lines 13.
other adjacent rows arranged in the row direction that intersects the column direction.
the first and second word lines between the two memory cells MC;
2nd axis parallel to 13 (Xi-X2 axis or X3-X4 axis)
A line pair is formed in the planar shape of the second memory cell MC with
It is composed of the same planar shape. With this configuration, the memo
Recell MC transfer MISFETQt, drive MISF
One semiconductor region of each ETQd is connected to the adjacent first semiconductor region.
Memory cell MC1 That of each of second memory cells M and C
It can also be used as a memory cell, reducing the area occupied by the memory cell MC.
, the degree of integration of the SRAM 1 can be improved. Furthermore, the said memo
Recell MC, @contacting first memory cell MC1 second memory cell
Each Moricell MC uses photolithography technology.
Diffraction phenomenon during exposure, etching liquid circulation, etc.
Uniform process conditions and reduce variation in dimensions of each element
Therefore, the size of each element can be reduced to reduce the size of the memory cell M.
Reduce the area occupied by C and further improve the degree of SRAMI integration
can. In addition, (B-1') MISFETQt for transfer and drive
SR where memory cell MC is configured with MISFETQd
In the AMI, the MISF for transfer of the memory cell MC
The gate electrode 13 of ETQt is connected to the drive MISFETQ.
The upper layer of the gate electrode 7 of d has a thicker film thickness than that of the gate electrode 7.
do. With this configuration, the transfer of the memory cell M(1,
MISFETQt for driving, and MISFETQd for driving.
The regions can be overlapped (the gate electrode 7 of Qd and the gate electrode of Qt)
The word line 13 integrated with the word line 13 is overlapped with the gate electrode 13.
), the area occupied by memory cell MC is reduced, and S
In addition to improving the integration degree of RAM1, the drive MISF
Film thickness of gate electrode (lowest layer of memory cell) 7 of ETQd
can be made thinner, reduce the growth of the step shape in the upper layer, and flatten the layer.
Therefore, the upper layer wiring (gate electrode 13, word line 13, base
Check for disconnection, etc. in each of the quasi-voltage lines 13 or the upper layer wiring).
The electrical reliability of SRAMI can be improved. In addition, (B-2) MISFETQt for transfer and drive
Memory cell MC composed of MISFETQd is word
line (WLH3) and data line (DL: 33).
In the connected SRAMI, the memory cell MC
Gate electrode I3 of transfer MISFET Qt, the word
Each of the lines 13 is in the same layer and the driving MISFET
The upper layer of the gate electrode 7 of Qd is constructed with a thicker film than that.
to be accomplished. With this configuration, the effect of the configuration (B-1)
In addition, by increasing the cross-sectional area of the word line 13,
Since the resistance value of the code line 13 can be reduced, the memory cell MC
By speeding up the information writing and reading operations of SRAM,
1, the operating speed can be increased. (B-3) The above configuration (B-1) or (B-2)
The gate electrode 7 of the driving MISFET Qd is a polycrystalline silicon film.
The gate of the transfer MISFETQt is
The root electrode 13 is provided on the polycrystalline silicon film 13A and its upper part.
With a laminated structure formed of high melting point metal silicide film 13B
configured. With this configuration, the gate electrode! product of 3
The layer structure is a single layer structure of the polycrystalline silicon film of the gate electrode 7.
The specific resistance value is smaller than that of SRAMI, so the operating speed of SRAMI is faster
speed up. In addition, (B-4) MISFETQt for transfer and M for drive
Memory cell MC composed of ISFETQd is a word line
(W L ) 13, data line (D L : 33), base
Connect to each of the quasi-voltage lines (source A!: Vss) 13
In the SRAM 1, the transfer of the memory cell MC is performed.
gate electrode 13 of MISFETQt for use, the word line 1
3. Each of the reference voltage lines 13 is made of the same conductive layer, and
In a layer different from the gate electrode 7 of the drive MISFET Qd.
A conductive layer with a smaller specific resistance value (polycide structure)
). With this configuration, the word line 13. base
It is possible to reduce the specific resistance value of each quasi-voltage line 13 (and to reduce the
(The structure can increase the film thickness and reduce its resistance value.)
Speed up information writing and reading operations of recell MC
, the operating speed of the SRAM 1 can be increased. In addition, (B-5) MISFETQt for transfer and M for drive
SRAM where memory cell MC is configured with ISFETQd
In I, the transfer MISFET of the memory cell MC
Qt is configured with an LDD structure, and the driving MISFETQ
d is configured with a double drain (DDD) structure. This configuration
Accordingly, MISFETQd for driving the memory cell MC
MIS for transferring the driving capacity (unit funductance gm) of
Increase it compared to the driving capacity (unit: gm) of FETQt,
The effective β ratio of memory cell MC can be increased.
, memory by reducing the area occupied by the drive MISFETQd.
The area occupied by cell MC can be reduced, and the degree of integration of SRAM1 can be increased.
You can improve. Furthermore, the effective β of the memory cell MC
By increasing the ratio, the information of memory cell MC
Can improve the stability of information held in the storage node area
Therefore, it reduces malfunction of memory cell MC and improves SRAMI.
Operational reliability can be improved. The capacitive element C arranged in the memory cell MC is. As shown in Figures 1, 2, 12 and 18,
Mainly the first electrode 7. Dielectric film 21. Each of the second electrodes 23
Constructed by sequentially stacking layers. In other words, capacitive element C is
Consists of a laminate structure. Memory cell MC mainly has
Two capacitive elements C are placed in the , and these two capacitive elements C
are connected in series between the information storage node areas of memory cells MC.
and placed. The [th] electrode 7 is the gate electrode of the driving MISFET Qd.
(Polycrystalline silicon formed in the first layer gate material formation process)
It consists of part of the membrane (membrane). In other words, one of the memory cells MC
The gate electrode 7 of the drive MISFET Qd1 has two
The first electrode 7 of one of the capacitive elements C is configured. on the other hand
The gate electrode 7 of the drive MISFET Qd 2 is connected to the other drive MISFET Qd 2.
The first electrode 7 of the capacitive element C is configured. A dielectric film 21 is formed on the first electrode (gate electrode) 7.
be done. The dielectric film 21 is also formed in areas other than the first electrode 7.
However, on the first electrode 7, the first word line (W
LI) 13, an area defined by each of the reference voltage lines 13,
and second word line (W L 2 ) 13, reference voltage line 1
The area defined by each of 3 is the substantial dielectric of the capacitive element C.
Used as body membrane. This dielectric film 21 is, for example, oxidized.
It is made of silicon film. The second electrode 23 is provided on the first electrode 7 with a dielectric film 21 interposed therebetween.
It consists of The second electrode 23 is approximately the same as the dielectric film 21.
Similarly, word line (WL) 13. Husband of reference voltage tiA13
The area defined by each is the substantial second electrode of the capacitive element C.
used. The second electrode 23 is the gate material of the third layer.
Formed during the formation process, for example, formed from a single layer polycrystalline silicon film
be done. Polycrystalline silicon film contains n-type impurities to reduce resistance.
For example, P (or A s ) is introduced. In other words, the capacitive element C is the driving MISFETQd
The gate electrode 7 of No. 1 is used as the first electrode 7, and the driving MISFE
The capacitive element C arranged in the region of TQd1 and the driving MI
The gate electrode 7 of SFETQd2 is used as the first electrode 7, and the driving
The capacitive element C placed in the area of MISFETQd2 for
Consists of. The second electrode 23 of this capacitive element C is for load use, as will be described later.
Also configured as the gate electrode 23 of MISFETQp
. Further, the second electrode 23 of the capacitive element C is connected to the load MISF
ETQp drain region (actually n-type channel formation region)
area 26N) and one semiconductor area of the transfer MISFETQt.
area, drain region of drive MISFET Qd, drive M
Conductive wire connecting each of the gate electrodes 7 of ISFETQd
It is also configured as a layer (intermediate conductive layer) 23. placed in the area of the driving MI 5FETQd 1
The second electrode 23 of one capacitive element C is a driving MI 5F.
Drain region (11) of ETQd 1, Ml5F for transfer
One semiconductor region (18) of ETQtl, MIS for driving
It is connected to each gate electrode 7 of FETQd2. child
These connections connect the second electrode 23 of the capacitive element C to the driving MI
Pull out in the gate length direction (column direction) of 5FETQd1
is formed in the same layer and integrally with the second electrode 23.
This is done in the conductive layer 23. The conductor 123 is an insulating film (dielectric
Same as body membrane 21 (1g) 21, insulating film 8. Husband of insulating film 12
The drain is inserted through the connection hole 22 formed by removing the
In contact with each of the in region, one semiconductor region, and gate electrode 7.
Continued. Similarly, the area of the drive MISFETQd2
The second electrode 23 of the other capacitive element C placed in the
Drain region (11) of dynamic MISFETQd2, transfer
One semiconductor region (18) of MISFETQt2 for
Connected to each of the gate electrodes 7 of the active MI 5FETQd1.
Continued. These connections are connected to the second electrode 23 of the capacitive element C.
is pulled out in the gate length direction of drive MISFETQd2.
This is done with the conductive M23. The conductive layer 23 passes through the connection hole 22.
and the drain region, one semiconductor region, and the gate electrode.
7. In the memory cell array MAY, cells arranged in a column direction are
The capacitive element C of the memory cell MC is as shown in FIG.
, the second voltage is connected to the Yl-Y3 axis or Y2-Y4 axis.
The planar shape of the pole 23 (and conductive layer 23) is configured with line symmetry.
Ru. In addition, the capacitor elements of memory cells MC arranged in the row direction
Child C is the aforementioned drive MISFETQd and transfer MISFET
Unlike the line-symmetric arrangement of SFETQt, the second electrode 23
Construct a planar shape with non-linear symmetry. That is, arrayed in columns
The arrangement of the second electrode 23 of the capacitive element C of the memory cell MC
For a column, the next stage adjacent in the row direction is arranged in the column direction.
The capacitive element C of the memory cell MC is connected to the second electrode of the preceding stage.
23, the planar shape of the second electrode 23 is arranged in a line pair in the column direction.
The planar shape of the second electrode 23 is
One memory cell M for each row of memory cells MC.
Shifted by C (1 memory cell pitch) in the column direction
be done. In the memory cell array MAY, the above memo
The second electrode 2B (and the conductive layer 2 of the capacitive element C of the recell MC)
The arrangement of 3) will be described later, but is mainly arranged in the upper layer of the second electrode 23.
Power supply voltage line (Vcc: 2εP) and load M
The planar shape of ISFETQp is non-linear with respect to the row direction.
Since it is structured, it is governed by this. Two load MISFETs Qpl of the memory cell MC
, Qp2 are shown in FIGS. 1, 2, 13, and 1, respectively.
As shown in Figure 9, on the area of the drive MISFETQd,
configured. MISFETQP for load 1 is MI for drive
Configured on the area of SFETQd2, MISFE for load
TQP2 is configured on the driving MI 5FETQdl.
Ru. Each of the load MI 5FETs QP1 and Qp2 is
Each gate length direction of dynamic MISFET Qd1 and Qd2
The gates are arranged with the gate length direction substantially perpendicular to the gates. for this load
MISFETQp1. Each of QP2 is mainly an n-type channel.
gate insulating film 24, gate electrode 23
, is composed of a source region 26P and a drain region 26P.
Ru. The gate electrode 23 is the second electrode (third electrode) of the capacitive element C.
(polycrystalline silicon film formed in the gate material formation process for each layer)
Consists of 23. In other words, drive MISFETQd1
The second electrode 23 of one capacitive element C placed in the region is
Configures the gate electrode 23 of the load MISFET Qp2
. The other one placed in the region of drive MISFETQd2
The second electrode 23 of the capacitive element C is a load MISFET Qpl.
constitutes the gate electrode 23 of. The gate insulating film 24 is formed on the gate electrode 23.
It will be done. The gate insulating film 24 is made of, for example, a silicon oxide film.
Ru. An n-type channel forming region 26N is formed on the gate electrode 23.
It is configured with a gate insulating film 24 interposed therebetween. n-type channel type
The formation region 26N is connected to the driving MISFET in the gate length direction.
It is arranged to almost coincide with the gate width direction of Qd. n-type chi
The channel forming region 26N is formed in the fourth layer gate material forming step.
For example, it is made of a polycrystalline silicon film. polycrystalline
The threshold voltage of the load MISFETQp is etched into the silicon film.
If the n-type impurity (e.g. P) to set the enhancement type is
be introduced. The load MISFET QP is
(during operation), apply a sufficient power supply voltage Vcc to the information storage node area.
information can be stored stably. Also,
When the load MISFETQp is not in operation (○FF operation)
, the supply of power supply voltage Vcc to the information storage node area is approximately
Since it can be shut off reliably, the amount of standby current is reduced and low
Power consumption can be reduced. In this respect, the load MISFETQp is a high resistance element for the load.
It's different compared to The source region 26F is the n-type channel forming region 26.
Integrated and identical on one end side (source region side) of N
Consists of a P-type conductive layer (26P) formed of conductive layers
. In other words, the source region (p-type conductive layer) 26P is in the fourth layer.
It is formed from a polycrystalline silicon film formed in the gate material formation process.
This polycrystalline silicon film is doped with P-type impurities (for example, BF2).
will be introduced. The source region 26P is shown in FIGS. 2 and 13.
and marked 26p in Figure 19 and surrounded by a two-dot chain line.
within the area (part of which is configured as a power supply voltage of 126P)
configured). The drain region 26P is an n-type transistor.
integrally on the other end side (drain side) of the channel forming region 26N.
formed of the same conductive layer as the source region 26P.
It is composed of a p-type conductive layer (26P). drain
The area 26P is the area marked with the symbol 26p and surrounded by a two-dot chain line.
Constructed within the region. In other words, the manufacturing process described below
In the area 26p surrounded by the two-dot chain line, the
p-type impurity forming source region and drain region 2BP
is introduced, and the other region is an n-type channel forming region 2.
6N. The load MISFET Qp1. drain region 26P of
is one semiconductor region of transfer MI 5FETQt 1
, drain region of drive MISFETQd1 and drive
Connected to the gate electrode 7 of MISFETQd2. similar
The drain region 2SP of the load MISFET QP2 is
, one semiconductor region of transfer MISFETQt2, drive
Drain region of MISFETQd2 and MIS for driving
It is connected to the gate electrode 7 of FETQd1. These connections
The connection is performed via the conductive layer 23. In addition, the drain region 26P of the load MISFETQp is
Gate electrode 23 via n-type channel formation region 26N
They are separated from each other. In other words, the load MISFETQp is
The gate electrode 23 and the drain region 26P overlap.
They are separated without being separated. In other words, the load MI 5FETQp
The drain region 2SP side has an offset structure. This offset structure load MISFET QP is an n-type chip.
Brake between channel forming region 26N and drain region 26P
The down pressure can be improved. i.e. this offset
The structure consists of a drain region 26F and a gate electrode 23.
n-type channel formation region 26N where charges are induced.
By separating the drain region 26P and the n-type chamfer
Breakdown resistance of pn junction with channel forming region 26N
In the case of the 9th embodiment that can improve the pressure, the load MISFET
Qp is an offset of approximately 0.6 [μm] or more.
It consists of distance dimensions (separation dimensions). The conductive layer 23 is the second electrode 2 of the capacitive element C as described above.
3 (3rd layer gate material formation process)
(polycrystalline silicon film formed in steps). The conductive layer 23 is M for load.
It is formed of the same conductive layer as the gate electrode 23 of ISFETQp.
It will be done. This conductive layer 23 is a contact formed on the interlayer insulating film 24.
The p-type of the upper layer load MISFETQp is passed through the connecting hole 25.
Connected to drain region 26P. Also, as mentioned above
, the conductive layer 23 is connected to the transfer MISFET through the connection hole 22.
One semiconductor region of Qt, the drive MISFET Qd
It is connected to the rain region and gate electrode 7. in this way
The conductive layer 23 to be configured is determined by the thickness of the conductive layer 23 and the conductivity.
The position of the upper connection hole 25 of the layer 23 and the lower connection hole 22
The load MISFET Q corresponds to the dimension between the
The other end side of the p drain region 26P, the transfer MISFET
One semiconductor region (18) of Qt and driving MISFE
The conductive layer 23 is formed of a polycrystalline silicon film doped with n-type impurities.
Therefore, the P-type drain region 26P is formed.
The one semiconductor region (18) of P-type impurity, the drain
The diffusion distance to each of the regions (11) can be increased by the conductive layer 23.
Wear. In other words, the conductive layer 23 is connected to the transfer MISFETQt
, in each channel formation region of drive MISFETQd.
, P type of drain region 26P of load MISFETQp
Reduces impurity diffusion and improves transfer MISFET
Qt, the respective threshold voltages of the driving MISFET Qd.
Fluctuations can be prevented. The conductive layer 23 is a load MISF
Gate electrode 23 of ETQp, second electrode 23 of capacitive element C
Or the same conductive layer as the conductive layer 23 drawn out from it (same conductive layer)
Since it is formed in one manufacturing process), the number of conductive layers is reduced due to the structure.
can. In addition, the conductive layer 23 has a number of manufacturing steps in the manufacturing process.
can be reduced. In this way, (B-7) two driving MISFETQd
and two load MISFETQP, the memory cell MC is
In the configured SRAM1, the navigation memory cell MC is
This one is placed on top of one drive MIS FETQd.
The gate electrode 7 of one driving MISFET Qd, one negative
The gate electrodes z3 of M and 15FETQp are opposite each other.
and one load MISFETQp is provided, and this one
The drain region 26P of the load MISFET QP is
Gate electrode z of one or the other load MISFETQp
Conductive layer (intermediate conductive layer) 23 formed of the same conductive layer as 3
and the drain of the other driving MISFETQd.
Connect to area (11). With this configuration, the memory
Drain region of one load MISFETQp of cell MC
area 26P and the drain of the other driving MISFET Qcl
The distance between the regions is separated by the conductive layer 23, and the one of the regions is separated by the conductive layer 23.
Form the drain region 26P of the load MISFETQp.
The drain of the other driving MISFET Qd of the p-type impurity
Since diffusion to the in area can be prevented, the
Based on the diffusion of the p-type impurity into MISFETQd
Improved the electrical characteristics of SRAMI, such as preventing fluctuations in low voltage.
I can move up. Furthermore, similarly, the one load MISF
The P-type drain region 26p of ETQP is a conductive layer (intermediate conductive layer).
layer) 23 to the other transfer MI 5FETQt.
Since it is also connected to the other semiconductor region (18), this transfer
It is also possible to prevent fluctuations in the threshold voltage of MISFETQt for
. (B-8) Memory cell MC of the above configuration (B-7)
Turn off the drain region 26P of the load tIsFETQP.
It is composed of a set structure. With this configuration, the load M
ISFETQP drain region 26P-n type channel type
The breakdown voltage between the formation area 26N has been improved, and the
Since the occupied direct product of MISFETQp can be reduced, the memory
Reduce the area occupied by cell MC and increase the degree of integration of SRAMI
I can move up. The source region (p-type conductive layer) of the load MISFET Qp
26P) is connected to the power supply voltage line (Vcc) 26P.
. The power supply voltage line 26P is connected to the P-type trench conductor layer which is the source region.
6 which is constructed integrally with 26P and is constructed of the same conductive layer.
In other words, the power supply voltage! 26P is the 4th layer gate material forming process
It is formed from a polycrystalline silicon film formed in
The element film contains p-type impurities (for example, BP) that reduce the resistance value.
will be introduced. Two power supply voltage lines 26P are arranged in the memory cell MC.
It will be done. These two power supply voltage lines 26P are connected to the memory cell array.
may be spaced apart from each other as shown in Figure 19.
Moreover, they extend substantially in parallel in the same column direction. Memory cell M
One power supply voltage line 26P arranged at
It is configured integrally with the source region of SFETQp2, and the first
and extends along the board line (WLl) 13. on the other hand
The power supply voltage line 26P is the solenoid of the load MISFET Qpl.
The second word Ji (WL2)
13 and extends along it. As shown in FIGS. 13 and 19, the memory cell M
In C, one power supply voltage line 26P extends in the column direction.
At the same time, the other semiconductor of the transfer MI 5FETQt1
The area (18) and the first data line (D) of the complementary data line DL
LI:33) (intermediate conductive layer 23 described later)
detour in the column direction. In other words, one power supply voltage line 26P
is the load MISFET Qpl of the memory cell MC and the above
Do not pass between the connected part, but adjacent to this connected part in the row direction.
Load of other memory cells MC in contact with (arranged above)
A detour is made between the MISFETQpl and the MISFETQpl. Also, one
The power supply voltage line 26P is adjacent in the row direction (disposed on the upper side).
one power supply voltage line 26P of the other memory cell MC
Also used as. The other power supply voltage line 26P is. Similarly, it extends in the column direction, and the transfer MISFETQ
The other semiconductor region (18) of t2 and the complementary data line DL
The connection part with the second data line (D L 2: 33)
(intermediate conductive layer 23 to be described later) is detoured in the column direction. The other power supply voltage line 26P is the load MI of the memory cell MC.
A detour is made between SFETQp2 and the connection part, and this connection is
The connected part and other members adjacent in the row direction (placed below)
Passes between Morisel MC load MISFET QP2
do not. Similarly, the other power supply voltage mzsp is
Another memory cell M adjacent in the direction (disposed on the lower side)
It is also used as the other power supply voltage line 26P of C. In other words, 1
Two power supply voltage lines 26P are arranged in each memo cell MC.
However, each of these two power supply voltage lines 26P is connected in the column direction.
The respective power supply voltages of other memory cells MC adjacent above and below
Since it is also used as line 26P, one memory cell MC has
Substantially one power supply voltage line 26P is arranged.
Ru. Two power supply voltage lines 26 arranged in the memory cell MC
P is the memory cell array M, as shown in FIG.
In the column direction of AY, Yl-Y3 axis or Y2-Y4 axis
The planar shape is constructed with line symmetry. Also, memory
The two power supply voltages gzs arranged in the cell MC are
In the row direction of the cell array MAY, the aforementioned driving MI
Line-symmetrical arrangement of SFETQd and transfer MISFETQt
different from the column and the same as the arrangement of the second electrode 23 of the capacitive element C.
Similarly, the planar shape is constructed with non-linear symmetry. In other words, column direction
The power supply voltage extending through the memory cells MC arranged in I!
The next column adjacent to the 26P planar shape in the row direction
A power supply voltage line extending through memory cells MC arranged in the direction
26P is a power supply voltage extending from the previous stage memory cell MC.
Similar to the pressure wire 26P, it is configured with line symmetry in the column direction and
, a power supply voltage line 26 extending through the preceding memory cell MC.
1 memory cell MC for P (1 memory cell pitch)
h) in the column direction. memory cell array
MISF for transfer of power supply voltage line 26P
between the other semiconductor region of ETQt and complementary data line DL.
The detour of the connecting portion (intermediate conductive layer 23) is in the same row direction.
It is done on the upper side. In other words, the power supply voltage line 26P
As shown in the figure, bypass all the above connections upwards.
. In this way, (A-14) the mechanism of the above configuration (A-1, 3)
The other semiconductor of Morisel MC's transfer MISFET Qtl
The first data line (
DLI:33) is connected and transfer MISFETQt2
The second data of the complementary data line DL is placed in the other semiconductor region of
line (DL2: 33) is connected and the first word
line (along WLIH3, the transfer MISF
The other semiconductor region of E T Q t 1 and the first data line
(D L L ) bypassing the connection part (intermediate conductive layer 23)
and one half of the transfer MI 5FETQt 2
to the conductor region (18) via the load MISFET Qp2.
Extend the first power supply voltage line (source line) 26P to be connected
and the transfer line along the second word line (WL2) 13.
The other semiconductor region of the transmission MISFET Qt2 and the second data
The connecting portion (intermediate conductive layer 23) with the conductive wire (DL2) is
Detour in the same direction as the power supply voltage line 26F of No. 1, and
One semiconductor area of transfer MISFET Qtl for load
Second power supply voltage connected via MISFETQpl
The line (source line) 26P is extended. That is, (A-
15) Placed in the memory cell MC of the above configuration (A-14)
The two power supply voltage lines 26P connected to the memory cell array MA
In Y, column direction (Yl-Y3 axis or Y2-Y4 axis)
The row direction (Xi-X2 axis or XX3 axis
-X4 axis). With this configuration,
Complementary to the other semiconductor region of the transfer MISFETQt
At the connection part (intermediate conductive layer 23) with the data line DL
, bypass the two power supply voltage lines 26P only in one direction (upper side)
and between the connection part and the load MISFET Qpl.
One power supply voltage line 26P (or the connection section and the load MI
The other power supply voltage line 26P) is connected between SFETQp2.
Therefore, the one power supply voltage line 26P is not placed.
The connecting portion of the memory cell MC and the load M
Reduce the area occupied between ISFETQpl and SRAM
The degree of integration of 1 can be improved. Note that this effect does not apply to memory
MC's load MISFETQP is used as a high resistance element for load.
The same result can be obtained even if the values are changed. Of the capacitive elements C arranged in the aforementioned memory cell MC,
of the capacitive element C placed on the driving MISFET Qd1.
The second electrode 23 (and conductive layer 23) is as shown in FIG.
, one power supply voltage line 26P is connected to the connection part (intermediate conductor).
In the conductive layer 23), the detour is made to another memory cell MC on the upper side.
and the connection part and the MI 5FETQp 1 for load.
Since we are reducing the separation dimension between
The planar shape is reduced by an amount corresponding to . Also, the memory
Capacitor placed on MISFETQdZ for driving MC
The second electrode 23 (and conductive layer 23) of element C
The source voltage line 26P is connected to the connection portion (intermediate conductive layer 23).
and detours to this memory cell MC, and connects it to the connection part.
Connect the other power supply voltage line 2 between it and the load MISFET Qp2.
6P, so this other power supply voltage line 26P
The planar shape increases by the amount corresponding to the passage. In other words, the power supply voltage line 26P is
This power supply voltage line 2 always extends over the Morisel MC.
The driving M is the side where SP detours over the memory cell MC.
Second electrode of capacitive element C placed on ISFETQd2
Based on the planar shape of 23 (and conductive layer 23),
Capacitive element placed on drive MI 5FETQd 1
The planar shape of the second electrode 23 (and conductive layer 23) of C is reduced.
be done. Therefore, the capacitive element C of the memory cell MC
The two electrodes 23 (and the conductive layer 23) are arranged in the row direction (Xi-X2
axis or X3-X4 axis), the drive
of the second electrode 23 placed on the dynamic MISFET QdZ.
The planar shape of all the second electrodes 23 is determined by the planar shape.
, the area occupied by memory cell MC increases, but as mentioned above,
In accordance with the arrangement of the power supply voltage line 26P, the
By arranging it line-symmetrically, the drive MISFETQd
The size of the second electrode z3 on the second electrode z3 on the
The area occupied by Morisel MC can be reduced. In this way, (A-16) the memo of the above configuration (A-15)
Each of the load MISFETs Qpl and Qp2 of the recell MC
gate electrode 23 (second electrode 23 of capacitive element C and conductive
The planar shape of the layer 23) is configured with line symmetry in the column direction.
, are configured asymmetrically in the row direction. With this configuration
, the two load MISFETQp of memory cell MC.
The gate electrode 23 (second
Since the planar shape of the electrode 23 and conductive layer 23) can be reduced,
, the area occupied by the memory cell MC is reduced by an amount corresponding to this reduction.
It is possible to reduce the size and improve the degree of integration of the SRAM1. The other of the transfer MISFETQt of the memory cell MC
The semiconductor region (18) is shown in FIG. 1, FIG. 2, FIG.
As shown in Figure 20, complementary data, 6! (DL)3
Connected to 3. MIS for transfer of one side of memory cell MC
FETQtl is connected to the first data line (D
L L ) 33. Other transfer MI 5
FET Qt 2 is connected to the second data line (
DL2). This transfer MISFETQt
The connections between the other semiconductor region and the complementary data line 33 are as follows.
, intermediate conductive layers stacked sequentially from the lower layer side to the upper layer side,
1!23.29, through each of the embedded electrodes 32.
Ru. The intermediate conductive layer 23 is shown in FIG. 1, FIG. 2, FIG.
As shown in FIG.
. A part of this intermediate conductive layer 23 is a side wall space.
sa! 6, the interlayer insulating film 2
MISFET for transfer through the connection hole 22 formed in 1.
It is connected to the other semiconductor region (18) of Qt. The contact
Connecting hole 22 is a side wall spacer! Territory defined in 6.
The opening size is larger than the area (larger on the gate electrode 13 side).
It consists of The side wall spacer 16 is
As mentioned above, the gate electrode 13 of the transfer MISFETQt
The sidewalls are formed in self-alignment thereto. In other words, inside
A part of the interlayer conductive layer 23 is bounded by the sidewall spacer 16.
Transfer MI at the specified position and self-aligned to it.
Connected to the other semiconductor region of SFETQt. intermediate guide
The other part of the conductive layer 23 is at least connected to this intermediate conductive layer 23.
Mask alignment margin in the manufacturing process with the upper intermediate conductive layer 29
An amount corresponding to the tolerance dimension is drawn out onto the interlayer insulating film 21.
. This intermediate conductive layer 23 includes the transfer MISFETQt and other
A manufacturing process is applied to each of the semiconductor region and the intermediate conductive layer 29.
Even if mask misalignment occurs, this mask misalignment
absorb it. The other semiconductor region of the transfer MISFETQt has a corresponding
The intermediate conductive layer z9 can be apparently connected by self-alignment. The intermediate conductive layer 23 is the gate of the load MISFET QP.
the second electrode 23 of the capacitive element C, the conductive layer 23
are made of the same conductive layer as each. In other words, the third layer
It is formed from a polycrystalline silicon film formed in the gate material formation process.
, this polycrystalline silicon film contains n-type impurities that reduce the resistance value.
be introduced. The intermediate conductive layer 29 is shown in FIG. 1, FIG. 2, FIG.
As shown in FIG. 20, the interlayer I! organized on the lamina z7
Ru. One end side of the intermediate conductive layer 29 is formed on an interlayer insulating film z7.
The intermediate conductive layer 23 is connected to the intermediate conductive layer 23 through the connecting hole 28.
Ru. This intermediate conductive layer 23 is a MISF for transfer as described above.
Connected to the other semiconductor region of ETQt. intermediate conductive layer
The other end side of 28 is drawn out in the column direction and is connected to an interlayer insulating film 30.
Embedded electrode 32 embedded in connection hole 31 formed in
connected to. This embedded electrode 32 is connected to the complementary data line 3
Connected to 3. In the other semiconductor region of the transfer MISFETQtl,
The intermediate conductive layer 29 to which the end side is connected is a MISFE for transfer.
Complementary transistors extending in the row direction on the other semiconductor region of TQt2
The first data line (DL L ) of the gender data lines 33
33 is pulled out in the column direction to the bottom, and this pulled out area
It is connected to the first data line 33 at the terminal. Similarly, transfer
One end side is in contact with the other semiconductor region of MISFETQt2.
The intermediate conductive layer 29 connected to the transfer MISFET Qtl
Complementary data extending in the row direction over the other semiconductor region of
The second data line (D L 2 ) 33 of the lines 33
is pulled out in the column direction, and in this pulled out area
It is connected to the second data line 33. In other words, the intermediate conductive layer 2
9 is a MISFET Qtl, Q for transfer of memory cell MC.
each of t2 and extends to the inverted position in the column direction.
Connecting each of the first data line 33 and the second data line 33
configuring a cross-wiring structure. The method for forming the intermediate conductive layer 29 will be described later.
, formed in the first layer metal material forming step of the manufacturing process.
It is formed of a high melting point metal film such as a W film. This W film is
Compared to the polycrystalline silicon film and high melting point metal silicide film mentioned above,
The resistance value is small. The interlayer insulating film 27 underlying this intermediate conductive layer 29 is oxidized.
A silicon film 27A and a BPSG film 27B were laminated in sequence.
Composed of a composite membrane. BPSG in the upper layer of the interlayer insulating film 27
The film 27B is subjected to glass flow, and the surface is flattened.
will be applied. The buried electrode 32 is a contact formed on the interlayer insulating film 30.
selectively formed on the intermediate conductive layer 29 in the via hole 31
be done. This buried electrode 32 is generated in the connection hole 31.
It absorbs the steep step shape and improves the complementary data line 33 of the upper layer.
Can prevent disconnection defects. As shown in FIG.
Silicon film 30A, coating type silicon oxide film 30B, deposition type
3M's laminated structure in which 30C silicone films are sequentially laminated.
configured. Lower layer silicon oxide film 30A. As will be described later, each of the upper silicon oxide films 30C is made of tetrafluoride.
Ethoxysilane (TEOS: Tetra Eth
oxyS 1lane) plasma using gas as the source gas
Deposited by MacCVD method. The lower silicon oxide film 30A is
The film is deposited with a uniform thickness along the step shape of the base, especially on the bottom.
In the step-shaped concave part of the ground, the upper side of this concave part
Overhang shape is less likely to occur. In other words, the lower acid
The silicon oxide film 30A prevents the formation of cavities based on the overhang shape.
It can reduce the amount of raw material. The intermediate layer silicon oxide film 30B is
Applied using the SpinOnG 1ass method.
, after the baking process, the entire surface is etched (etched back).
(check) is done. This intermediate layer silicon oxide film 30B is
The shape is concentrated on the stepped portion of the surface of the silicon oxide film 30A.
is formed (remains), and the surface of the interlayer insulating film 30 is planarized.
It will be done. The intermediate layer silicon oxide film 30B is basically the same as described above.
A connection hole connecting the interconductive layer 29 and the complementary data line 33
On the surface of the lower silicon oxide film 30A except for the region 31
It is formed on the stepped part. In other words, the silicon oxide film 3 of the intermediate layer
Complementary data line (aluminum
Corrosion of aluminum alloy) 33 can be prevented. Upper layer silicon oxide film
30G covers the surface of the silicon oxide film 30B, which is the intermediate layer.
However, deterioration of the film quality of this silicon oxide film 30B can be prevented. The complementary data line (DL) 3B is as shown in FIG.
2, is formed on the interlayer insulating film 30. This complementarity data
The wire 33 is an embedded electrode 32 embedded in the connection hole 31.
connected to. Complementary data line 33 is at the beginning of the manufacturing process.
It is formed in the second layer metal material forming process. Complementary data line
33 is a barrier metal film 33A5 aluminum alloy film 33
It has a two-layer laminated structure in which B is laminated in sequence. The barrier metal film 33A is basically a transfer MIS.
The other semiconductor region (18) of FETQt and the intermediate conductor! 2
Silicon (Si) of 3, aluminum of aluminum alloy film 33B
This prevents the mutual diffusion of Ni (A ff ) and the so-called
Prevents alloy spikes. In addition, the barrier metal film 33
A is a metal material with good adhesion for the lower layer embedded electrode 32.
Configure. The barrier metal film 33A is formed of, for example, a TiW film. The aluminum alloy film 33B is a polycrystalline silicon film with a high melting point.
Low specific resistance value compared to metal films and high melting point metal silicide films.
Sai. Aluminum alloy film 33B is doped with Cu and Si.
Constructed of aluminum. Cu basically improves electromigration resistance voltage.
It has the ability to Si basically uses alloy spikes.
It has a preventive effect. Moreover, the complementary data line 33 is
, the aluminum alloy film 33B is an aluminum film, or
The lower layer barrier metal film 33A is abolished and a single layer aluminum layer is used.
It may also be composed of an aluminum alloy film. The complementary data line 33 is shown in FIGS. 2 and 20.
, extending in the row direction over the memory cells MC. complementarity
One of the first data m (D L 1
) 331t Me-Tl: IJ t'#MC(7) Drive
MI 5FETQd for 111 1. MISFE for transfer
Extend in the row direction on TQt2 and load MISFETQpZ.
Exists. The other second data line (D L 2 ) 33 is a memory cell.
MISFETQd2 for driving M and C, MISFE for transfer
Extend in the row direction on TQtl and load MISFETQpl.
Exists. That is, the first data l1 of the complementary data line 33
A33 and the second data line 33 are spaced apart from each other and almost
Extend substantially parallel in the row direction. As shown in FIGS. 2 and 20, the memory cell array
In MC, the phase of memory cells MC arranged in the column direction is
The planar shape of the complementary data line 33 is Yl-Y3 axis or Y2-
It is arranged line-symmetrically with respect to the Y4 axis. arranged in rows
The planar shape of the complementary data line 33 of the memory cell MC is
Arranged symmetrically with respect to the l-X2 axis or the X3-X4 axis
Ru. In this way, (B-10) Transfer MI of memory cell MC
In addition to this transfer MISFETQt, there is a
A complementary data line (
DL) In SRAML where 33 is extended, the memo
The other of the transfer MISFETQtl of the recell MC
An intermediate conductive layer 29 is interposed in the semiconductor region (18), etc.
Complementarity extending the upper part of the transfer MISFET Qt2
One first data line (DL L ) 3 of the data lines 33
3 and the other transfer MISFET Q
An intermediate conductive layer 29 is interposed in the other semiconductor region of t2.
, extends the top of one transfer MI 5FETQt 1
Complementarity data! ! 33, the other second data line (DL
2) Connect 13. With this configuration, the memory
Cell MC transfer MISFETQt arrangement and complementary data
The arrangement of the tangent wires 33 is reversed, and the distance is matched to the reversed distance.
The corresponding amount is routed through the intermediate conductive layer 29, and the transfer MI
Complementary data 83B with the other semiconductor region of SFETQt
Since the connection distance with the transfer MISFET is increased,
The silicon of the other semiconductor region of Qt and the complementary data line 33
Interdiffusion with metal (AQ of aluminum alloy film 33B)
and prevents alloy spikes, etc.
can improve reliability. (B-1,1) Complementarity data of the above configuration (B-10)
The data line 33 is a barrier metal film (for example, T i W) 33
It is composed of a laminated structure of A and an aluminum alloy film 33B.
, the intermediate conductive IF29 is composed of a high melting point metal film (W).
It will be done. With this configuration, the aluminum alloy film 33B
has a specific resistance value compared to other high melting point metal films and polycrystalline silicon films.
Since it is small and the resistance value of the complementary data line 33 can be reduced,
By increasing the speed of information transmission on the complementary data line 33, SRA
The operation speed of MI can be increased, and the intermediate conductive
Since the high melting point metal film of the layer 28 has barrier properties, the above-mentioned
Alloy spikes can be better prevented. 1, 2, and 14 on the memory cell MC.
and main word line (MWL) as shown in FIG.
29 and a sub word line (SWLI) 29 are arranged. Each of the main word line z9 and sub word line 29 is the same
Conductive layer (high melting point formed in the first layer metal material formation process)
the same conductive layer as the intermediate conductive layer 29;
Consists of. In other words. Each of the main word line 29 and sub-word line 29 is a word line.
Constructed in a layer between line (WL) 13 and complementary data line 33
be done. Each of the main word line 29 and sub word line 29
is connected to transfer MISFETQt1 of memory cell MC.
connected to the intermediate conductive layer 29 and the transfer MISFET Qt2.
The intermediate conductive layer 29 is disposed between the intermediate conductive layer 29 and the intermediate conductive layer 29 connected thereto. main thing
Each of the word line 29 and the sub-word line 29 is spaced apart from each other.
and the memory cell array MAY extends substantially in parallel in the column direction.
do. As shown in Figures 3, 4 and 6 above, the main
There are four word lines 29 arranged in the row direction (4 [bitl
) is arranged for each memory cell MC. main word
Line 29 represents a total of 16 memory blocks in 4 memory blocks MB.
Extends over the Mori cell array MAY, reducing resistance value
For the purpose of
Configure. The sub word line (SWLI) 29 is shown in FIGS.
As shown in Figure 6, word decoding of memory block MB is performed.
Memory cell area located near the data circuit WDEC
In a ray MAY, one memory arranged in the row direction
One is arranged for each cell MC. The sub word line 29 is 1
with a length that extends a memory cell array MAY,
The length of the line is shorter than that of the main word line 29.
Therefore, the wiring width dimension is made narrower than that of the main word line 29.
do. Each of the main word line 29 and the sub word line 29. Reference voltage line (Vss) 13 connected to memory cell MC
is made of the same conductive layer as the word line (W L ) 13, and this
The conductive layer that extended the reference voltage lX13 is now an empty area.
Therefore, we created this empty area (enough to place two wires).
area). In other words, memory cell MC
In addition to the word line (WL) 13 and the reference voltage line 13,
Mains used in a divided word line method in the column direction.
Used with double word line 29 and double word line method
Two word lines of sub-word line 29 can be extended. In this way, (A-10) the first of the configuration (A-9)
Word line (WLI) 13 and second word line (WL2) 1
3 is composed of the same conductive layer, and the main word line (MW
L) 29, first sub word line (SWLI) 29 and second
The sub word line (SWL2) 29 is the first word line 13
and the second word linework 3 and the same conductive layer, which is a separate layer,
and compared to the first word line 13 and the second word line 3.
Constructed of materials with low resistance. This configuration allows
Main word line 29. Sub word line 29 and word line
13 three types of word lines are constructed with two conductive layers.
, reducing the number of conductive layers and simplifying the multilayer wiring structure of SRAM1
main word line 2, which can be
9. Reduce the specific resistance value of each sub-word line 29, and
By increasing the charging and discharging speed of SRAM1, the operating speed of SRAM1 can be increased.
You can speed up the process. Also, (A-11) Word lines extending in the column direction! 3 and
Where the reference voltage line (Vss) 13 intersects with the column direction
A memory is installed in the area where it intersects with the complementary data line 33 extending in the direction.
In the SRAMI where the cell MC is arranged, the reference voltage
The pressure line 13 is connected to the same conductive layer as the word line (W L ) 13.
The first data line (D
L L ) 33 and the second data line (DL2) 33 in front
Same conductive layer separate from word line 13 and reference voltage line 13
The word line 13 and the reference voltage line 13 and the
In the same conductive layer between the complementary data line 33, the word
The device line 13 and the reference voltage line 13 extend in the same column direction.
Main used when adopting the bided word line method
Word line (MWL) 29 and double word line system
The two sub-word lines (SWL) 29 used in
Configure word lines. With this configuration, the reference voltage line 13 is connected to the word line 13.
It was composed of the same conductive layer, and the reference voltage line 13 was extended.
There is an empty area in the conductive layer where at least two wires can be extended.
The main word line 29 and subword line 29 can be placed in this empty area.
By extending the two word lines of the word line 29,
SRAMI
The degree of integration can be improved. In other words, the memory cell array
said main word without increasing its footprint on MAY
! ! 29 and sub-word line 29 can be extended, so the SR
Divided word line method and double word line method for AMI
A dry line method can be used at the same time. A substrate including the complementary data line 33 of the memory cell MC.
The entire surface (excluding the area of external terminal BP) is shown in Figure 1.
So, final passivation film (final protective film)
34 are configured. This final passivation film
34 does not show its structure in detail, but it is made of silicon oxide film, nitride film, etc.
Three-layer laminated structure in which a silicone film and a resin film are sequentially laminated.
Consists of. The silicon oxide film below the final passivation film 34 is
As will be described later, tetraethoxysilane gas is used as the source gas.
It is formed by the CVD method. In other words, the underlying silicon oxide
The film prevents cavities from forming in the overlying silicon nitride film. The silicon nitride film of the intermediate layer is formed by plasma CVD. This intermediate layer silicon nitride film has the effect of increasing moisture resistance. The upper resin film is made of polyimide resin, for example. This resin film is applied to the sealing part of the resin-sealed semiconductor device.
Shields alpha rays emitted from radioactive elements contained in
, the α-ray soft error resistance of the SRAM 1 can be improved. Ma
In addition, the resin film is a filler contained in the resin sealing part.
Do not crack the interlayer film such as the final passivation film 34.
prevent the occurrence of problems. The peripheral circuit of the SRAM1 is shown in Figure 21 (cross-sectional view of main parts).
As shown, it is composed of 0MO8. The n-channel MISFETQn of this CMO5 is
The device isolation insulating film 4 and the P-type channel stopper region 5
Within the defined area, the P-type well region 2
Constructed on the main surface of the active region. In other words, the n-channel MISFETQn is mainly p-type
Well region 2, gate insulating film 12. Gate electrode 13, so
It consists of a source region and a drain region. The gate electrode 13 is a MISF for transfer of the memory cell MC.
It is composed of the same conductive layer as the gate electrode 13 of ETQt. The source region and the drain region each have a low impurity concentration.
type semiconductor region 17 and high impurity concentration n° type semiconductor region
Consists of 18 areas. In other words, the n-channel M of the peripheral circuit
I S F E T Q n is the transfer rate of memory cell MC.
Like the transmission MISFETQt, it is configured with an LDD structure.
Ru. The n-channel MISFETQn that adopts the LDD structure is
As mentioned above, the amount of hot carriers generated can be reduced.
Therefore, fluctuations in threshold voltage over time can be prevented. Also,
This n-channel MISFETQn is a rotating tIsFE
Compared to polycrystalline silicon films such as gate electrode 7 of TQd, specific resistance is
The gate electrode 13 is composed of a conductive layer having a laminated structure with a small value.
Therefore, the operating speed can be increased. Source region and drain of the n-channel MISFETQn
A wiring 29 is provided in the n° type semiconductor region 18, which is each of the n° type semiconductor regions.
is connected. Delivery! 2B is arranged in the memory cell MC.
The intermediate conductive layer 29, the main word llA 29 and the sub
It is made of the same conductive layer as the word line 29. This wiring 29 is formed on the interlayer insulating film 27, 24, 21, etc.
The contact hole 28 is connected to the n-type semiconductor region 18 through the contact hole 28.
It will be done. Further, the wiring 29 is formed in the interlayer insulating film 30.
Through the embedded electrode 32 embedded in the connection hole 31,
It is connected to the wiring 33 of the layer. The embedded electrode 3z is a memo.
The same conductive layer as the embedded electrode 32 formed on the recell MC.
configured. The wiring 33 is a phase wire arranged in the memory cell MC.
It is composed of the same conductive layer as the complementary data 11X33. The p-channel MI 5FETQp of the CMO8 is
, within the area defined by the element isolation insulating film 4.
, are formed on the main surface of the active region of the n-type well region 3. In other words, p-channel MISFETQp is mainly n-type
Well region 3, gate insulating film 12. Gate electrode 13, so
sn-type well consisting of a source region and a drain region
Region 3 constitutes a channel forming region. Gate electrode 13
is the n-channel M I S F E T Q n and
Similarly, the gate electrode 13 of the transfer MISFETQt
It is composed of the same conductive layer. Source region, drain region
are the n-type semiconductor region 19 with a low impurity concentration and the n-type semiconductor region 19 with a high impurity concentration, respectively.
It is composed of a P° type semiconductor region 20 having an impurity concentration. low
The impurity-concentrated P-type semiconductor region 19 is an n-channel MIS
Similar to FETQn, P° type semiconductor region with high impurity concentration
It is provided between the region 20 and the channel forming region. In other words, the p-channel MI 5FETQp has an LDD structure.
configured. Similarly, p-channel adopting LDD structure
MISFETQp prevents threshold voltage fluctuation over time
can. In addition, the p-channel M5FETQp has a gate
electrode! The specific resistance value of 3 is small, so the operation speed can be increased.
I can figure it out. Source region and drain region of P-channel MISFETQp
A wiring 29 is connected to each of the p-type semiconductor regions 20.
Continued. In addition, the wiring 29 is connected to the top via the embedded electrode 32.
It is connected to the layer wiring 1R33. The CMO5 area of this peripheral circuit is the memory cell array.
The final passivation film 3 is similar to the MAY area.
4 is composed. In this way, (D-3) is controlled by the word line (WL) 13.
MISFETQt for transfer and MISFETQ for drive
d constitutes a memory cell MC, and this memory cell MC
Controls information write operation, information retention operation, and information read operation.
The peripheral circuit that controls the MISFET (CMO8 in this example)
), the transfer MISF
Gate electrode 13 of ETQt and word connected to it
The line 13 is connected to the gate electrode 7 of the driving MISFET Qd.
The peripheral circuit
The gate electrode 13 of the MISFET (Qn, Qp) is
Same conductive layer as gate electrode 13 of transfer MISFETQt
Consists of. With this configuration, transfer of the memory cell MC is possible.
Gate electrode 13 and word line 1 of transmission MISFET Qt
Reduce the resistance value of 3 and write information to memory cell MC.
and information read operation can be speeded up, SRA
In addition to increasing the operating speed of MI, the peripheral circuit
Gate electrode of MISFET (Qn, Qp)! 3 resistance
To reduce the value and increase the operating speed of this MISFET
This allows for faster SRAMI operation speed.
It will be done. The input stage circuit ■ of the peripheral circuit and the external circuit shown in FIG.
The electrostatic breakdown prevention circuit ■ placed between the terminal BP and
The specific cross-sectional structure of MISFET Qnl for lamps is shown below.
Although not shown, the MISFET for driving the memory cell MC
It has the same structure as Qd. In other words, MI for clamp
SFETQn1 has a p° type well region 2, a gate insulating film
6. Gate electrode 7. Consists of source region and drain region
be done. Source and drain regions each have low impurity content
High concentration n-type semiconductor region 10 and high impurity concentration n-type semiconductor region 10
It is composed of a semiconductor region 11. That is, M for clamp
I S F E T Q n 1 has a double drain structure
Consists of. As mentioned above, SRAMI has a memory cell MC.
, LDD structure for transfer MISFETQt, drive MIS
FETQd has two types of N-channel structures with double drain structure.
Adopts MISFET. Of these two types of n-channel MISFET structures,
The n-channel M I S F E T Q n of the side circuit is
Aims to increase operating speed and prevent fluctuations in threshold voltage
The LDD structure is adopted for this purpose. In addition, there is a static electricity damage prevention circuit.
MISFETQnl for clamping in Route I is resistant to electrostatic damage.
For the purpose of improving the pressure, the n-channel t of the above two types of structures
Of the rsFETs, 0 have a double drain structure.
In the case of the embodiment, for example, the n of the peripheral circuit that adopts the LDD structure
The electrostatic breakdown voltage of channel MISFETQn is approximately 30 [
V]. In contrast, the electrostatic breakdown prevention circuit
MISFE for clamps that adopts the double drain structure of I
The electrostatic breakdown voltage of TQn 1 is approximately 150 [V]
It will be done. The protective resistance element R of the electrostatic breakdown prevention circuit (■) is shown in the figure.
However, the conductivity formed in the 2Nth gate material formation step
It is composed of layer 13. This conductive layer 13 has a large number of layers as described above.
Laminated structure of crystalline silicon film 13A and high melting point metal silicide film 13B
The film is made of a thicker material than other gate materials.
Therefore, the current capacity of the protective resistance element R can be increased. One
Therefore, the protective resistance element R will be disconnected even if an excessive current flows.
become less likely to be In addition, the protective resistance element R has four layers of gates.
Among the materials (7, 13, 23 and 26), the thickest
The third conductive layer 23 can also be formed. In addition, the protective resistance element
The child R is made of any two of the four layers of gate material or
It may be configured with a laminated structure in which more than one layer is laminated. In addition, the protective resistance element R is a clamping MISFETQn
l, n channel M I S F E T Q n
A so-called extension of the same structure as any source or drain region.
It may also be configured as a diffused layer resistance element. The output stage circuit ■ of the peripheral circuit shown in FIG. 9 and the external
The electrostatic breakdown prevention circuit ■ placed between the terminal BP and
MISFET Qn4, Qn5 for lamps
As with the electrostatic breakdown prevention circuit (■) above, each of
Consists of rain structure. Adopting this double drain structure
Each of the clamp MISFETs Qn4 and Qn5 is static.
Electric breakdown voltage can be improved. Bipolar transistor B of the electrostatic breakdown prevention circuit (■)
The iT is configured of npn type as described above. This bipo
The n-type emitter region of the controller transistor BiT is for transfer.
In each of the source region and drain region of MISFETQt
It is composed of a certain n° type semiconductor region 8. Also, n-type
The transmitter region is the source region and drive MISFET Qd.
It is composed of n-type semiconductor regions 11, each of which is a rain region.
It will be done. The P-type base region is composed of a P-type well region 2.
Ru. The n-type collector region is composed of an n-type semiconductor substrate. In other words, the bipolar transistor BiT is an n-channel M
It can be constructed using the same manufacturing process as ISFETQn. Output n-channel MISFETQn2 of output stage circuit ■,
Each of Qn3 is the same as each of electrostatic breakdown prevention circuit I and ■.
Similarly, it is constructed with a double drain structure. This double dray
Output n-channel MISFET Qn2 that adopts a
, Qn3 can each improve the electrostatic breakdown voltage. similarly
, n-channel MISFETQn6 of output stage circuit ■ is double
Consists of a drain structure. That is, as shown in FIG.
In each of the input stage side shown in FIG. 9 and the output stage side shown in FIG.
M I S F E T Q that adopts a heavy drain structure
n is shown surrounded by a broken line. In this way, (D-1) the external terminal BP and MISFE
Input/output stage circuit (■ or ■) formed by T (Qn, Qp)
) for clamping MISFETQn (Qnl, or
Electrostatic breakdown prevention circuit (Qn4 and Qn5) formed by
MISF for driving the memory cell MC.
SRA consisting of ETQd and transfer MISFETQt
In M1, a MISFE for transfer of the memory cell MC
The TQt is configured with an LDD structure, and the driving MI
5FETQd is configured with a double drain structure, and the electrostatic
MI 5FE for clamping the air breakdown prevention circuit (■ or ■)
A drain region directly connected to the external terminal BP of TQn.
area (or source area), or n-channel for the output of the output stage circuit
The drain region of channel MISFET Qn2 (or Qn3
The source region) has a double drain structure. This structure
As a result of the configuration, the memory cell is
Mutual conductance of MISFET Qd for driving MC
compared to the mutual conductance of the transfer MISFETQt.
Therefore, the effective β ratio can be increased. By reducing the area occupied by the drive MISFETQd,
The area occupied by the MC can be reduced and the degree of integration of SRAMI can be improved.
In addition, compared to the LDD structure described above, static electricity damage is reduced.
MISFETQn for clamping of prevention circuit (I or ■)
The breakdown voltage at the pn junction in the drain region can be increased.
Therefore, the electrostatic breakdown voltage of the electrostatic breakdown prevention circuit (I or m)
or n-channel MIS for output of output stage circuit
Breakdown resistance at pn junction in drain region of FETQn2
Since the voltage can be increased, the electrostatic breakdown voltage of the output stage circuit can be increased.
It is possible to prevent electrostatic damage to the SRAM 1. Also,
By increasing the effective β ratio of the memory cell MC,
Information held in the information storage node area of Morisel MC
Improved stability reduces malfunctions of memory cells MC.
The operational reliability of the SRAM 1 can be improved. (D-4) Memory cell MC of the above configuration (D-3)
transfer MISFETQt, peripheral circuit MISFET (
Qn, Qp) each has an LDD structure, and the memory
MISFETQd for driving cell MC has a double drain structure
Consists of. With this configuration, the above configuration (D-1)
In addition to the effect, the MI 5FE of the LDD structure of the peripheral circuit
T (Qn, Qp) is a driving MISF with a double drain structure.
The electric field strength near the drain region is weaker than that of ETQd.
I can do it. Since the amount of hot carriers generated can be reduced,
Reduces fluctuations in threshold voltage of MISFETs over time
Therefore, the electrical reliability of SRAMI can be improved. The voltage shown in Figures 1, 2, 13 and 19 above
The source voltage line (Vcc) 26P is
It is connected to a power supply voltage wiring 33 (not shown). The power supply voltage line 26P is arranged on the memory cell MC, and
Since the Mori cell array MAY extends in the column direction, the
In the region of the X decoder circuit XDEC shown in Figure 3, the voltage
It is connected to the source voltage wiring 33. This connection structure is shown in Figure 22.
(Cross-sectional view of main parts). A power supply voltage that extends the memory cell array MAY in the column direction.
The ends of the voltage wire 26P and the power supply voltage wiring 33 are each a p-type half.
Connected via the conductor region 20 and the power supply intermediate wiring 29
Ru. Power supply voltage line 26P, one end of p' type semiconductor region 20
The connection with the interlayer insulating film 21 and 24 is made using
This is done through the connecting hole 25. Power supply voltage line 26P is connected
The other end of the p° type semiconductor region 20 is covered with an interlayer insulating film 27.
The power supply intermediate wiring 29 is inserted through the connection hole 28 formed in the
connected to. This power supply intermediate wiring 29 is formed using an interlayer insulating film.
The power supply in the upper layer is connected through the connection hole 31 formed in 30.
It is connected to the voltage wiring 33. In other words, the power supply voltage line 26P is
connected to the body region 20, and connected to this connected portion and another region.
The type semiconductor region 20 is drawn out, and the drawn out region is
Connecting the power supply intermediate wiring 2 to the P type semiconductor region 20,
Intermediate wiring for this power supply! 29 to the power supply voltage wiring 33.
Continued. The p° type semiconductor region 20 has a power supply voltage of 12
Connection with 6P (polycrystalline silicon film introduced with P-type impurities)
It has a conductivity type that does not form a pn junction. This P° type
The semiconductor region 20 is a p-channel MISFET of the peripheral circuit.
P type semiconductors in the source region and drain region of Qp
It is made of the same conductive layer as the region 20. Intermediate wiring for the power supply
A line 29 indicates an intermediate conductive layer disposed in the memory cell MC.
29. Main word line 29, sub word line 29, peripheral circuit
The conductive layer is made of the same conductive layer as each of the wiring lines 29 of the path. power supply
Although not shown, the pressure wiring 33 is connected from the external terminal BP to the peripheral circuit.
Supply voltage Vcc to each circuit in the circuit and memory block LMB.
This is the main power supply main line. This power supply voltage wiring 33
Complementary data line 33 extending memory cell array MAY
, are made of the same conductive layer as each of the wirings 33 of the peripheral circuit.
. As described above, the power supply voltage line 26P connects the memory cell M
N-type channel formation region 2 of C load MISFET Qp
This n-channel forming region is composed of the same conductive layer as 6N.
Because it reduces the amount of leakage current at 26N, it is made of thin film.
It will be done. In other words, the connection structure is formed in the interlayer insulating film 27.
A connection hole z8 is formed in the region of the power supply voltage line 26P.
, the power source intermediate conductive layer 29 is connected to the power source through this connection hole 28.
In the case of direct connection to the voltage line 26P, the connection hole
During etching (dry etching) to form 28,
It is possible to prevent the power supply voltage line 26P from coming off. Power-supply voltage
If wire 26P is disconnected, connect power supply voltage wire 26P and power supply intermediate
The connection area with the conductive layer 29 is extremely reduced and the resistance value increases.
or the power supply voltage line 26P and the power supply intermediate conductive layer 29
A poor connection occurs. Next, regarding the specific manufacturing method of the above-mentioned SRAM1,
Figures 23 to 32 (memory cells shown for each manufacturing process)
This will be briefly explained using a cross-sectional view of main parts of MC.

[Well formation process]

First, an n° type semiconductor substrate 1 made of single crystal silicon is prepared. Next, a silicon oxide film is formed on the main surface of the n-type semiconductor substrate 1. The silicon oxide film is formed, for example, by a thermal oxidation method, and has a thickness of approximately 40 to 50 [nm]. Next, a silicon nitride film is formed on the main surface of the p" type well region formation region of the n" type semiconductor substrate 1 via the silicon oxide film.This silicon nitride film serves as an impurity introduction mask and an oxidation-resistant mask. The silicon nitride film is used as, for example, CV
It is deposited by method D and has a thickness of about 40 to 60 [nm]. After the silicon nitride film is deposited, it is formed by patterning using photolithography technology. Next, using the silicon nitride film as an impurity introduction mask, an n-type impurity is introduced into the main surface of the n°-type well region formation region of the rectangular semiconductor substrate 1. For example, P is used as the n-type impurity. P uses the ion implantation method, and 1
1013 [a] with an energy of about 20 to 130 [KeV]
toms/tyl] is introduced. P is introduced into the main surface of the n-type semiconductor substrate 1 through the silicon oxide film. Next, a silicon oxide film is grown on the main surface of the n° type semiconductor substrate 1 in which the well region is to be formed. This silicon oxide film is grown by a thermal oxidation method using the silicon nitride film as an oxidation-resistant mask. The silicon oxide film is grown to a thickness of about 130 to 140 [nm]. Next, the silicon nitride film is removed. Then, using the grown silicon oxide film as an impurity introduction mask, a P type impurity is introduced into the main surface of the formation region of the P- type well region of the n-type semiconductor substrate 1. For example, B as a P-type impurity
Use F. BF. uses the ion implantation method, and with an energy of about 60 [KeV], 10" ml O" [atoi+s/cJ
It will be introduced to some extent. BF is n through the silicon oxide film.
It is introduced into the main surface of the ゛-type semiconductor substrate 1. Next, P introduced into the main surface of the n-type semiconductor substrate 1
The p-type impurity and the n-type impurity are each stretched and diffused, and the p-type impurity forms the p-type well region 2, and the n-type impurity forms the n-type well region 2.
Each of the mold well regions 3 is formed. The stretching diffusion of impurities is carried out for about 100 to 180 minutes at a high temperature of, for example, 1200 [''C]. By forming the p'' type well region 2 and the n'' type well region 3, a twin well An n" type semiconductor substrate 1 having the structure is completed.

[Step of Forming Element Isolation Region] Next, each of the silicon oxide film on the main surface of the p-type well region 2 and the silicon oxide film on the main surface of the n-type well region 3 of the n-type semiconductor substrate 1 is formed. remove. Next, the P' type well region 2. n-type well region 3
A new silicon oxide film is formed on each main surface. The silicon oxide film is formed by a thermal oxidation method, and has a thickness of about 10 to 15
It is formed with a film thickness of [nm]. Next, a silicon nitride film is formed on the main surface of each of the active region forming regions of the p° type well region 2 and the n′ type well region 3. The silicon nitride film is used as an impurity introduction mask and an oxidation-resistant mask. The silicon nitride film is deposited by, for example, a CVD method, and is formed to have a film thickness of about 100 to 150 [nml]. The silicon nitride film is formed by patterning it by photolithography after its deposition. During this patterning, that is, when removing the silicon nitride film by etching, the silicon nitride film is etched in a vertical shape, and the non-active regions exposed from the silicon nitride film are etched. Since the silicon oxide film or a portion thereof is removed, a new silicon oxide film is formed in this non-active region. This newly formed silicon oxide film is formed by, for example, a thermal oxidation method, and is
Formed with a film thickness of 14 [n ml]. This newly formed silicon oxide film is formed for the purpose of removing etching damage when patterning the silicon nitride film, preventing contamination when introducing impurities, and the like. In the formation region of the memory cell array MAY, the planar shape of the silicon nitride film is a ring shape corresponding to the planar shape of the active region shown in FIG. The planar shape of the silicon film is one of the transfer MISFETs of the four memory cells MC.
Total of 8 MISFs including Qt and drive MISFET Qd
It consists of ETs connected in series. In other words, the silicon nitride film has no termination in the direction in which the pattern extends, and has a ring shape in which the pattern is closed. This ring-shaped silicon nitride film is arranged in a staggered manner in the memory cell array MAY. Further, at the end of the memory cell array MAY, the planar shape of the silicon nitride film is formed in a half-ring shape and has a margin, as shown in FIG. Further, at the end of the memory cell array MAY and at the corner of the memory cell array MAY, the planar shape of the silicon nitride film is one quarter of the ring shape, that is, the memory cell MC
One of the transfer MISFETQt and the drive MISFE
It is formed in an L-shape which is the planar shape of the active region of TQd. Since this one-quarter ring shape of the silicon nitride film has terminations in both directions in which the pattern extends, two extra dimensions are added. Next, using the silicon nitride film as an impurity introduction mask, a P-type impurity is introduced into the formation region of the inactive region (element isolation region) of the p-type well region 2. For example, BF2 is used as the P-type impurity. BF2 is introduced into the main surface of the P-type semiconductor substrate 2 through the silicon oxide film using an ion implantation method, and about 10" to 1013 atoms#jl are introduced at an energy of about 40 KeV. Next, using the silicon nitride film as an oxidation-resistant mask,
A silicon oxide film is grown on the main surface of each non-active region of the '-type well region 2n-type well region 3, and an element isolation insulating film 4 is formed. The element isolation insulating film 4 is formed by, for example, a thermal oxidation method (
It is formed of a silicon oxide film formed by a selective thermal oxidation method, and has a thickness of about 400 to 500 [nm]. As described above, in the memory cell array MAY, the planar shape of the silicon nitride film used as an oxidation-resistant mask when forming the element isolation insulating film 4 is ring-shaped. The inner frame side and the outer frame side of the ring shape of the silicon nitride film, that is, the boundary area between the active region and the non-active region, are formed between the silicon nitride film and the P- type well region 2 to the active region of the P" type well region 2. Since oxygen is supplied to the side main surface, the silicon oxide film under the silicon nitride film grows, and a so-called bird's beak (lateral oxidation) occurs at the end of the element isolation insulating film 4. In the direction in which the ring-shaped pattern of the silicon film extends, the pattern has no termination and is closed.
Since there is no oxygen supply, the element isolation insulating film 4 is not formed and bird's beaks do not occur.Also, since the pattern of the silicon nitride film is ring-shaped in the boundary region between the active region and the inactive region, the pattern is not terminated. The length of the bird's beak is shorter than when it has . Further, at the end of the memory cell array MAY, the planar shape of the silicon nitride film used as an oxidation-resistant mask when forming the element isolation insulating film 4 is a half ring shape and has a margin. Since oxygen is supplied to the boundary area between the inner frame side and the outer frame side of the half-ring shape of this silicon nitride film,
A silicon oxide film under the silicon nitride film grows, forming an element isolation insulating film 4.
A bird's beak appears at the end of the Similarly, the end of the half-ring-shaped pattern of the silicon nitride film in the direction in which it extends (the end of the memory cell array MAY or the dotted line E) is the same as the inner frame side and the outer frame side, respectively. Therefore, a bird's beak occurs when the element isolation insulating film 4 is formed. When a bird's beak occurs, the memory cell array M
The planar shape of the active region of the memory cell MC located at the end of the memory cell array MAY is reduced by an amount corresponding to the amount of bird's beak generated compared to the planar shape of the active region of the memory cell MC located at the center of the memory cell array MAY. , since a margin is provided, the results are almost the same. In other words,
The margin dimension is set to be at least the same as or larger than the amount of bird's beak generation. Also, at the end of the memory cell array MAY, the memory cell array M
Since the planar shape of the active region of the memory cell MC located at the corner of AY is provided with a margin as described above, the planar shape of the active region of the memory cell MC located at the center of the memory cell array MAY is is formed equivalently to In the heat treatment step for forming the element isolation insulating film 4, the p-type impurity introduced into the non-active region is stretched and diffused, and a p-type channel stopper region 5 is formed. In this way, (C-26) p-type well region (substrate) 2
A transfer MISFET Qt is placed on the main surface of the active region surrounded by the element isolation insulating film 4 formed in the non-active region of
In an SRAMI in which a memory cell MC is constituted by a driver MISFET Qd and a driving MISFET Qd, on the main surface of the active region forming region of the p well region 2, spaced apart from each other and regularly,
A process of arranging a plurality of oxidation-resistant masks (silicon nitride films) each having a ring-shaped planar shape, and using the oxidation-resistant masks to selectively cover the main surface of the inactive region of the p° type well region 2. The method also includes a step of forming an element isolation insulating film 4 using an oxidation method. With this configuration, in the oxidation-resistant mask whose planar shape is a ring shape, the boundary area between the active region and the non-active area exists on the inner frame side and the outer frame side which are opposite to each other in the ring shape. A bird's beak is generated when forming the element isolation insulating film 4 using the selective oxidation method, but the length of this bird's beak is determined by the length of the bird's beak because the oxidation-resistant mask is formed in a ring shape and has no termination. It is shorter than when it has . In addition, in the direction in which the ring-shaped oxidation-resistant mask pattern extends, the pattern is closed, that is, there is no end to the pattern, and the boundary region does not exist, so there is no reduction in the area occupied by the active region due to the occurrence of bird's beaks. Since the element isolation insulating film 4 has a ring shape in this manner, the amount of dimensional conversion of the active region pattern can be reduced in the manufacturing process of the SRAM 1. Reducing the amount of dimensional conversion of the pattern enables fine processing, so
The degree of integration of MI can be improved. (C-27) In the memory cell array MAY, the oxidation-resistant mask of the above structure (C-26) is provided on the main surface of the active region forming region of the p-type well region 2, spaced apart from each other and in the column direction. A plurality of pieces are arranged in a row at the same pitch, and in the next column in the row direction intersecting the column direction of this arrangement, the pieces are spaced apart from each other and are arranged at the same pitch in the column direction, but 2 times with respect to the previous row arrangement. A plurality of them are arranged in a row, shifted by one-tenth of a pitch. With this configuration, the oxidation-resistant masks are arranged in a staggered manner, and the distance between adjacent oxidation-resistant masks in each of the column and row directions can be made uniform and minimized, so that the oxidation-resistant masks are arranged in a staggered manner. can be enhanced. In other words, the element isolation insulating film 4 between the oxidation-resistant masks
The area occupied by the SRAMI can be reduced and the degree of integration of the SRAMI can be improved. (C-28) The memory cell MC of the configuration (C-27) is composed of two transfer MISFETQt and two drive MISFETQd, and the ring shape of the oxidation-resistant mask (silicon nitride film) is as follows: Two memory cells MC adjacent in the column direction and two memory cells MC adjacent to these two memory cells MC in the row direction, a total of four memory cells M
In C, one transfer MISFETQt and one drive MISFETQd, a total of four transfer MISFETs.
SFETQt and four driving MISFETQd are connected in series. With this configuration, among the total of four memory cells MC adjacent to each other in the column direction and the row direction, one semiconductor of each of the four transfer MISFETs Qt and the four driving MISFETs Qd, a total of eight MISFETs. The region can be formed integrally with the other semiconductor region of another MISFET and can be used also. As a result,
The memory cell MC corresponds to the dual-purpose semiconductor region.
The area occupied by the SRAM 1 can be reduced and the degree of integration of the SRAM 1 can be improved. In addition, (C-29) the above configurations (C-26) to (C-2
Among the regularly arranged oxidation-resistant masks in 8), the oxidation-resistant mask (silicon nitride film) arranged at the end of the memory cell array MAY is formed by a part of the ring shape formed based on the layout rule ( (formed in the shape of the dotted line E shown in FIG. 15), the oxidation-resistant mask arranged at the end has a boundary region with the inactive region in the direction in which the ring-shaped pattern extends, at least with a dimension corresponding to the bird's beak. (provide extra dimensions),
With this configuration, a margin is formed in advance in the oxidation-resistant mask arranged at the end of the memory cell array MAY, so that in the manufacturing process of the SRAM1, the active region in the central part of the memory cell array MAY and the end of the memory cell array MAY It is possible to reduce the difference in the amount of dimension conversion of the pattern between the active region and the active region. That is, the electrical characteristics of the memory cells MC can be made uniform within the memory cell array MAY (including the central portion and the terminal portion), and the electrical reliability of the SRAMI can be improved. The element isolation insulating film 4 and the p-type channel stopper region 5
After forming the silicon nitride film used as an oxidation-resistant mask, the silicon nitride film is removed. [Step of Forming First Gate Insulating Film] Next, the silicon oxide film on the main surfaces of the active regions of each of the p'-type well region and n-type well region 3 is removed. By the process of removing this silicon oxide film, the p-type well region 2
, the main surfaces of the active regions of the n'' type well region 3 are exposed.Next, silicon oxide is newly deposited on the main surfaces of the active regions of the p° type well region 2 and the W type well region 3. The silicon oxide film is mainly used to prevent contamination when introducing impurities, and to remove the so-called white ribbon of the silicon nitride film at the end of the element isolation insulating film 4 that cannot be removed when the silicon nitride film is removed. The silicon oxide film is formed by, for example, a thermal oxidation method, and has a thickness of about 18 to 2
It is formed with a film thickness of 0 [nm]. Next, impurities for threshold voltage adjustment are introduced into the main surface portions of the active regions of the P' well region 2 and the N' type row well region 3, respectively. An n-type impurity such as BF2 is used as the threshold voltage adjusting impurity. This BF2 uses the ion implantation method and is produced at approximately 2×10” to 3×101′” [atoms/a#] at an energy of about 40 to 50 [K e V].
introduced to some extent. BF2 is introduced into the main surfaces of the P semiconductor substrate 2 and the π type well region 3 through the silicon oxide film. Next, the silicon oxide film on the main surface of the active region of each of the P-type well region 2 and the n-type well region 3 is removed, and
The main surfaces of the active regions of the °-type well region 2 and the n-type well region 3 are exposed. After this, as shown in Figure 23,
A gate insulating film 6 is formed on the main surface of the active region of each of the P<-> type well region 2 and the N<-> type low well region 3. The gate insulating film 6 is formed by a thermal oxidation method and has a thickness of about 13 to 14 [n
ml of film thickness. The gate insulating film 6 is connected to the drive MISFETQd of the memory cell MC and the electrostatic breakdown prevention circuit 1. It is used as the gate insulating film of each MISFETQn of the output stage circuit (2) and (2). [Step of Forming First Layer Gate Material] Next, a polycrystalline silicon film 7 is deposited over the entire surface of the substrate including on the gate insulating film 6. This polycrystalline silicon film 7 is formed in the step of forming the first layer of gate material. The polycrystalline silicon film 7 is deposited by the CVD method, and is formed of so-called doped polysilicon into which impurities are introduced to reduce the resistance value during the deposition. This polycrystalline silicon film 7 is made of disilane (S
It is deposited by a CVD method using i2H, ) and phosphine (PH, ) as source gases. For example, in the case of this example, the CVD method uses Si, H. Approximately 80 [5ccii] and about 1[ccii] as carrier gas.
%] of nitrogen gas is about 90 [sccm], and the temperature is about 500 to 520['C] and 0.8C.
Under these conditions, the polycrystalline silicon film (doped polysilicon) 7 is produced based on the following production reaction formulas <1> to <3>. 2 Si H, book + 2P umbrella → 2Si(P) + 2H,・
...3> In the case of this embodiment, P, which is an n-type impurity, is introduced into the polycrystalline silicon film 7, and P is about 1020 to 1021
It is introduced at a concentration of [ato■s/aJ]. Furthermore, when the polycrystalline silicon film 7 is used as the gate electrode of the MISFET and the first electrode of the capacitive element C, it is formed to have a relatively thin film thickness of about 100 nm. This polycrystalline silicon film) is used as the first electrode (7) of the capacitive element C as described above, and a dielectric film (21) is formed on the polycrystalline silicon film 7. The dielectric strength voltage changes depending on the method of forming the polycrystalline silicon film 7. Figure 33 (
Figure 2) shows the results of measuring the dielectric breakdown voltage of the insulating film formed on top of each of the polycrystalline silicon films deposited using two different formation methods. 33rd
In the figure. The horizontal axis indicates the formation temperature ['C] of a thermally oxidized silicon film formed on a polycrystalline silicon film. The vertical axis shows the dielectric strength voltage [M V / al ] of the insulating film (dielectric film). Data (A) is the polycrystalline silicon film (doped This figure shows the dielectric breakdown voltage of a silicon oxide film formed by thermal oxidation on polysilicon. Data (B
), P is introduced by ion implantation into a polycrystalline silicon film (non-doped polysilicon) deposited by CVD method, and then an insulating silicon oxide film is formed on the polycrystalline silicon film by thermal oxidation method. Indicates pressure resistance. Data (C) shows the dielectric strength voltage of a silicon oxide film deposited by CVD on a polycrystalline silicon film (doped polysilicon) deposited by CVD using Si, H, as a source gas. The deposition temperature of the silicon oxide film deposited by the CVD method is about 800 ['C]. As shown in the measurement results in FIG. 33, when a silicon oxide film is formed by a thermal oxidation method at the same formation temperature, oxidation on a polycrystalline silicon film deposited by a CVD method using Si, H, as a source gas is The silicon film (A) has a higher dielectric strength voltage than the silicon oxide film (B) on a polycrystalline silicon film into which P is introduced after deposition. Also,
In the case of the polycrystalline silicon film deposited by the CVD method using Si, H, as the source gas, the silicon oxide film (C) deposited by the CVD method is more expensive than the silicon oxide film (A) deposited by the thermal oxidation method.
has a high dielectric strength. The changes in the dielectric strength voltage of the silicon oxide film mentioned above are shown in FIGS. 34 and 3.
As shown in the measurement results in Figure 5 (a diagram showing the surface roughness of the polycrystalline silicon film), it is estimated that this is based on the surface condition of the polycrystalline silicon film. Figure 34 shows C using 5i2H1 as the source gas.
FIG. 35, which shows the surface state of a polycrystalline silicon film deposited by the VD method, shows the surface state of a polycrystalline silicon film into which P is introduced after being deposited by the CVD method. In each of FIGS. 34 and 35, the horizontal axis shows the distance [μm] on the surface of the polycrystalline silicon film, and the vertical axis shows the undulations (roughness) [K people] on the surface. As shown in the measurement results of FIGS. 34 and 35, Si,
The surface of a polycrystalline silicon film deposited by the CVD method using H, as a source gas has higher flatness than the surface of a polycrystalline silicon film into which P is introduced after deposition. A polycrystalline silicon film deposited by a gaseous CVD method is shown in FIG. Since the surface has small undulations (small irregularities) and the occurrence of electric field concentration can be reduced, the dielectric breakdown voltage of the silicon oxide film formed by the thermal oxidation method on this polycrystalline silicon film can be improved. In other words, the capacitive element C described above is a polycrystalline silicon film deposited by the CVD method using Si, H, as a source gas, and the first electrode (
By forming 7), the dielectric breakdown voltage of the dielectric film can be improved. In addition, the silicon oxide film formed by the thermal oxidation method has a plurality of crystal grains (grains) with different crystal planes on the surface of the underlying polycrystalline silicon film. Since the growth rates are different, variations in film thickness occur. When this silicon oxide film with variations in film thickness is used as a dielectric film of the capacitive element C, an electric field is concentrated between the first WL pole (7) and the second electrode (23) in the thin part of the film. Therefore, as shown in FIG. 33, the M-edge breakdown voltage is lower than that of a silicon oxide film deposited by the CVD method. In other words. As shown in FIG. 33, the silicon oxide film deposited by the CVD method can be formed on the polycrystalline silicon film with a uniform thickness along the underlying shape, so it can be used as a dielectric film of the capacitive element C. When used, the occurrence of electric field concentration can be reduced and the dielectric strength voltage can be improved. In addition, as shown in FIG. 36 (a diagram showing the relationship between the thickness of the polycrystalline silicon film and the dielectric strength voltage of the gate insulating film), the polycrystalline silicon film is formed as an insulating film depending on the formation method and the deposited film thickness. changes the dielectric strength of the In FIG. 36, the horizontal axis shows the film thickness [nm] of the polycrystalline silicon film, and the vertical axis shows the insulation of the insulating film (silicon oxide film: corresponding to the gate insulating film 6, for example) underlying the polycrystalline silicon film. Data showing breakdown voltage [MV/C1l]
(D) shows the dielectric strength voltage of the insulating film underlying the polycrystalline silicon film deposited by the CVD method using 5i2H as the source gas.
Data (E) shows the dielectric strength voltage of the insulating film underlying the polycrystalline silicon film into which P is introduced after deposition. As shown in data (E) in FIG. 36, the insulating film underlying the polycrystalline silicon film into which P is introduced after deposition has a dielectric breakdown voltage when the polycrystalline silicon film has a thickness exceeding 70 [nm]. Although no deterioration occurs, when the film thickness becomes 70 [nm] or less, the dielectric strength deteriorates rapidly. On the other hand, as shown in data (D), Si, H. The insulating film underlying the polycrystalline silicon film (doped polysilicon) is deposited by the CVD method using as a source gas. Even if the polycrystalline silicon film has a thickness of 70 [nm] or less, there is almost no deterioration in dielectric strength.In other words, this polycrystalline silicon film has a dielectric strength that is lower than the dielectric strength of the underlying insulating film (for example, the gate insulating film 6). Since it does not deteriorate, it can be formed with a thin film thickness of 70 [nm] or less. In addition, when the thickness of a polycrystalline silicon film approaches the size of the crystal grains, the flatness of one surface is determined by the shape of the crystal grains and is impaired (the film thickness is not uniform), resulting in disconnection and other defects. Since it is easy to use and cannot be used as a conductive layer, approximately 1
Formed with a film thickness of 0 [nm3 or more. Additionally, as a method of introducing impurities into polycrystalline silicon films, CVD
There is a method in which a phosphorus glass film is formed on the surface of a polycrystalline silicon film (non-doped polysilicon) deposited by a method, and the P contained in this phosphorus glass film is introduced into the polycrystalline silicon film by a thermal diffusion method. . This impurity introduction method uses hydrofluoric acid to remove the phosphorus glass film. The polycrystalline silicon film deposited by the above-mentioned CVD method using Si, H, as a source gas does not require the use of hydrofluoric acid for the removal of the phosphorus glass film, and moreover, the polycrystalline silicon film deposited by other deposition methods Since the film quality can be formed denser than that of a silicon film, it is possible to prevent deterioration of the dielectric strength of the underlying insulating film (for example, the gate insulating film 6) due to the seepage of the hydrochloric acid into the film. For the reasons mentioned above, the polycrystalline silicon film 7 formed in the step of forming the first layer of gate material is coated with the upper layer or the underlying layer to the extent that the operating speed is not impaired when used as a gate electrode of a MISFET, etc. Since the dielectric strength voltage of the insulating film can be ensured, the film thickness can be reduced to about 100 [nm] and the upper layer can be made flat. After forming the polycrystalline silicon film 7 formed in the step of forming the first layer of gate material, this polycrystalline silicon film 7 is subjected to heat treatment. This heat treatment is performed, for example, in nitrogen (N2) gas for 70
It is carried out for about 8 to 12 minutes at a temperature of 0 to 950 ['C],
The P introduced into the polycrystalline silicon film 7 is activated and the film quality is stabilized. Next, an insulating film 8 is formed on the entire surface of the substrate including the top of the polycrystalline silicon film 7.
Form A. The insulating film 8A is mainly used for MIS for transfer which will be described later.
It is used as an oxidation-resistant mask in the thermal oxidation process for forming the gate insulating film (12) of FETQt. This insulating film 8A
is formed of a silicon nitride film deposited by CVD. This silicon nitride film cannot be used as an oxidation-resistant mask if the thickness is less than 3 [nm], so it is formed with a thickness of 3 [nm] or more. In addition, the silicon nitride film has a thickness of 10 [nm] in order to suppress the growth of stepped shapes and to flatten the upper layer.
Form with the following thin film thickness. In other words, the silicon nitride film has 3
It is formed with a film thickness of ~10[nml], and in this example, it is 8[nml].
The film is formed with a film thickness of nm]. Next, an insulating film 8 is formed over the entire surface of the substrate including the top of the insulating film 8A. The insulating film 8 electrically isolates the lower polycrystalline silicon film 7 and the upper conductive layer (13). The insulating film 8 is made of inorganic silane (S i H4 or S i H,
A silicon oxide film is deposited by a CVD method using CI□ as a source gas and nitrogen oxide (N, O) gas as a carrier gas. The silicon oxide film is deposited at a temperature of about 800[° C.]. The insulating film 8 is formed to have a thickness of about 120 to 140 [nm]. Next, the insulating film 8.8A and the polycrystalline silicon film 7 are each sequentially patterned to form a gate electrode 7 from the polycrystalline silicon film 7, as shown in FIG. Patterning uses photolithography technology, for example RIE.
This is done using anisotropic etching such as etching. Gate electrode 7 is M for driving
It is configured as a gate electrode of ISFETQd. Also,
Gate electrode 7 is MI for clamping of electrostatic breakdown prevention circuit I.
SFETQn1. M for clamping static electricity damage prevention circuit■
ISFETQn4, Qn5. Output n-channel MISFETQn2 of output stage circuit ■. Qn3, n channel MI
It is used as the gate electrode of each of S F E T Q n 6. (First step of forming the first source region and drain region,
Sidewall spacers 9 are formed on the sidewalls of the gate electrode 7 and the insulating film 8. Side wall spacer 9 is
depositing a silicon oxide film on the entire surface of the substrate including on the insulating film 8;
It is formed by etching the entire surface of this silicon oxide film by an amount corresponding to the thickness of the deposited film. As described above, the silicon oxide film is formed using carbon dioxide using inorganic silane gas as a source gas.
It is deposited by the VD method, and is formed to have a film thickness of, for example, 140 to 160 [nm]. For etching, anisotropic etching such as RIE is used. Next, during etching to form the sidewall spacers 9, the active regions of the p-type well region 2 and the go-type well region 3 in regions other than the gate electrode 7 and the sidewall spacer 9 are etched. Since the main surface is exposed,
A silicon oxide film (no reference numeral) is formed on this exposed region. This silicon oxide film is mainly used for the purpose of preventing contamination during the introduction of impurities and preventing damage to the main surface of the active region due to the introduction of impurities. The silicon oxide film is formed, for example, by a thermal oxidation method, and has a thickness of about 10 [nm]. Next, transfer MISFETQ of memory cell array MAY
t, in the formation region of each of the n-channel MISFETQn and p-channel MISFETQp of the peripheral circuit (excluding the formation region of the double drain structure), an impurity introduction mask 40 is applied.
form. In the memory cell array MAY, the impurity introduction mask 40 is formed outside the region indicated by the symbol DDD in FIG. 10 and surrounded by the dashed line. The impurity introduction mask 40 is formed of, for example, a photoresist film formed by photolithography. Next, using the impurity introduction mask 40, two types of n-type impurities are introduced into the main surface of the p-type well region 2 in the formation region of the driving MISFET Qd of the memory cell array MAY. These two types of n-type impurities are produced by the same manufacturing process in the electrostatic breakdown prevention circuit 1.11I and the output stage circuit.
n-channel MIS that adopts a double drain structure for each
It is also introduced into the main surface of the P'' type well region 2 in the FETQn formation region. One of the n-type impurities is P, and the other is As, which has a slower diffusion rate than P. P is approximately 30 [K
About 10 ”[atoms/
aJ] degree is introduced. As is produced by using the ion implantation method, with an energy of about 40 [KeV] and about 10" [at
o+ms/aJ] degree is introduced. When introducing each of P and As, together with the impurity introduction mask 40,
Sidewall spacers 9 formed on the side walls of gate electrode 7 are also used as impurity introduction masks. After introducing each of P and As, the impurity introduction mask 40 is removed. Next, the two types of n-type impurities, P and As, are each subjected to stretch diffusion, as shown in FIG. 25. An n-type semiconductor region 10 with a low impurity concentration of P and an n°-type semiconductor region 11 with a high impurity concentration of As are formed. The n-type semiconductor region IO and the n°-type semiconductor region 11 are
Since the diffusion rates of each n-type impurity are different, a double drain structure is formed. n-type semiconductor region 10, n. Each type semiconductor region 11 is provided with a sidewall spacer 9
is used as an impurity introduction mask, so the driving MIS
In the FETQd formation region, the amount of diffusion toward the channel formation region is regulated by the sidewall spacer 9. In other words, each of the n-type semiconductor regions 1O1 and n°-type semiconductor regions 11 can be diffused toward the channel formation region side by an amount corresponding to the film thickness of the sidewall spacer 9, compared to the case where the gate electrode 7 is used as an impurity introduction mask. The amount can be reduced. This reduction in the amount of diffusion toward the channel forming region is achieved by the driving M
Since the effective gate length (channel length) of the ISFETQd can be ensured, the short channel effect of the ISFETQd for dynamic operation can be prevented. Through the process of forming each of the n-type semiconductor regions 1O1 and n°-type semiconductor regions 11, a driving MISFET Qd that employs a double drain structure of the memory cell MC in the memory cell array MAY is completed. In addition, through the same manufacturing process, the electrostatic breakdown prevention circuit 1.1
MISFETs Qnl to Qn6 each employing a double drain structure for 1I and output stage circuit 2 are completed. In this way, (D-2) external terminal BP and MISFET
MISFET (
Qnl, Qn4. An electrostatic breakdown prevention circuit (I, ■) formed by Qn5) is arranged, and the memory cell MC is
S consisting of SFETQd and transfer MISFETQt
In RAMI, MIS for driving the memory cell MC
FETQd, a MISFET (Qnl, Q
n4, Qn5) or a MISFET (Qn2゜Q n
3, Qn6) and a step of forming a transfer MISFET Qd of the memory cell MC. With this configuration, the electrostatic breakdown prevention circuit (I,
■) MISFETs (Qnl, Qn4.Qn5) or MISFETs (Qn2.Qn3.
Qn6), the number of manufacturing steps in the SRAMI manufacturing process can be reduced by the amount corresponding to the step of forming the MISFET of the electrostatic breakdown prevention circuit or the MISFET of the input/output stage circuit.

[Step of forming the second gate insulating film] Next, the transfer MISFETQ of the memory cell array MAY is
t, p° type well region 2.t, in each formation region of n-channel MISFETQn and p-channel MISFETQp of the peripheral circuit. A threshold voltage adjusting impurity is introduced into the main surface of each active region of the n" type well region 3. As the threshold voltage adjusting impurity, a p type impurity such as BF,
use. BF is approximately 40 [KeV] using the ion implantation method.
Approximately 10” [atoms/cffl
It will be introduced to some extent. BF is introduced into the main surfaces of each of the p° type well region 2 and the n− type well region 3 through a silicon oxide film, which is not labeled, and is formed on the main surface of the active region. Next, the transfer MISFE of the memory cell array MAY
TQt, peripheral circuit n-channel MI 5FETQn,p
In each formation region of channel MISFETQp,
The silicon oxide film on the main surfaces of the active regions of each of the p-type well region 2 and the n-type well region 3 is removed to expose the main surfaces. Next, this exposed P-type well region 2. A gate insulating film 12 is formed on the main surface of each active region of the n-type well region 3.
form. The gate insulating film 12 is formed by a thermal oxidation method,
The film is formed to have a thickness of about 13 to 14 [nm]. The gate insulating film 12 is connected to the transfer MISFETQt of the memory cell MC.
, is used as a gate insulating film for n-channel MISFETQn and p-channel MISFETQp in peripheral circuits. In the thermal oxidation process for forming this gate insulating film 12, the gate electrode 7 of the driving MISFET Qd (other MISFET
The upper surface portions of the FETs Qrxl to Qn6 are covered with the insulating film 8A, and this insulating film 8A is used as an oxidation-resistant mask. The gate electrode 7 is surrounded by an insulating film (silicon oxide film) 8 and a sidewall spacer 9, but since oxygen is supplied during the thermal oxidation process, the insulating film 8A
If not provided, it will be oxidized. In this oxidation, the oxidation rate of the upper surface portion of the gate electrode 7 is faster (rapidly oxidized) than the upper corner portion 8B of the gate electrode 7 (the area surrounded by the dotted line shown in FIG. 26). Therefore, silicon in the surface portion is eaten away to a greater extent than in the corner portion 8B, and the corner portion 8B of the gate electrode 7 is turned up. In other words, a silicon oxide film is grown on the upper surface portion of the gate electrode 7, which is thicker than that on the corner 8B and has an unclear thickness. Insulating film (silicon nitride film) 8A
This can reduce the curling of the gate electrode 7. [Step of Forming Second Nth Gate Material] Next, a polycrystalline silicon film 13A is deposited over the entire surface of the substrate including the top of the gate insulating film 12. This polycrystalline silicon film 13A is formed in the second layer gate material forming step. Similar to the polycrystalline silicon film 7, the polycrystalline silicon film 13A is made of 5i2H.
In this embodiment, the polycrystalline silicon film 13A is deposited by the CVD method using , and PH as source gases.
P is introduced to a concentration of 0" [atoms/cD. As described above, the polycrystalline silicon film 13A can improve the dielectric strength voltage of the underlying #1! edge film, that is, the gate insulating film 12, and
As the gate material for the layer, a high melting point metal silicide film (1
3B) can reduce the substantial resistivity value, which is considered impossible with polycrystalline silicon films in which P is introduced after deposition.7Q[
It can be formed with a thin film thickness of not more than n rr+]. That is,
The polycrystalline silicon film 13A needs to have a film thickness of lo [nm1 or more, so that crystal grains do not affect the uniformity of the film thickness.
It is formed with a thin film thickness of 10 to 100 [nml]. Next, the polycrystalline silicon film 13A is subjected to heat treatment. This heat treatment is performed, for example, in nitrogen gas at a temperature of 700 to 950 [
The process is carried out for about 15 to 25 minutes at a temperature of "C" to activate P introduced into the polycrystalline silicon film 13A and to stabilize the film quality. On the source regions (10 and 11), the polycrystalline silicon film 13A and the underlying gate insulating film 12 are sequentially removed to form a connection hole 14.The connection hole 14 is formed by photolithography. For example, RI using a photoresist film (etching mask).
It is formed by anisotropic etching such as E. This connection hole! 4 connects the source region of the driving MISFET Qd and the reference voltage line (13), respectively. Clean gate insulating film 12
After forming the polycrystalline silicon film 13A, the polycrystalline silicon film 13A is formed directly on the gate insulating film 12, and the contact hole 14 is formed after this, so that the photoresist film forming the contact hole 14 is in direct contact with the gate insulating film 12. No, that is, this connection hole 1
4 does not cause contamination of the gate insulating film 12 due to the formation and peeling of the photoresist film, so the dielectric strength voltage of the gate insulating film 12 does not deteriorate. Next, a high melting point metal silicide film 13B is formed over the entire surface of the substrate including the polycrystalline silicon film 13. This high melting point metal silicide film 1
3B is formed in the step of forming the second layer gate material. A part of the high melting point metal silicide film 13B is connected to the source region of the driving MISFETQd through the connection hole 14. The high melting point metal silicide film 13B is formed of WSi deposited by CVD or sputtering. WSi2 is a highly stable gate material for mass production. Since the high melting point metal silicide film 13B has a specific resistance value smaller than that of the polycrystalline silicon film 13A, it also has a specific resistance value of about 80 to 100 [
The film is formed with a relatively thin film thickness of [nm]. Next, an insulating film 15 is formed on the entire surface of the substrate including the high melting point metal silicide film 13B. This insulating film 15 has a thicker thickness than the insulating film 8 on the gate electrode 7, for example, 200 to 300 nm.
It is formed with a film thickness of 0.00 [nm]. In other words, even if the insulating film 8 on the gate electrode 7 is etched away when forming the connection hole (22) described later, the insulating film 15 on the gate electrode (13) remains, and this Gate electrode (1
3) The upper conductive layer (23) is formed to a thickness that provides insulation for each of the upper conductive layers (23). The insulating film 15 is made of, for example, organic silane (S
x (OC2H3)4) as a source gas, high temperature (e.g. 700 to 850 [°C]), low pressure (e.g. 1
, 0 [torr] is formed using a silicon oxide film deposited by the CVD method. Next, 1M-order patterning is performed on each of the insulating film 15, high melting point metal silicide film 13B, and polycrystalline silicon film 13A,
As shown in FIG. 26, the gate electrode 1 has a laminated structure composed of a polycrystalline silicon film 13A and a high melting point metal silicide film 13B.
form 3. The gate electrode 13 is connected to the transfer MISFETQt of the memory cell MC, and the n-channel MISFE of the peripheral circuit.
It is used as the gate electrode of TQn and p-channel MISFETQp. Furthermore, the word line (W L ) 13 and the reference voltage line (Vss) 13 are formed in the same manufacturing process as the process of forming the gate electrode 13. The patterning is performed by anisotropic etching such as RIE using an etching mask formed by photolithography.

[First step of forming the second source region and drain region,
MI for transfer of memory cell MC of memory cell array MAY
SFETQt, peripheral circuit n-channel MISF
In each formation region of E T Q n, an n-type impurity is introduced into the main surface of the active region of the P° type well region 2 . This n-type impurity is an n-type impurity with a low impurity concentration in the LDD structure.
P is introduced for the purpose of forming the type semiconductor region (17) and has a gentler impurity concentration gradient than As in order to weaken the electric field strength near the drain region. P is introduced using an ion implantation method at an energy of about 30 [KeV] to the extent of about 1X10'' [atoms/aJ].P is introduced using the gate electrode 13 as an impurity introduction mask, and the gate electrode 13 is used as an impurity introduction mask. 13 in a self-aligned manner. After that, a heat treatment is performed, and the P is stretched and diffused to form an n-type semiconductor region 17 (see FIG. 27). Ar) Medium, 900-1000
The process is carried out at a high temperature of [°C] for about 20 [minutes]. Based on this heat treatment, the amount of diffusion of the n-type semiconductor region 17 toward the channel forming regions of the transfer MISFETQt and the n-channel MISFETQn increases, and after the manufacturing process is completed, the amount of diffusion in the n-type semiconductor region 17 increases to about 0.5 [μm] or more. It overlaps with the gate electrode 13 with a dimension of . The n-type semiconductor region 17 is connected to a transfer MISFETQ, which will be described later.
Since more heat treatment is performed compared to the n° type semiconductor region (18) with high impurity concentration of each of the t and n channel MISFETQn, the ratio of the diffusion amount is smaller than that of the n° type semiconductor region (18). becomes larger. As shown in the measurement results in FIG. 37 (a diagram showing the relationship between the length of the LDD section and the amount of drain current), as the amount of overlap between the n-type semiconductor region (LDD section) 17 and the gate electrode 13 increases, The amount of drain current increases. In FIG. 37, the horizontal axis indicates the length Ln [μm] of the n-type semiconductor region (LDD portion) 17 in the gate length direction. The vertical axis indicates the drain current amount [mA] of the n-channel MI employing the LDD structure used in the measurement shown in Fig. 37.
SFET has a gate length L/gate@W ratio of 0.5 [μm
/10 μml. Further, the thickness of the gate insulating film (silicon oxide film) is 10 [nm], and the drain voltage Vd and gate voltage Vg are both 5 [V]. The n-type semiconductor region 17 has an impurity concentration of I x 10'' [atoois/aJ] and an impurity concentration of 5 x 10'' [ato+*s/aJ]. Further, the amount of drain current is measured when the n-type semiconductor region 17 and the gate electrode 13 overlap and when they do not overlap. As shown in the measurement results in FIG. 37, for any impurity concentration, as the length Ln of the n-type semiconductor region 17 increases, the parasitic resistance in the gate length direction of the n-type semiconductor region 17 increases, and the drain The amount of current is reduced. However, in any case of impurity concentration, the n-type semiconductor region 17
teeth. When overlapped with the gate electrode 13, the parasitic resistance is reduced due to the electric field effect from the gate electrode 13, so that the amount of drain current increases. In particular, when the impurity concentration of the n-type semiconductor region 17 is I x 10'' [atoms/cj, the increase in the amount of drain current is large. ), as shown in the measurement results of the n-type semiconductor region (L
As the amount of overlap between the DD portion) 17 and the gate electrode 17 increases, the electric field strength is reduced. In FIG. 38, the horizontal axis is the length Ln [μm] of the n-type semiconductor region 17 in the gate length direction.
shows. The vertical axis indicates electric field strength (×10 [V/cm]). The n-channel MISFET employing the LDD structure used in the measurement shown in FIG. 38 is the same as that used in the measurement shown in FIG. 37 above. It consists of the following conditions. As shown in the measurement results in FIG. 38, when the impurity concentration of the n-type semiconductor region 17 is 5 x 10" [atoms/aJ], the electric field strength is reduced as the length Ln of the n-type semiconductor region 17 increases. However, when the n-type semiconductor region 17 and the gate electrode 13 overlap, the electric field strength increases.On the other hand, the impurity concentration of the n-type semiconductor region 17 is 1×1013 [a
toms/cjl, the length L of the n-type semiconductor region 17
As n becomes longer, the electric field strength is similarly reduced, and when the n-type semiconductor region 17 and the gate electrode 13 overlap each other, the electric field strength is further reduced. This electric field strength reduction effect occurs when the length Ln of the n-type semiconductor region 17 becomes approximately 0.1 μm or more. In this embodiment, even if the length Ln of the n-type semiconductor region 17 changes slightly, the electric field strength is approximately constant, and the stable regional length L is 0°5 [μm] or more.
n to form an n-type semiconductor region F. Further, the length Ln of the n-type semiconductor region 17 is increased to the extent that the short channel effect does not appear significantly. Based on the measurement results shown in FIGS. 37 and 38 above. Transfer MISFETQt that adopts the above-mentioned LDD structure,
Each of the n-channel MISFETQn has a gate electrode 13
And n-type semiconductor area! 7 to actively improve the mutual conductance (gm) and increase the amount of drain current. In addition, we also have a transfer MISFETQ that adopts an LDD structure.
Each of the t- and n-channel MISFETs Qn is formed by forming an n-type semiconductor region 17 with an impurity concentration of approximately I×10 ” [atoms/aJ], increasing the length Ln of the n-type semiconductor region 17, and increasing the length Ln of the n-type semiconductor region 17. 17 is overlapped with the gate electrode 13 to reduce the electric field strength.This reduction in electric field strength can reduce the amount of hot carriers generated near the drain region.
It is possible to reduce variations in the threshold voltages of Qt and n-channel MISFET Qn over time. Next, an n-type impurity is introduced into the main surface of the active region of the n-type well region 3 in the formation region of the P-channel MISFET Qp of the peripheral circuit. This n-type impurity is introduced for the purpose of forming a low impurity concentration n-type semiconductor region (19) of an LDD structure. BF is used as the P-type impurity. B
F, using the ion implantation method, with an energy of about 40 CKeVE, about 10'' to 1013 [atoms/d]
Approximately 1 will be introduced. BF2 is introduced in self-alignment with respect to the gate electrode 13 using the gate electrode 13 as an impurity introduction mask. By introducing this P-type impurity,
A P-type semiconductor region 19 is formed (see FIG. 21), n
This is because the diffusion rate of type impurities is faster than that of n-type impurities. The P-type semiconductor region 19 can be used as a gate electrode even without heat treatment! A sufficient overlap can be formed with 3. Next, sidewall spacers 16 are formed on the sidewalls of the gate electrode 13 and insulating film 15, respectively. The sidewall spacer 16 is formed by depositing a silicon oxide film over the entire surface of the substrate including the top of the insulating film 15, and etching the entire surface of the silicon oxide film by an amount corresponding to the thickness of the deposited film. The silicon oxide film is deposited by the CVD method using inorganic silane gas as a source gas, for example, as described above.
The film is formed with a film thickness of [nm]. For etching, anisotropic etching such as RIE is used. Next, during etching to form the sidewall spacer 16, the gate electrode 7 and the sidewall spacer 1 are etched.
p-type well region 2. n7
Since the main surface of each active region of the mold well region 3 is exposed, a silicon oxide film (not numbered) is formed on this exposed region. This silicon oxide film is mainly used for the purpose of preventing contamination when introducing impurities and preventing damage to the main surface of the active region due to the introduction of impurities. The silicon oxide film is formed, for example, by a thermal oxidation method, and has a thickness of about 10 [nm]. Next, the transfer MI 5FETQt l of the memory cell MC of the memory cell array MAY, the n-channel MI of the peripheral circuit
In each formation region of SFETQn, an n-type impurity is introduced into the main surface of the active region of the P-type well region 2. n
As the type impurity, AS, which has a slower diffusion rate than P, is used for the purpose of shallowing the pn junction depth. As is introduced into the gate electrode 13 and the sidewall spacer 16 as an impurity by using an ion implantation method and with an energy of about 30-50 [KeV]. Use as an introduction mask,
It is introduced in self-alignment with this gate electrode 13 and sidewall spacer 16. Next, in the formation region of the p-channel MISFET Qp of the peripheral circuit, a P-type impurity is introduced into the main surface of the active region of the n-type well region 3. BF is used as the P-type impurity. BF is approximately 30[KeV] using the ion implantation method.
] with an energy of about 10 ” -10” [atom
About s/cJ will be introduced. BF2 is the gate electrode 13
Using the sidewall spacers 16 and 16 as impurity introduction masks, the impurities are introduced in self-alignment with the gate electrode 13 and the sidewall spacers 6. Thereafter, heat treatment is performed to stretch and diffuse the n-type impurity to form a Go-type semiconductor region 18, and the P
A p-type semiconductor region 20 is formed by stretching and diffusing the type impurity.
form. The heat treatment is performed, for example, in nitrogen gas at a temperature of 900 to 1
000 ['C] for about 1 to 3 [minutes].
The °-type semiconductor region 18 is used as a source region and a drain region. By forming this n° type semiconductor region 18, as shown in FIG.
In AY, the transfer MISFET Qt adopting the LDD structure of the memory cell MC is completed, and the 21st
n-channel M adopting the LDD structure of the peripheral circuit shown in the figure
ISFETQn is completed. Further, by the step of forming the P° type semiconductor region 20, the LD shown in FIG.
A P-channel MISFET Qp employing the D structure is completed. In this way, (C-1) the memory cell MC is configured by the transfer MISFETQt and the drive MISFETQd.
In the RAM 1, a step of forming a gate electrode 7 with a gate insulating film 6 interposed on the main surface of the formation region of the drive MISFET Qd of the P-type well region (substrate) 2, and a step of driving the p-type well region 2. Two types of n-type impurities (P, As) having opposite conductivity types and different diffusion rates from the P-type well region 2 are introduced into the main surface of the formation region of the MISFET Qd for use in a self-aligned manner with respect to the gate electrode 7. , a step of forming a driving MISFET Qd with a double drain structure, and a step of forming a gate electrode 13 with a gate insulating film 12 interposed on the main surface of the formation region of the transfer MISFET Qt in the P-type well region 2. , on the main surface of the transfer MISFET Qt formation region of the P-type well region 2
A low concentration n-type impurity of the opposite conductivity type to the −-type well region 2 (
a step of introducing P) in self-alignment with the gate electrode 13; a step of forming a sidewall spacer 16 on the sidewall of the gate electrode 13 in self-alignment therewith;
A high concentration n-type impurity (A s ) of a conductivity type opposite to that of the P-type well region 2 is applied to the main surface of the formation region of the transfer MISFET Qt in the P-type well region 2 with respect to the sidewall spacer 16. The method includes a step of introducing in a self-aligned manner and forming a transfer MISFETQt having an LDD structure. With this configuration, the transfer MISFETQt and drive MISFETQd are set to L for the purpose of preventing hot carriers.
In the case of a DD structure, a total of four impurity introduction masks are used, but in this example, driving M, 15FETQ is used for the purpose of preventing hot carriers and increasing mutual conductance.
d has a double drain structure, and two types of n with one mask.
Since type impurities were introduced and a total of three masks were used, one for the drive MISFETQd and two for the transfer MISFETQt, the number of masks could be reduced by one, and the number of manufacturing steps in the SRAMI manufacturing process could be reduced. Further, the gate insulating film 6 of the drive MISFETQd, the transfer MISFET
SFETQt gate insulating film! Since each of 2 is formed in separate manufacturing processes, the thickness of each gate insulating film can be independently optimized. For example, the thickness of the gate insulating film 6 of the drive MISFETQd is the same as that of the gate insulating film of the transfer MISFETQt! If it is formed thinner than the film thickness of 2, the driving MI
By increasing the mutual conductance of SFETQd, the β ratio of memory cell MC can be increased. (C-2) The quick-action MISF of the configuration (C-1)
A reference voltage line (Vss) 13 formed in the same manufacturing process as the gate electrode 13 of the transfer MISFETQt is connected to the source region of the double drain structure of the ETQd. With this configuration, in addition to the above effects. This reference voltage line 13 below the reference voltage line 13 and the driving M
The connecting semiconductor region (semiconductor region for taking out the reference voltage Vss) that connects the source region (11) of the ISFETQd can be formed in the process of forming the double drain structure semiconductor region (10 and 11) of the driving MISFETQd. Therefore, the number of manufacturing steps in the SRAM 1 manufacturing process can be reduced by the amount corresponding to the step of forming the semiconductor region for connection. (C-3) The step of forming the drive MISFET Qd adopting the double drain structure of the structure (C-1) is performed after forming the gate electrode 7.
A step of forming a sidewall spacer 9 on the sidewall of the gate electrode 7 in a self-aligned manner, and then introducing two types of n-type impurities (P. As) having different diffusion rates with respect to the gate electrode 7 in a self-aligned manner. shall be. With this configuration, the driving MISFETQ is
The amount of diffusion (diffusion amount) of the semiconductor regions d (10 and H) toward the channel formation region side can be reduced. As a result, the substantial gate length of the driving MISFET Qd is secured,
Since the short channel effect can be prevented and the area occupied by the driving MISFET Qd can be reduced, the area occupied by the memory cell MC can be reduced and the degree of integration of the SRAM 1 can be improved. In addition, (C-4) a transfer MI that adopts the LDD structure;
In the step of forming SFETQt, after forming the gate electrode 13, the n-type impurity (P) with a low impurity concentration is introduced, and the introduced n-type impurity is subjected to a heat treatment (annealing) for stretching and diffusion. After (n-type semiconductor region 17
), the sidewall spacer 16 is formed, and then the high impurity concentration n-type impurity (A
s)). With this configuration, the amount of diffusion toward the channel formation region side of the n-type semiconductor region 17 formed by introducing the n-type impurity with a low impurity concentration into the LDD structure of the transfer MISFET Qt can be increased by adding the heat treatment. , the amount of overlap between the gate electrode 13 of the transfer MISFET Qt and the n-type semiconductor region 17 formed by introducing the n-type impurity with a low impurity concentration is increased, and the electric field generated near the drain region is increased. Since the strength can be weakened, the amount of hot carriers generated can be reduced, the deterioration of the threshold voltage of the transfer MISFET Qt over time can be reduced, and the electrical reliability of the SRAMI can be improved. (C-5) In an SRAMI in which a memory cell MC is configured of a transfer MISFET Qt controlled by a word line (WL) 13 and a driving MISFET Qd connected to a reference voltage line (Vss) 13, the memory cell MC A step of forming the gate electrode 7 of the drive MISFET Qd, and forming the gate electrode 13 of the transfer MISFET Qt of the memory cell MC on the upper layer of the gate electrode 7,
A step of forming a word, sia, and reference voltage l1A13 in the same conductive layer as this gate electrode 13 is provided. With this configuration, the transfer MISFETQ of the memory cell MC
Since the word line 13 and the reference voltage line 13 were formed in the process of forming the gate electrode 13 of t, the SRAM
The number of manufacturing steps in one manufacturing process can be reduced. In addition, (C-12) MISFE for transfer of memory cell MC
In the SRAM 1 in which a word 1iA (WL) 13 is integrated with the gate electrode 13 of TQt, the transfer MISFE of the memory cell MC in the p-type well region (substrate) 2
A step of forming a gate insulating film 12 on the main surface of the TQt formation region, and a step of forming a carbon dioxide film on the entire surface of the substrate including the top of this gate insulating film 12.
A step of forming a polycrystalline silicon film (doped polysilicon) 13A deposited by the VD method and into which impurities to reduce the resistance value are introduced during the deposition, and a step of forming a polycrystalline silicon film (doped polysilicon) 13A on the entire surface of the substrate including the top of this polycrystalline silicon film 13A. Melting point metal silicide film (WSi,
) 13B and this high melting point metal silicide film 13
B. Patterning is applied to each of the polycrystalline silicon films 13A, and the transfer MIS is formed on the gate insulating film 12 using the remaining polycrystalline silicon films 13A and high melting point metal silicide film 11B.
The method includes a step of forming the gate electrode 13 of the FETQt and the word line 13 integrally connected thereto. With this configuration, the polycrystalline silicon film 13A under the gate electrode 13 of the transfer MISFET Qt is doped with n-type impurity (P) during deposition.
In addition, we have abolished the thermal diffusion treatment of P after deposition, and eliminated the use of fluoric acid to remove the phosphorus glass film formed on the surface of the polycrystalline silicon film during this thermal diffusion treatment. , the film quality of the polycrystalline silicon film (doped polysilicon) 13A into which n-type impurities are introduced during the deposition is changed to the polycrystalline silicon film (non-doped polysilicon) in which impurities are not introduced during the deposition.
Since the gate insulating film 12 can be formed more densely than the polycrystalline silicon film, it is possible to reduce the deterioration of the dielectric breakdown voltage of the gate insulating film 12 due to seepage of fluoric acid into the polycrystalline silicon film. As a result, the resistance value is reduced and the SRA
The film thickness of the lower layer polycrystalline silicon film 13A of the word line 13 with a two-layer structure is made thinner for the purpose of increasing the operating speed of MI,
Since the overall film thickness of the word line 13 can be reduced, the underlying surface (the surface of the interlayer insulating film 30) of the conductive layer (for example, the complementary data line DL) disposed on the word line 13 can be made flat. . (C-13) The transfer MI of the configuration (C-12)
The lower polycrystalline silicon film 13A of the gate electrode 13 of SFETQt and the word line (WL) 13 connected thereto is made of Si.
, H, and PH3 as source gases. With this configuration, the surface of the polycrystalline silicon film 13A on the gate insulating film 12 side is flattened. Since it is possible to prevent electric field concentration from occurring between the p-type well region 2 and the gate electrode 13, it is possible to improve the transfer MISFE.
Deterioration of the dielectric strength voltage of the gate insulating film 12 of TQt can be reduced. Also, (C-14) the above configuration (C-12) or (C-1
3) Polycrystalline silicon film L3 under the gate electrode 13 of the transfer MISFET Qt and the word line 13 connected thereto
A is formed to have a thickness of 30 [nm] or more and 70 [nm] or less. With this configuration, the transfer MISFET
It is possible to reduce the thickness of the gate electrode 13 of Qt, and
Deterioration of the dielectric strength voltage of the gate insulating film 12 can be reduced. (C-15) In the SRAM 1 in which the memory cell MC is constituted by the transfer MISFET Qt and the driving MISFET Qd whose source region (11) is connected to the reference voltage line (Vss) 13, the P° type well region (substrate )2
A gate electrode 7 is formed on the main surface of the formation region of the driving MISFETQd, and a source region and a drain region (11) are formed on the main surface of the driving MISFETQd.
and a step of forming d. A step of forming a gate insulating film 12 on the main surface of the formation region of the transfer MISFET Qt in the p-type well region 2, and forming a polycrystalline silicon film L3 on the entire surface of the substrate including the top of this gate insulating film lz.
The step of depositing A, the polycrystalline silicon film 13A on the source region (11) of the driving MUSFETQd, and the gate insulating film 12 below it are sequentially removed, and the connection hole 14 is removed.
A drive MISF is formed over the entire surface of the substrate including the polycrystalline silicon film 13A and through the connection hole 14.
A step of forming a high melting point metal silicide film 13B connected to the source region (11) of ETQd, sequentially patterning each of the high melting point metal silicide film 13B and the polycrystalline silicon film 13A, and forming the gate insulating film! polycrystalline silicon film 1 on z
3A and a high melting point metal silicide film 13B, and a step of forming a reference voltage line 13 connected to the source region of the driving MISFET Qd. With this configuration, the transfer MISFETQ
After forming the gate insulating film 12 of t, a polycrystalline silicon film 13A is formed directly on this gate insulating film 12, and then,
The polycrystalline silicon film 13A and the underlying gate insulating film 12 are removed to form a connection hole on the surface of the source region (11) of the driving MISFETQd. 4, the photoresist mask forming this connection hole 14 is used as the transfer MI
The gate insulating film 12 of the transfer MISFET Qt should not be in direct contact with the gate insulating film 12 of the SFET Qt due to contamination, etc.
Deterioration of dielectric strength voltage can be reduced. (B-6) Memory cell MC of the above configuration (B-5)
The transfer MISFET Qt which adopts the LDD structure has a diffusion amount of the n-type semiconductor region 17 with a low impurity concentration from the end of the gate electrode 13 to the channel formation region side (the amount of overlap between the gate electrode 13 and the n-type semiconductor region 17, Alternatively, the length Ln) of the n-type semiconductor region 17 is set to a range of 0.5 μm or more and no short channel effect occurs. With this configuration, the gate electrode 13 of the transfer MISFET Qt and the low impurity concentration n-type semiconductor region (LDD section) 1
By increasing the amount of overlap with 7 and weakening the electric field strength generated near the drain region, the amount of hot carriers generated can be reduced and the transfer MISFETQ
Reduces the deterioration of the threshold voltage over time of t, and improves SRAMI
can improve electrical reliability. (D-5) A memory cell MC is configured with a transfer MISFETQt and a drive MISFETQd that are controlled by the word line (WL) 13, and performs information write operation, information retention operation, and information read operation of this memory cell MC. In an SRAMI in which a peripheral circuit to be controlled is configured with a MISFET, a step of forming the MI 5FETQd for driving the memory cell MC, and a step of forming the MISFE for the transfer of the memory cell MC.
In addition to forming TQt, n-channel MIS of peripheral circuit
and a step of forming a FETQn (or p-channel MISFETQP). With this configuration, the n-channel MISFETQn of the peripheral circuit can be formed in the process of forming the transfer MISFETQt of the memory cell MC.
The amount corresponds to the process of forming the n-channel MISFETQn of this peripheral circuit. The number of manufacturing steps in the manufacturing process of the SRAM 1 can be reduced. [Third layer gate material formation process] Next, etching is performed on the entire surface of the substrate, mainly for the MISFETQ for driving the memory cells MC of the memory cell array MAY.
#1 formed on the gate electrode 7 of d! l Membranes 8 and 8
Remove each of A. The removal of the insulating films 8 and 8A is as follows:
Said gate electrode 13, word line! 3. An insulating film formed on each of the reference voltage lines 13! 5 and sidewall spacers 16 as etching masks (as defined in these masks). In other words, gate electrode 1
3. The insulating films 8 and 8A under each of the word line 13° reference voltage line 13 remain. These insulating films 8 and 8
The removal of A is mainly performed for the purpose of exposing the surface of the gate electrode 7 of the driving MISFET Qd1, which becomes the first electrode 7 of the capacitive element C of the memory cell MC. Furthermore, although each of the insulating film 8 and the insulating film 15 is formed of a silicon oxide film having approximately the same etching rate in this embodiment, the insulating film used as an etching mask! 5 is formed thicker than the insulating film 8, and remains even if the insulating film 8 is removed. When etching the insulating film 8, the underlying insulating film (silicon nitride film) 8A has a different etching rate and is therefore used as an etching stopper layer. That is, by forming the insulating film 8A used as an etching stopper layer under the insulating film 8, the etching controllability of the insulating film 8 can be improved. In this way, (C-16) In the SRAM 1 in which the memory cell MC is composed of the transfer MISFETQt and the drive MISFETQd, the p-type well region (substrate) 2
a step of forming a gate insulating film 6 on the main surface of the formation region of the driving MISFET Qd; A polycrystalline silicon film 7 is formed on the entire surface of the substrate including the top of this gate insulating film 6.
, a step of sequentially forming an insulating film (silicon nitride film) 8A and an insulating film (silicon oxide film) 8 as an oxidation-resistant mask, and a step of sequentially forming an insulating film 8, an insulating film 8A, and a polycrystalline silicon film 7, respectively. A process of sequentially patterning with the same pattern to form the gate electrode 7 of the driving MI 5FETQd using the polycrystalline silicon film 7, and forming sidewall spacers (silicon oxide film) 9 on the side walls of the gate electrode 7. The process of
A step of forming a gate insulating film 12 by thermal oxidation on the main surface of the formation region of the transfer MISFET Qt in the p-type well region 2, and forming the transfer MISFET Qt on the gate insulating film 12.
a step of forming a gate electrode 13; The entire surface of the substrate is etched, and the insulating film 8 on the gate electrode 7 is etched. and a step of sequentially removing each of the insulating films 8A. With this configuration, the drive MISFETQd
Based on the phenomenon that the oxidation rate of the corner portion 8B is slower than that of the surface portion of the gate electrode 7, the end portion of the gate electrode 7 of the quick-acting M, 15FETQd is curled up during the thermal oxidation process for forming the gate insulating film 12. can be reduced by the insulating film (silicon nitride film: oxidation-resistant mask) 8A on the gate electrode 7,
The thickness of the insulating film (silicon oxide film) 8 on the gate electrode 7 can be made uniform, and the amount of etching in the step of removing the insulating film 8 can be reduced. Furthermore, in the step of removing the insulating film 8, the insulating film (silicon nitride film) 8A on the gate electrode 7 is used as an etching stopper layer, and under-etching and over-etching can be reduced, so that the controllability of etching can be improved. . In addition, in the thermal oxidation process for forming the gate insulating film 12, the insulating film (silicon nitride film) 8A on the gate electrode 7 is used as a heat-resistant oxidation mask, and the crystal grains of the polycrystalline silicon film on the surface portion of the gate electrode 7 are Since the growth of the gate electrode 7 can be reduced, the surface of the gate electrode 7 can be made flat. This flattening of the surface of the gate electrode 7 means that the surface of the first electrode 7 of the capacitive element C can be flattened. Next, an insulating film 21 is formed on the entire surface of the substrate including the exposed surface of the gate electrode 7. This insulating film 21 is mainly used as the dielectric film 21 of the capacitive element C of the memory cell MC. The insulating film 21 is formed of a silicon oxide film deposited by the CVD method, which can improve the dielectric breakdown voltage, as shown in the measurement results of FIG. 33. The first electrode 7 of the capacitive element C is made of Si,
The third layer is deposited by a CVD method using H, as a source gas.
As shown in Figure 4, one surface can be flattened, so the insulating film 2
1, the dielectric strength can be improved, and as a result, the film thickness can be reduced. Further, the insulating film 21 is formed of a single silicon oxide film, and can be made thinner. The insulating film 21 is formed with a thin film thickness of about 40 [nm]. Next, on one semiconductor region (18) and the other semiconductor region (18) of the transfer MISFET Qt of the memory cell MC, the insulating film 21 and the underlying insulating film are removed to form a connection hole 22. The connection hole 22 formed on one semiconductor region of the transfer MISFETQt connects the one semiconductor region (18), the drain region (11) of the drive MISFETQd, the gate electrode 7, and the second capacitor C.
It is formed for the purpose of connecting each of the electrodes (23). The connection hole 22 formed on the other semiconductor region of the transfer MISFETQt is connected to the other semiconductor region, the intermediate conductive layer (2
The connection hole 22 formed in the latter insulating film 21 for the purpose of connecting each of 3) is a transfer MISFET.
It is formed with a larger opening size on the gate electrode 13 side than the side wall spacer 16 provided on the side wall of the gate electrode 13 of Qt. That is, the sidewall spacer 16 is exposed in the connection hole 22 formed in the insulating film 21,
The substantial opening size of the contact hole 22 on the other semiconductor region (18) is defined by the sidewall spacer 16. Therefore, the substantial opening position of the connection hole 22 on the gate electrode 13 side is defined by self-alignment with respect to the gate electrode 13. Next, a polycrystalline silicon film 23 is deposited over the entire surface of the substrate including on the insulating film Zl, which becomes the dielectric film. This polycrystalline silicon film 23
is formed in the step of forming the third layer of gate material. A part of the polycrystalline silicon film 23 passes through the connection hole 22 and connects to the transfer M
Semiconductor region of ISFETQt, driving MISFETQd
is connected to the drain region and gate electrode 7. This polycrystalline silicon film 23 includes the gate electrode (23) of the load MISFET Qp, the second electrode (23) of the capacitive element C, and the conductive layer (
23) and the intermediate conductive layer (23). In particular, the polycrystalline silicon film 23 is connected to the load MISFETQ.
p's gate electrode (23) and capacitive element C's second electrode (2
3), so as above, 5i2H,
and P.H. (Doped polysilicon) is deposited by CVD method using as a source gas. The polycrystalline silicon film 23 is formed with a thin film thickness of, for example, 60 to 80 [nm] in order to suppress the growth of a stepped shape in the upper layer, and has a thickness of 10" to 10" [ato+ms/a].
It is formed with a P concentration of approximately Thereafter, heat treatment is performed to activate P introduced into the polycrystalline silicon film 23. This heat treatment was carried out in nitrogen gas for 700 min.
It is carried out at a high temperature of ~900 ['C] for about 20 [93]. Next, the polycrystalline silicon film 23 is patterned,
As shown in FIG. 28, the gate electrode 23 of the load MISFET Qp, the second electrode 23 of the capacitive element C, the conductive layer 23,
Each of the intermediate conductive layers 23 is formed. The polycrystalline silicon film 23 is patterned using, for example, an etching mask formed by photolithography and anisotropic etching such as RIE. By the step of forming the second electrode 23, the first electrode 7,
A capacitive element C in which the dielectric film 21 and the second electrode 23 are sequentially laminated is completed. In this way, the gate electrode 7 of (C-6) drive MISFET Qd is the first electrode 7, and the second electrode 23 is connected to the information storage node region with the dielectric film 21 interposed on the first electrode 7. In the SRAM 1 in which a capacitive element C provided with is arranged in a memory cell MC, the first electrode 7 or the second electrode 23 is made of a multilayer film deposited by the CVD method and into which an impurity to reduce the resistance value is introduced during the deposition. It is formed from a crystalline silicon film (doped polysilicon film). With this configuration, the C
Compared to a polycrystalline silicon film deposited by the VD method and then doped with impurities to reduce its resistance, the surface of the polycrystalline silicon film on the side that contacts the dielectric film 21, that is, the upper side of the first electrode 7 or the second electrode 2
The lower surface of 3 can be flattened. As a result, electric field concentration generated between the second electrode 7 and the second electrode 23 of the capacitive element C can be prevented, and the dielectric strength voltage of the dielectric film 21 of the capacitive element C can be improved, thereby increasing the electrical reliability of the SRAMI. You can improve your sexuality. Also, the dielectric film 2 of the capacitive element C! Since the dielectric strength of the capacitive element C can be improved, the dielectric film 21 can be made thinner and the capacitive element C can be improved.
Since the amount of charge stored in S can be increased, the size of capacitive element C can be reduced to reduce the area occupied by memory cell MC, and
The degree of integration of RAMI can be improved. Further, the capacitive element C
Since the amount of charge stored in the memory cell MC can be increased,
The stability of information retention can be improved, and the alpha-ray soft error resistance can be improved. (C-7) The gate electrode 7 of the active MI 5FETQd is the first electrode 7, and the second electrode 7 is connected to the information storage node region with a dielectric film 21 interposed on the first electrode 7.
In the SRAM 1 in which a capacitive element C provided with an electrode 23 is arranged in a memory cell MC, the first electrode 7 or the second electrode 23 is made of Si, H, and PH. It is formed of a polycrystalline silicon film 23 deposited by the CVD method using as a source gas. With this configuration, compared to a polycrystalline silicon film (merely doped polysilicon) deposited by a CVD method, a dielectric film of a polycrystalline silicon film deposited by a CVD method using Si, H, and PH as a source gas 2! The surface on the side that comes into contact with, that is, the upper surface of the first electrode 7 or the upper surface of the second electrode 23 can be made more flat. As a result, the above configuration (C-6
) can have the same effect as the above. Further, the gate electrode 7 of the (C-S) drive MISFET Qd is used as the first electrode 7, and a dielectric film 21 is formed on the first electrode 7.
In the SRAM 1 in which a capacitive element C provided with a second electrode 23 connected to an information storage node region with a polycrystalline silicon film 23 deposited by a CVD method is disposed in a memory cell MC, the first electrode 7 is and a step of forming a dielectric film 2 using a silicon oxide film deposited on the first electrode 7 by a CVD method. With this configuration, the first
Compared to the case where a dielectric film is formed using a silicon oxide film formed by thermal oxidation on the surface of the polycrystalline silicon film that is the electrode 7, the crystal planes of the crystal grains on the surface of the underlying polycrystalline silicon film are (
The silicon oxide film can be deposited regardless of the presence of a plurality of different crystal planes, and the thermal oxidation growth rate is different for each crystal plane, and the thickness of this silicon oxide film, that is, the dielectric film 21, can be made uniform. The electric field concentration generated between the electrode 7 and the second electrode 23 is prevented to improve the dielectric strength voltage of the dielectric film 21, and the SRAM
The electrical reliability of 1 can be improved. In addition, the above configuration (C-
Similar to the effect of 6), the size of the capacitive element C can be reduced and the area occupied by the memory cell MC can be reduced.
The degree of integration can be improved. Furthermore, the stability of information retention in the memory cell MC can be improved, and the α-ray soft error withstand voltage can be improved. (C-9) The first electrode 7 or the second electrode 23 of the configuration (C-8) is a polycrystalline silicon film deposited by a CVD method and into which impurities to reduce the resistance value are introduced during the deposition; The capacitor is formed of a polycrystalline silicon film 23 deposited by a CVD method using Si, H, and PH as source gases. With this configuration, in addition to the effects of the configuration (C-8), the configuration (At)
The effect of C-6) or (C-7) can be achieved. (C-10) The drain region (11) of the first related MISFETQd and the gate electrode 7 of the second driving MISFETQd are connected to one semiconductor region (18) of the transfer MISFETQt, and the first driving MISFETQ
The first electrode 7 and the first driving MISFE are connected to the gate electrode 7 of d.
In an SRAMI in which a memory cell MC includes a capacitive element C in which each of the second electrodes 23 is connected to the drain region of the TQd, the first driving MISFETQd and the second driving MISFETQd are formed, and the first driving MISFETQd and the second driving MISFETQd are formed. a step of forming the first electrode 7 of the capacitive element C with the gate electrode 7 of the MISFETQd; and
A step of forming a transfer MISFET Qt in which one semiconductor region is connected to the drain region of d, and a step of forming the capacitive element C
A capacitive element C is formed by interposing a dielectric film 21 on the first electrode 7 of
A second electrode 23 is formed, and a part (extracted) conductive layer 23 of the second electrode 23 is used to connect the transfer MIS.
One semiconductor region of FETQt and second driving MISFE
The process of connecting the gate electrode 7 of TQd is fffi'L.
Ru. With this configuration, since the first electrode 7 of the capacitive element C is formed by the gate electrode 7 of the first driving MISFET Qd, the SR
The number of manufacturing steps in the manufacturing process of AM1 can be reduced, and in the step of forming the second electrode 23 of the capacitive element C (using the same conductive layer as the second electrode 23), the transfer MIsFE
One semiconductor region of TQt and second driving MISFETQ
Since the gate electrode 7 of d is connected, the number of manufacturing steps in the SRAMI manufacturing process can be reduced by the amount corresponding to the step of connecting the two. (C-11) Capacitive element C having the above configuration (C-10)
The first electrode 7 or the second electrode 23 is 5i2H, and PH
, a polycrystalline silicon film (doped polysilicon) deposited by the CVD method using as a source gas 23. Alternatively, it is formed of a polycrystalline silicon film (doped polysilicon) deposited by the CVD method and into which impurities are introduced to reduce the resistance value during the deposition. With this configuration, in addition to the effects of the configuration (C-10), it is possible to achieve the effects of the configuration (C-6) or (C-7'). (C-17) The driving M of the above-mentioned configuration (C-16)
The gate electrode 7 of the ISFET Qd is used as the first electrode 7 of the capacitive element C, and the gate electrode 7 has the insulating film (silicon oxide film) 8 and the insulating film (silicon nitride film) 8A removed.
A second electrode 23 of the capacitive element C is formed thereon with a dielectric film 21 interposed therebetween. With this configuration, the surface of the gate electrode 7, which is the first electrode 7 of the capacitive element C, is covered with the insulating film (silicon nitride film) 8A during the thermal oxidation step, and the surface is flattened. First electrode 7 and second electrode 2 of element C
3 can be reduced, and the dielectric strength voltage of the dielectric film 21 of the capacitive element C can be improved. (C-18) An SR composed of a memory cell MC in which the gate electrode 7 of the driving MISFETQd is connected to one semiconductor region (18) of the transfer MISFETQt.
In the AMI, a step of forming a gate electrode 7 and an insulating film 8 on the main surface of the formation region of the drive MISFET Qd in the p-type well region (substrate) 2, and a step of forming the transfer of the p-type well region 2. A gate electrode 13 and an insulating film 15 thicker than the insulating film 8 are formed on the main surface of the formation region of the transfer MISFET Qt. A step of forming a semiconductor region (18) and the driving MI
A step of removing a part of the insulating film 8 on the gate electrode 7 of the SFETQd and forming a connection hole 22 that exposes at least a part of the surface of one semiconductor region of the transfer MISFETQt, and passing through the connection hole 22. The transfer MI
One semiconductor region (18) of SFETQt, driving MI
Each of the gate electrodes 7 of SFETQd is connected to the gate electrode 7.
and a conductive layer 23 formed above the gate electrode 13
and a step of connecting with. With this configuration, the thickness of the insulating film 15 on the gate electrode 13 of the transfer MISFET Qt is formed thicker than the thickness of the insulating film 8 on the gate electrode 7 of the drive MISFET Qd, and the connection hole 22 is formed. Since the insulating film 15 is left on the gate electrode 13 during this process, short circuit between the gate electrode 13 and the conductive layer 23 can be prevented, and the yield in the SRAMI manufacturing process can be improved. Further, (C-19) constitutes a memory cell MC in which the gate electrode 7 of the drive MISFETQd is connected to one semiconductor region (18) of the transfer MISFETQt, and the other semiconductor region of the transfer MISFETQt of this memory cell MC. In the SRAMI in which the complementary data line (DL: 33) is connected to (18), the p-type well region (substrate)
2, the step of forming the gate electrode 7 on the main surface of the formation region of the driving M, 15FETQd, and the p-type well region 2.
A gate electrode 13 above the gate electrode 7 is formed on the main surface of the formation region of the transfer MISFETQt, and the one semiconductor region and the other semiconductor region are formed on the main surface of the transfer MISFETQt formation region. (18
) and connecting one semiconductor region of the transfer MISFET Qt and the gate electrode 7 of the drive MISFET Qd with a conductive layer 23 formed above the gate electrode 7 and the gate electrode 13, forming an intermediate conductive layer 23 on the other semiconductor region of the transfer MISFET Qt with the same conductivity ftN as this conductive layer 23;
With this intermediate conductive layer 23 interposed, the transfer MISF
A complementary data line (D L
: 33). With this configuration, the intermediate conductive layer 23 can be formed in the step of forming the conductive layer 23 connecting one semiconductor region of the transfer MISFET Qt and the gate electrode 7 of the drive MISFET Qd. The number of manufacturing steps in the manufacturing process of the SRAM 1 can be reduced by the amount corresponding to the forming step. Further, since the conductive layer 23 is formed of the same conductive layer as the second electrode 23 of the capacitive element C and the gate electrode 23 of the load MISFET Qp, the manufacturing process of the SRAMI is equivalent to the step of forming the conductive layer z3. The number of manufacturing steps in the process can be reduced. [Step 1 of forming third gate insulating film] Next, the gate electrode 23, the second electrode 23, the conductive layer 23
, an insulating film 24 is formed over the entire surface of the substrate including the upper portions of the intermediate conductive layers 23 . The insulating film 24 electrically isolates the lower conductive layer such as the gate electrode 23 and the upper conductive layer /I (26), and is used as the gate insulating film 24 of the load MISFET Qp. The insulating film 24 is formed of a silicon oxide film deposited by the CVD method using inorganic silane gas as a source gas, similarly to the dielectric film 21 and the like of the capacitive element C described above. The insulating film 24 has a thickness of about 2
Formed with a film thickness of 0 [nm1 or more, load MISFETQ
Since it is used as the p gate insulating film 24, the conduction characteristics (
The film thickness is approximately 50 [nm] or less in order to ensure good ON characteristics. In this embodiment, the insulating film 24 is, for example, 35 to 45 [n
m].

[Fourth Layer Gate Material Formation Step] Next, a connection hole 25 is formed in the insulating film 24 above the conductive layer 23 of the memory cell MC of the memory cell array MAY. The connection hole 25 is formed for the purpose of connecting the lower conductive layer 23 and the upper conductive layer (26, actually the n-type channel forming region 26N of the load MISFETQp). Next, a polycrystalline silicon film 26 is formed over the entire surface of the substrate including on the insulating film 24. This polycrystalline silicon film 26 is formed in the step of forming the fourth layer of gate material. The polycrystalline silicon film 26 is an n-type channel forming region (26
N), source region (26P), power supply voltage line (Vcc:
26P). The polycrystalline silicon film 26 is
Unlike the aforementioned polycrystalline silicon films 7.13A and 23,
It is formed of so-called non-doped polysilicon deposited by the CVD method using 5i2H as a source gas. Polycrystalline silicon film 2
6 is formed with a thin film thickness of, for example, 40 [n ml]. As described above, the polycrystalline silicon film 2G is formed to have a thickness of 30 nm or more so that crystal grains do not affect the uniformity of the film thickness. Further, the polycrystalline silicon film 26 is. In order to reduce leakage current as a load MISFET QP, it is formed with a film thickness of 50 [nm1 or less] as shown in FIG. 39 (a diagram showing the film thickness dependence of leakage current). Third
In Figure 9, the horizontal axis indicates the film thickness of the polycrystalline silicon film [n ml;
The vertical axis indicates the amount of leakage current [pΔ]. As shown in FIG. 39, when the polycrystalline silicon film has a thickness of about 50 nm or less, the amount of leakage current can be rapidly reduced.

[Step of forming third source region and drain region] Next,
Although not shown, an insulating film is formed on the polycrystalline silicon film 26. This insulating film is formed for the purpose of alleviating damage to the surface of the contamination prevention 1 when introducing impurities. The insulating film is formed of, for example, a silicon oxide film formed by a thermal oxidation method, and has a thickness of about 4
It is formed with a thin film thickness of about 6 [nml]. Next, impurities for threshold voltage adjustment are introduced into the entire surface of the polycrystalline silicon film 26. As the impurity for adjusting the threshold voltage, an n-type impurity such as P is used. P is MISFE for load
This is introduced for the purpose of making the threshold voltage of TQp an enhancement type. The enhancement type threshold voltage is obtained at an impurity concentration of approximately 1027 to 101s [ato+ls/ajl. therefore. P is produced by using an ion implantation method, with an energy of about 30 [KeV] and about 10'' to 10'' [atoms/
aJ] degree is introduced. When the impurity concentration of P introduced into the polycrystalline silicon film exceeds 10'' [atoms/ai], the threshold voltage of the polycrystalline silicon film increases (increases in absolute value), so it acts as a high resistance element. In other words, when the load MISFET Qp is non-conductive (OFF), only a current corresponding to the leakage current in the n-type channel formation region (26N) supplies the power supply voltage Vcc to the information storage node region of the memory cell MC. Since the information retention characteristics are deteriorated, the P introduced into the polycrystalline silicon film deteriorates.
If the impurity concentration is further increased and the threshold voltage is raised, the amount of leakage current increases. This increase in leakage current hinders power consumption. By the step of introducing the threshold voltage adjusting impurity, the n-type channel forming region 26
N is formed. Next, p-type impurities are introduced into the polycrystalline silicon film 26 in the formation region of the source region (2SP) of the load MI 5FETQp of the memory cell MC of the memory cell array MAY and the formation region of the power supply voltage line (Vce: 26P). do. For example, BF is used as the p-type impurity, and the thirteenth
It is introduced into the area indicated by the reference numeral 26P in the figure and surrounded by the two-dot chain line. BF2 uses the ion implantation method and is approximately 30
Approximately 10” [atoms/
aJ] degree is introduced. When introducing p-type impurities, a photoresist film formed by photolithography is used as an impurity introduction mask. Next, the polycrystalline silicon film 26 is patterned,
An n-type channel forming region 26N, a source region 26P, and a power supply voltage M26P are each formed. The polycrystalline silicon film 2B is patterned by anisotropic etching such as RIE using, for example, an etching mask formed by photolithography. , as shown in FIG. 29, the load MISFET Qp of the memory cell MC is completed. Also. By completing this load MISFET Qp, the memory cell MC is completed. Further, as shown in FIG. 22, the power supply voltage line 26P passes through the connection hole 25 at the peripheral circuit area (X decoder circuit XDEC area).
type semiconductor region 20 . This p type semiconductor region 20 has a P channel M of one periphery @ path.
It is formed in the same manufacturing process as the source region and drain region (20) of ISFETQP. In this way, (B-9) The polycrystalline silicon film 26 deposited by the CVD method forms the n-type channel forming region 26N and the source region 26.
Load MISFET with P (and drain region) formed
In the SRAMI that configures the memory cell MC with Qp,
An n-type impurity having a conductivity type opposite to the channel conductivity type (p-type) is introduced into the n-type channel formation region (non-doped polysilicon) of the load MISFET Qp of the memory cell MC. With this configuration, the load MI of the memory cell MC
The absolute value of the threshold voltage of SFETQp is increased, the threshold voltage is set to the enhancement type, and the MIS for the load is
Since the conduction and non-conduction (ON, 0FF) of FETQp can be reliably controlled, the power supply voltage Vcc can be reliably supplied from the power supply voltage line (Vcc) 26P to the information storage node area of the memory cell MC, and the information can be stabilized. In addition, it is possible to reduce unnecessary current supply (leak current) and reduce the amount of standby current of SRAMI that uses a battery backup method. In addition, (C-20) SRA in which a memory cell MC is configured by a drive MISFETQd and a load MISFETQp.
In MI, a gate electrode 7. of the driving MrSFETQd of the memory cell MC is formed on the main surface of the formation region of the driving MISFETQd of the p-type well region (substrate) 2.
A step of forming a source region and a drain region (11), and forming a gate electrode 23 of the load MI 5FETQp with a dielectric film 21 interposed on the gate electrode 7 of the drive MISFETQd, and forming the gate electrode 23 of the load MISFETQp.
is the drain region (11) of the driving MISFET Qd.
and a step of forming an n-type channel formation region 26N and a source region (and drain region) 26P of this load MISFETQp with a gate insulating film 24 interposed on the gate electrode 23 of this load MISFETQp. Be prepared. With this configuration, the drive MISFETQ
The first electrode 7.d of the capacitive element C inserted between the information storage node regions in the step of forming the gate electrode 7.d. MIS for load
Since each of the second electrodes 23 of the capacitive element C can be formed in the process of forming the gate electrode 23 of the FETQp, the number of manufacturing steps in the SRAMI manufacturing process can be reduced by the amount corresponding to the process of forming the capacitive element C. . Furthermore, since the load MISFET Q, p and the capacitive element C are each superimposed on the drive MISFET Qd of the memory cell MC, the area occupied by the memory cell MC is reduced by an amount equivalent to this superposition. The degree of integration of SRAM 1 can be improved. (C-21) The configuration (C-20) The load M
The gate electrode 23 of ISFETQp is made of Si, H. A polycrystalline silicon film (doped polysilicon) 23 deposited by the CVD method using a source gas of (polysilicon). This structure is compared to a polycrystalline silicon film deposited by the CVD method (non-doped polysilicon) and then doped with impurities to lower the resistance. The surface of the polycrystalline silicon film 23 on the side that contacts the gate insulating film 24, that is, the surface above the gate electrode 23 can be flattened. As a result, the gate electrode 2 of the load MISFETQp
3 and n-type channel forming region 26N (or source region 26N)
It is possible to prevent electric field concentration generated between P) and improve the dielectric strength voltage of the gate insulating film 24.
The thickness of the gate insulating film 24 of Qp can be reduced. Making the gate insulating film 24 of the load MISFET QP thinner can improve electrical characteristics such as improved conduction characteristics (ON characteristics). (C-22) The load MI of the configuration (C-21)
The n-type channel forming region 26N of SFETQP is 30 to 5
It is formed with a film thickness of 0 [n ml]. With this configuration,
N-type channel formation region 2 of the load MISFET QP
The leakage current at 6P can be significantly reduced, and the power supply voltage Vcc
Since the amount of wasted current supplied to the information storage node region of the memory cell MC can be reduced, the amount of standby current of the SRAMI that employs the battery backup method can be reduced. (C-23) The load MI of the configuration (C-21)
5FETQp(7) gate insulating film 24 is formed of a silicon oxide film deposited by CVD method. With this configuration, the surface of the gate electrode 23 of the load MISFET Qp on the gate insulating film 24 side can be flattened, and the dielectric strength voltage of the gate insulating film 24 can be improved, so that the film thickness of the gate insulating film 24 can be reduced. I can figure it out. As a result. The electrical characteristics of the load MI 5FETQp can be improved. (C-24) The load MI of the above configuration (C-23)
The gate insulating film 24 of SFETQP has a thickness of 30 to 50 [nm
It is formed with a film thickness of l. With this configuration, the load M
Since the thickness of the gate insulating film 24 of the ISFET QP is reduced, the electrical characteristics of the load MISFET Qp can be improved. [First Layer Metal Wiring Formation Step] Next, an interlayer insulating film 27 is formed over the entire surface of the substrate including over the memory cell MC. The interlayer insulating film 27 is a silicon oxide film 27A.
, BPSG film 27B are sequentially stacked to form a two-layer structure. The lower silicon oxide film 27A is formed for the purpose of preventing B and P contained in the upper BPSG film 27B from leaking to the lower layer side. The silicon oxide film 27A is, for example, 5i (OC2
H6)4 as a source gas at high temperatures (e.g. 600~
800 [”C]), low pressure (e.g. 1°0 [torr
r]) is deposited by the CVD method. The silicon oxide film 27A is formed to have a thickness of, for example, 140 to 160 [nm]. The upper layer BPSG film 27B is formed for the purpose of flattening the surface and suppressing the growth of the step shape in the upper layer. BPSG film 27
B is mainly deposited by a CVD method using inorganic silane (eg, SiH) as a source gas. This BPSG film 27B is
For example, after depositing a film with a thickness of 280 to 320 [nm], glass flow is applied to flatten the surface. Glass flow is
For example, the process is carried out in nitrogen gas at a high temperature of 800 to 900 [C] for about 10[93 m]. Next, a contact hole 28 is formed in the interlayer insulating film 27. The connection hole 28 is formed on the intermediate conductive layer 23 formed on the other semiconductor region (18) of the MC transfer MISFET Qt. The connection hole 28 is formed by directional etching.As shown in FIG.
On the n° type semiconductor region 18 of T Q n, P channel M
It is also formed on the p° type semiconductor region 20 of ISFETQp. Furthermore, the connection hole 28 is also formed on the P° type semiconductor region 20 at the connection portion of the power supply voltage line 2SP of the peripheral circuit shown in FIG. 22. Next, a high melting point metal film 29 is formed on the entire surface of the substrate including on the interlayer insulating film 27. The high melting point metal film 29 is formed in the first layer metal wiring forming step. This high melting point metal film 29 is formed of, for example, a W film deposited by sputtering. The W film is
When deposited by the CVD method, the step coverage in a single step shape part is good, but the W film deposited by the sputtering method tends to peel off from the surface of the interlayer insulating film 27, and the adhesion on the surface of the interlayer insulating film 27 is poor. However, it has the disadvantage of poor step coverage and increased internal stress if the film is thick. Therefore, in the SRAMI of this embodiment, taking advantage of the high adhesion of the W film, the interlayer insulating film 27 underlying the W film is flattened by glass flow using a BPS G film 27B). Coverage is addressed, and internal stress is addressed by making the W film thinner. The W film is thin for metal wiring, for example, 280 to 320 [n
ml of film thickness. Next, patterning is applied to the high melting point metal film 29,
As shown in FIG. 30, in the memory cell array MAY, a main word line (MWL) 29, a sub-word line (S
WL) 29 and an intermediate conductive layer z9 are each formed. A portion of the intermediate conductive layer 29 is connected to the lower intermediate conductive layer 23 through the connection hole 28 . This intermediate conductive layer 23 is the other semiconductor region (
18). In addition, as shown in FIG. 21, in the peripheral circuit, the layout! 29 is formed. moreover,
In the peripheral circuit shown in FIG. 22, a power supply intermediate wiring (Vcc) 29 is formed. This power supply intermediate wiring 29
is once connected to the P'' type semiconductor region 20 through the connection hole 28, and is connected via this P'' type semiconductor region 20 to a power supply voltage line 26P extending over the memory cell array MAY. The refractory metal film 29 is patterned by anisotropic etching using, for example, an etching mask formed by photolithography. In this way, (A-12) May'/'7-door aCMWL) of the above-mentioned configuration (A-11)29. ? Bward # (SW
L) Each of 29 is a high melting point metal film (
The interlayer insulating film 27 underlying each of the main word line 29 and sub-word line z9 is a BPSG film (silicon oxide film) 27B that has been planarized by glass flow.
Consists of. With this configuration, the high melting point metal film 29 deposited by the sputtering method has higher adhesion with the underlying interlayer insulating film 27 than the high melting point metal film deposited by the CVD method. Since the underlying interlayer insulating film 27 is planarized, the step coverage of the main word line 29 and the sub-word line 29 is improved, and the separation of the main word line 29 and the sub-word line 29 is improved. Breakage of each of the wires 29 can be prevented. In addition, a high melting point metal film 2 deposited by sputtering
9 is formed with a thin film thickness of about 280-320 nm,
Reduce internal stress. (D-6) The power supply voltage line 26P that supplies the power supply voltage Vcc to the memory cell MC is located in the peripheral area of the memory cell array MAY, and an interlayer insulating film 27 is formed on the upper layer of the power supply voltage line 26P.
In the SRAMI, which is connected to the power source intermediate arrangement 29 provided with the n-type well region (substrate) 3
Step 2 of forming a P゛ type semiconductor region 20 in the peripheral portion of the memory cell array MAY, and forming an interlayer \IA film 21 and 24 on the entire surface of the substrate including the top of this p ° type semiconductor region 20.
a step of forming a contact hole 25 by removing a part of the interlayer insulating films 21 and 24 on the p° type semiconductor region 20, and a step of forming a contact hole 25 on the 1 mm interlayer film type 4; a step of forming a power supply voltage line 26P connected to a part of the p-type semiconductor region 20 through the power supply voltage line 25; a step of forming an interlayer insulating film 27 over the entire surface of the substrate including over the power supply voltage line 2SP; Insulating film 27, the interlayer insulating film 2
1 and 24 of the other parts of the p-type semiconductor region 20 to form a connection hole 28;
0, and a step of forming a power supply intermediate wiring 29 connected to the other region of the 0. With this configuration, the connection hole 28
is not on the power supply voltage line 26P, but on the power supply voltage line 26P.
P” should be formed on the p° type semiconductor region 20 in a region different from
The type semiconductor region 20 is formed as a buffer layer when forming the contact hole 28), and when forming the contact hole 28, bumping of the power supply voltage line 26P due to overetching can prevent defects. Yield can be improved. Note that in this connection structure, the power supply voltage line 2
Between each of the 6P and 111 source intermediate wirings 29, there is a conductive layer (for example, 23, 13, 7 or a laminated film thereof) which is not limited to the p-type semiconductor region 20 but is lower than the power supply voltage line 2SP. May intervene. However, the power supply voltage line 26P is p
Since this conductive layer is formed of a polycrystalline silicon film, it is formed of a p-type so that a Pn junction is not generated. Furthermore, the conductive layer may be formed of a high melting point metal film or the like that does not form a pn junction. (D-7) The step of forming the p° type semiconductor region 20 of the structure (D-6) includes the step of forming the p° type semiconductor region 20 of the memory cell array MAY
P-channel MISF of the peripheral circuit located in the peripheral area of
It is formed in the same manufacturing process as forming each of the source region and drain region (20) of the ETQP. With this configuration, the p-type semiconductor region 20 can be formed in the same manufacturing process as the step of forming each of the source region and drain region of the p-channel MISFET Qp of the peripheral circuit.
The number of manufacturing steps in the SRAM 1 manufacturing process can be reduced by the amount corresponding to the step of forming the p° type semiconductor region 20.

[Step of Forming Buried Electrodes] Next, an interlayer insulating film 30 is formed over the entire surface of the substrate including the upper portions of the main word line 29, sub-word line 29, and intermediate conductive layer 29. The interlayer insulating film 30 is a silicon oxide film 30A.
, a silicon oxide film 30B, and a silicon oxide film 30G are sequentially stacked to form a three-layer stacked structure. The lower silicon oxide film 30A is made of tetraethoxysilane gas (
TE01: Deposited by plasma CVD using s1(QC2H, ), ) as a source gas. Silicon oxide film 30
A can be formed to have a uniform film thickness in each of the flat portion and the stepped portion, and for example, the main word line 29° sub-word!
When filling the recesses (corresponding to the minimum wiring spacing) between each of the lines 29 and flattening the surface thereof, almost no overhang shape occurs, so that so-called cavities do not occur. This silicon oxide film 30A is made of 1/2 of the minimum wiring interval for the purpose of filling the minimum wiring interval and flattening the surface thereof.
The film is formed with a film thickness of 400 [nml] or more, for example. The silicon oxide film 30B as the intermediate layer is coated to a thickness of, for example, 200 nml by a spin-on glass method, and after a leveling process is performed, the entire surface is etched. This silicon oxide film 30
B is formed mainly for the purpose of flattening the surface of the interlayer insulating film 30. The entire surface etching is performed on the underlying conductive layer (29
), the conductive layer (33) of the upper layer is carried out under conditions such that it does not remain in the respective connection portions, but remains in the step portion. The upper silicon oxide film 30C, like the lower silicon oxide film 30A, is deposited by plasma CVD using tetraethoxysilane gas as a source gas. This silicon oxide film 30C
is formed to have a film thickness of, for example, 400 [nm]. The silicon oxide film 30C is mainly intended to ensure the film thickness as the interlayer insulating film 30, cover the intermediate layer silicon oxide film 30B, and prevent deterioration of the film quality of the intermediate layer silicon oxide film 30B. It is formed. Next, a contact hole 31 is formed in the interlayer insulating film 30. The connection hole 31 is formed by anisotropic etching such as RIE using an etching mask formed by photolithography, for example. Next, as shown in FIG. 31, a buried electrode 32 is formed in the connection hole 31. An intermediate conductive layer 2 is provided in the connection hole 31.
Since the surface of the high melting point metal film such as 9 is exposed, the embedded electrode 32 is formed on the surface of this high melting point metal film. The buried electrode 32 is formed of, for example, a W film deposited by selective CVD. [Step of forming second layer metal wiring] Next, as shown in FIG.
, a complementary data line (D
L) form 33. Further, as shown in FIG.
form. This complementary data line 33 (and wiring 33)
is formed in the second layer metal wiring forming step. Complementary data llA33 indicates the embedded electrode 3 embedded in the connection hole 3.
2 to the lower intermediate conductive layer 29. The complementary data line 33 is formed with a two-layer stacked structure in which a barrier metal film 33A and an aluminum alloy film 33B are stacked in sequence. The lower barrier metal film 33A is formed of a TiW film deposited by sputtering, for example, and has a thickness of about 180 to 2
It is formed with a film thickness of 20 [nm]. The upper aluminum alloy film 33B is made of Cu and S deposited by sputtering.
Made of aluminum doped with i, approximately 700-9
It is formed with a film thickness of 0.00 [nm]. In this way, (C-25) In the SRAMI having a multilayer wiring structure in which the upper layer wiring (33) is formed by interposing the interlayer insulating film 30 on the upper layer of the lower layer wiring (29), the first layer which is the lower layer wiring is placed on the substrate. A step of forming the wiring and the second wiring (29) at predetermined intervals, and forming the lower layer wiring (29).
A plasma CVD method using tetraethoxysilane gas as a source gas is applied to the entire surface of the substrate including the upper part, and the distance between the first wiring and the second wiring of this lower layer wiring (29) is one-half.
A step of depositing a lower layer silicon oxide film 30A with a thickness above, and applying an intermediate layer silicon oxide film 30B over the entire surface of the substrate including the top of this silicon oxide film 30A by a spin-on glass method. 30B and etching the entire surface of this silicon oxide film 30B to remove the lower wiring (
29) Silicon oxide film 30B on the first wiring and the second wiring
At the same time, the silicon oxide film 30B in other areas is removed.
The remaining silicon oxide film 30B
An upper silicon oxide film 30 is deposited on the entire surface of the substrate including the upper layer using the CVD method.
Step of depositing C and the silicon oxide films 30A, 30B
, 30C, and forming a contact hole 31 by removing the first wiring or the second wiring (29), and forming the first wiring or the second wiring (29) on the silicon oxide film 30C through the three connection holes.
Upper layer arrangement connected to wiring (29)! (33). With this configuration, the thickness of the silicon oxide film 30A at the flat portion and the stepped portion is made uniform, and the overhang of the silicon oxide film 30A is made uniform in the region between the first wiring and the second wiring of the lower layer wiring (29). Since the occurrence of cavities based on the shape can be reduced, insulation defects in the interlayer insulating film 30 can be reduced, such as prevention of penetration of cavities during etching of the entire surface of the silicon oxide film 30B, and the yield in the manufacturing process of the SRAM 1 can be improved. In addition, the silicon oxide film 30B
The steep step shape on the surface of 0A is alleviated, and the silicon oxide film 3
Since the 0G surface can be made flat, disconnection defects in the upper layer wiring (30) can be reduced, and the yield in the manufacturing process of the SRAM 1 can be improved. Moreover, since the silicon oxide film 30B does not remain in the connection hole 31 between the lower layer wiring (29) and the upper layer wiring (33) due to the etching of the entire surface, the upper layer wiring due to the moisture contained in this silicon oxide film 30B It is possible to prevent corrosion of (33) and improve the yield in the SRAMI manufacturing process. Further, the lower layer of the silicon oxide film 30B is covered with the silicon oxide film 30A, and the upper layer is covered with the silicon oxide film 30C, which reduces moisture absorption in the silicon oxide film 30B and improves the film quality of the silicon oxide film 30B. It is possible to improve the yield in the manufacturing process of the SRAM 1, such as by preventing cracks in the film 30B. [Final passivation film formation process] Next, as shown in FIGS. 1 and 21, a final passivation film 34 is formed over the entire surface of the substrate including the complementary data line 33. Final passivation film 34
is composed of a three-layer stacked structure in which a silicon oxide film, a silicon nitride film, and a resin film are stacked one after the other. The lower silicon oxide film is formed by plasma CVD using tetraethoxysilane gas as a source gas, which can form a uniform film thickness.
Deposited by method. Furthermore, since the lower layer silicon oxide film is formed after forming the aluminum alloy film 33B of complementary data 833, the above-mentioned CVD method that can be formed at a low temperature, for example, about 400 [''C] or lower is used. The silicon oxide film of, for example, is formed with a film thickness of 400 nm. The silicon nitride film of the intermediate layer is formed mainly for the purpose of improving moisture resistance.
It is deposited by the VD method and has a thickness of 1.0 to 1.4 [μm]. The two-layer resin film is formed of, for example, a polyimide resin film, and is formed mainly for the purpose of shielding alpha rays. This upper layer resin film is formed to have a thickness of, for example, 2.2 to 2.4 [μm]. By applying these series of manufacturing processes. The SRAM 1 of this embodiment is completed. As above, the invention made by the present inventor has been specifically explained based on the above-mentioned 5 examples, but 1. the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Of course. For example, the present invention applies to semiconductor memory devices other than SRAM, D
RAM (Dynamic RAM), ROM (Read
0nly Memory), etc. Furthermore, the present invention can be applied to semiconductor integrated circuit devices having SRAM, such as one-chip microcomputers incorporating SRAM and gate arrays. [Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below. (1) The degree of integration of a semiconductor integrated circuit device having an SRAM can be improved. (2) The operating speed of a semiconductor integrated circuit device having an SRAM can be increased. (3) Operation reliability of a semiconductor integrated circuit device having an SRAM can be improved. (4) Power consumption of a semiconductor integrated circuit device having SRAM can be reduced. (5) The soft error resistance of a semiconductor integrated circuit device having an SRAM can be improved. (6) The electrical reliability of a semiconductor integrated circuit device having an SRAM can be improved. (7) The electrostatic breakdown voltage of a semiconductor integrated circuit device having an SRAM can be improved. (8) The yield in the manufacturing process of a semiconductor integrated circuit device having an SRAM can be improved.6 (9) The number of manufacturing steps in the manufacturing process of a semiconductor integrated circuit device having an SRAM can be reduced. (10) Two or more of the effects (1) to (9) above can be achieved simultaneously.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of an SRAM memory cell according to an embodiment of the present invention. FIG. 2 is a plan view of the memory cell. FIG. 3 is a chip layout diagram of the SRAM. 4 to 6 are enlarged block diagrams of main parts of the SRAM, FIG. 7 is a circuit diagram of the memory cell, and FIGS. 8 and 9 are equivalent circuit diagrams of the input/output section of the SRAM. 10 to 14 are plan views of memory cells shown for each manufacturing step of the SRAM manufacturing process. 15 to 20 are plan views of a memory cell array shown for each manufacturing step of the SRAM manufacturing process, FIGS. 21 and 22 are sectional views of peripheral circuits of the SRAM, and FIGS. FIG. 32 is a sectional view of a memory cell shown for each manufacturing step of the SRAM manufacturing process, and FIGS. 33 to 39 are diagrams for explaining the present invention in detail. In the figure, 1... semiconductor substrate, 2, 3... well region,
4...Element isolation insulating film, 6,12.24...Gate insulating film, 7,13.23.26...Gate material, 10.
11.17.18.19°20...Semiconductor region, 8
, 15.21.24.27.30...insulating film, 9,1
6...Side wall spacer, 14.22゜25
, 28.31...Connection hole, 29.33...Metal wiring, MC...Memory cell, Qt...MISFE for transfer
T, Qd...Drive MISFET, Qp...Load MISFET, C...Capacitive element, WL...Word line, DL...Complementary data line, Vss...Reference voltage,
Vcc: power supply voltage. Fig. 2 Fig. 7 Fig. Fig. Fig. ss Fig. 1 Fig. Fig. Fig. Fig. 2 0 0.1 0.2 0.3 Length of LDD part [μm] 0.1 0.2 0.3 Length of LDD part [μm]

Claims (1)

[Scope of Claims] 1. In a method for forming a semiconductor integrated circuit device having an SRAM in which a memory cell is formed by a transfer MISFET and a drive MISFET, a gate insulating film is formed on the main surface of the drive MISFET formation region of the substrate. a step of forming a first gate electrode with an intervening MISFE for driving the substrate;
Two types of impurities having a conductivity type opposite to that of the substrate and having different diffusion rates are introduced into the main surface of the T formation region in a self-aligned manner with respect to the first gate electrode, thereby forming a driving MI of a double drain structure.
Steps of forming SFET and MISF for transfer of the substrate
forming a second gate electrode on the main surface of the ET formation region with a gate insulating film interposed; and a step of forming a transfer M of the substrate.
A step of introducing a low concentration impurity of a conductivity type opposite to that of the substrate into the main surface of the ISFET formation region in a self-aligned manner with respect to the second gate electrode, and a step of introducing a low concentration impurity into the main surface of the ISFET formation region in a self-aligned manner with respect to the second gate electrode; forming a sidewall spacer, and introducing a high concentration impurity of a conductivity type opposite to that of the substrate into the main surface of the transfer MISFET formation region of the substrate in self-alignment with the sidewall spacer,
1. A method for forming a semiconductor integrated circuit device, comprising the step of forming a transfer MISFET having an LDD structure. 2. A source line formed in the same manufacturing process as a second gate electrode of the transfer MISFET is connected to the source region of the double drain structure of the drive MISFET. A method for forming a semiconductor integrated circuit device. 3. In the step of forming the drive MISFET with the double drain structure, after forming the first gate electrode, a sidewall spacer is formed on the sidewall of the first gate electrode in a self-aligned manner, and then 2. The method of forming a semiconductor integrated circuit device according to claim 1, further comprising introducing two types of impurities having different diffusion rates into the first gate electrode in a self-aligned manner. 4. In the step of forming the LDD structure transfer MISFET, after forming the second gate electrode, the low concentration impurity was introduced, and annealing was performed to stretch and diffuse the introduced impurity. 4. The method of forming a semiconductor integrated circuit device according to claim 1, further comprising a step of forming the sidewall spacer and then introducing the high concentration impurity. 5. In a method for forming a semiconductor integrated circuit device having an SRAM in which a memory cell is constituted by a transfer MISFET controlled by a word line and a driving MISFET connected to a source line, the first A step of forming a gate electrode, and a step of forming a second gate electrode of a MISFET for transfer of a memory cell in the upper layer of this first gate electrode, and a step of forming a word line and a source line in the same layer as this second gate electrode. A method for forming a semiconductor integrated circuit device, comprising: 6. The gate electrode of the driving MISFET is used as the first electrode,
In the method for forming a semiconductor integrated circuit device having an SRAM in which a capacitive element is disposed in a memory cell, the capacitive element is provided with a second electrode connected to the information storage node with a dielectric film interposed on the first electrode. 1. A method for forming a semiconductor integrated circuit device, characterized in that the electrode or the second electrode is formed of a polycrystalline silicon film deposited by a CVD method and into which impurities for reducing resistance are introduced during the deposition. 7. The gate electrode of the driving MISFET is used as the first electrode,
In the method for forming a semiconductor integrated circuit device having an SRAM in which a capacitive element is disposed in a memory cell, the capacitive element is provided with a second electrode connected to the information storage node with a dielectric film interposed on the first electrode. 1. A method for forming a semiconductor integrated circuit device, characterized in that the electrode or the second electrode is formed of a polycrystalline silicon film deposited by a CVD method using disilane as a source gas. 8. The gate electrode of the driving MISFET is used as the first electrode,
In a method for forming a semiconductor integrated circuit device having an SRAM in which a capacitive element having a second electrode connected to an information storage node with a dielectric film interposed on the first electrode is arranged in a memory cell, a CVD method is used. forming the first electrode from the deposited polycrystalline silicon film; and depositing the CVD on the first electrode.
1. A method for forming a semiconductor integrated circuit device, comprising: forming a dielectric film using a silicon oxide film deposited by a method. 9. The first electrode or the second electrode is a polycrystalline silicon film deposited by a CVD method and into which impurities are introduced to reduce the resistance value during the deposition, or a CVD method using disilane as a source gas. 9. The method for forming a semiconductor integrated circuit device according to claim 8, wherein the semiconductor integrated circuit device is formed of a polycrystalline silicon film. 10. One semiconductor region of the first driving MISFET and the second driving M in one semiconductor region of the transfer MISFET.
The gate electrode of the ISFET is connected to the first driving M
The first electrode is the gate electrode of the ISFET, and the first driving MIS
In a method of forming a semiconductor integrated circuit device having an SRAM in which a memory cell is a capacitive element in which a second electrode is connected to one semiconductor region of an FET, the first driving MISFET and the second driving MISFET are formed. At the same time, a step of forming a first electrode of a capacitive element with the gate electrode of the first waste MISFET, and
A step of forming a transfer MISFET in which one semiconductor region is connected to one semiconductor region of the SFET, and forming a second electrode of the capacitor by interposing a dielectric film on the first electrode of the capacitor. , a part of this second electrode connects one semiconductor region of the transfer MISFET and the second drive MISFET.
1. A method for forming a semiconductor integrated circuit device, comprising the step of connecting gate electrodes of SFETs. 11. The first electrode or the second electrode of the capacitive element is a polycrystalline silicon film deposited by a CVD method using disilane as a source gas, or an impurity deposited by a CVD method and reducing the resistance value during the deposition. 11. The method of forming a semiconductor integrated circuit device according to claim 10, wherein the semiconductor integrated circuit device is formed of a polycrystalline silicon film into which is introduced. 12. In a method for forming a semiconductor integrated circuit device having an SRAM in which a word line is integrally formed with a gate electrode of a MISFET for transfer of a memory cell, a gate is formed on a main surface of a formation region of a MISFET for transfer of a memory cell of a substrate. A step of forming an insulating film, a step of forming a polycrystalline silicon film deposited by CVD over the entire surface of the substrate including on the gate insulating film, and into which impurities to reduce the resistance value are introduced during the deposition. A step of depositing a high melting point metal silicide film over the entire surface of the substrate including the crystalline silicon film, and patterning each of the high melting point metal silicide film and the polycrystalline silicon film to remove the remaining polycrystalline silicon film and the high melting point metal. A method for forming a semiconductor integrated circuit device, comprising the step of forming a gate electrode of the transfer MISFET and a word line integrally connected thereto on the gate insulating film using a silicide film. 13. The semiconductor integrated circuit according to claim 12, wherein the polycrystalline silicon film underlying the gate electrode of the transfer MISFET and the word line connected thereto is deposited by a CVD method using disilane as a source gas. Method of forming the device. 14. The polycrystalline silicon film below the gate electrode of the transfer MISFET and the word line connected thereto is 5 [nm]
14. The method for forming a semiconductor integrated circuit device according to claim 12, wherein the semiconductor integrated circuit device is formed with a thickness of 100 [nm] or more. 15. In a method for forming a semiconductor integrated circuit device having an SRAM in which a memory cell is constituted by a transfer MISFET and a driving MISFET whose source region is connected to a source line, on the main surface of the driving MISFET formation region of the substrate. Forming a first gate electrode, forming a source region and a drain region on the main surface thereof to form a drive MISFET, and forming a gate insulating film on the main surface of the transfer MISFET formation region of the substrate. a step of depositing a silicon film over the entire surface of the substrate including on the gate insulating film; and a step of sequentially removing the silicon film on the source region of the driving MISFET and the insulating film thereunder to form a connection hole. a step of forming a high melting point metal silicide film on the entire surface of the substrate including the silicon film and connected to the source region of the driving MISFET through the connection hole; and a step of forming each of the high melting point metal silicide film and the silicon film. A second gate electrode made of a silicon film and a high melting point metal silicide film is formed on the gate insulating film by sequential patterning.
1. A method for forming a semiconductor integrated circuit device, comprising the step of forming a source line connected to a source region of an FET. 16. In a method for forming a semiconductor integrated circuit device having an SRAM in which a memory cell is constituted by a transfer MISFET and a drive MISFET, a step of forming a first gate insulating film on the main surface of the drive MISFET formation region of the substrate. a step of sequentially forming a silicon film, a first insulating film as an oxidation-resistant mask, and a second insulating film on the entire surface of the substrate including on the first gate insulating film; sequentially patterning each of the films in substantially the same pattern to form a first gate electrode of the driving MISFET using the silicon film; and forming a sidewall spacer on the sidewall of the first gate electrode. , MIS for board transfer
A step of forming a second gate insulating film by thermal oxidation on the main surface of the FET formation region, a step of forming a second gate electrode of the transfer MISFET on this second gate insulating film, and etching the entire surface of the substrate. A method for forming a semiconductor integrated circuit device, comprising the step of sequentially removing each of the second and first insulating films on the first gate electrode. 17. The first gate electrode of the driving MISFET is used as a first electrode of a capacitive element, and a dielectric film is interposed on the first gate electrode from which each of the first and second insulating films has been removed. 17. The method of forming a semiconductor integrated circuit device according to claim 16, wherein a second electrode of a capacitive element is formed. 18. In a method for forming a semiconductor integrated circuit device having an SRAM including a memory cell in which a gate electrode of a driving MISFET is connected to one semiconductor region of a transfer MISFET, the main region of the substrate where the driving MISFET is formed forming a first gate electrode on the main surface of the transfer MISFET formation region of the substrate and forming the first insulating film on the main surface of the transfer MISFET formation region;
forming a second insulating film thicker than the insulating film, and forming the one semiconductor region on the main surface of the transfer MISFET formation region;
removing a portion of the first insulating film on the first gate electrode of the ET and forming a connection hole that exposes at least a portion of the surface of one semiconductor region of the transfer MISFET;
connecting one semiconductor region of the transfer MISFET and a first gate electrode of the drive MISFET through the connection hole with a conductive layer formed above the first and second gate electrodes. A method for forming a semiconductor integrated circuit device, characterized in that: 19. A semiconductor having an SRAM that constitutes a memory cell in which the gate electrode of a drive MISFET is connected to one semiconductor region of a transfer MISFET, and a data line is connected to the other semiconductor region of the transfer MISFET of this memory cell. In the method of forming an integrated circuit device, the step of forming a first gate electrode on the main surface of the formation region of the drive MISFET of the substrate, and the step of forming the first gate electrode on the main surface of the formation region of the transfer MISFET of the substrate. forming a second gate electrode in a layer above the electrode, and forming the one semiconductor region and the other semiconductor region on the main surface of the transfer MISFET formation region; and one semiconductor region of the transfer MISFET. , the first gate electrodes of the driving MISFET are connected to each other by a conductive layer formed above the first and second gate electrodes, and the conductive layer and the same layer are connected to each other on the other semiconductor region of the transfer MISFET. forming an intermediate conductive layer; and connecting a data line to the other semiconductor region of the transfer MISFET via the intermediate conductive layer. Method. 20. In a method for forming a semiconductor integrated circuit device having an SRAM in which a memory cell is constituted by a driving MISFET and a load MISFET, the driving MISFET is formed on the main surface of the formation region of the driving MISFET of the memory cell of the substrate.
A step of forming a first gate electrode, a source region, and a drain region of the FET, and interposing a dielectric film on the first gate electrode of the driving MISFET to form the load MISFET.
A step of forming a second gate electrode of T and connecting this second gate electrode to the drain region of the driving MISFET, and interposing a gate insulating film on the second gate electrode of the load MISFET to 1. A method for forming a semiconductor integrated circuit device, comprising the step of forming a channel forming region, a source region, and a drain region of a MISFET. 21. The second gate electrode of the load MISFET is a polycrystalline silicon film deposited by a CVD method using disilane as a source gas, or a polycrystalline silicon film deposited by a CVD method, and an impurity is introduced to reduce the resistance value during the deposition of the parentheses. 21. The method for forming a semiconductor integrated circuit device according to claim 20, wherein the semiconductor integrated circuit device is formed using a polycrystalline silicon film. 22. The channel forming region of the load MISFET is 5
22. The method of forming a semiconductor integrated circuit device according to claim 21, wherein the semiconductor integrated circuit device is formed with a thickness of [nm] or more and 50 [nm] or less. 23. The gate insulating film of the load MISFET is CVD
22. The method of forming a semiconductor integrated circuit device according to claim 21, wherein the semiconductor integrated circuit device is formed using a silicon oxide film deposited by a method. 24. The semiconductor integrated circuit device according to each of claims 21 to 23, wherein the gate insulating film of the load MISFET is formed to have a thickness of 10 [nm] or more and 50 [nm] or less. Formation method. 25. In a method for forming a semiconductor integrated circuit device having a multilayer wiring structure in which an upper layer wiring is formed with an interlayer insulating film interposed above the lower layer wiring, each of a first wiring and a second wiring, which are lower layer wiring, is formed on a substrate. A step of separating the first wiring and the second wiring of the lower wiring by a predetermined distance, and using a plasma CVD method using tetraethoxysilane gas as a source gas on the entire surface of the substrate including the lower wiring, and separating the first wiring and the second wiring of the lower wiring. Dimension 2
a step of depositing a first silicon oxide film having a thickness of 1/2 or more;
A second silicon oxide film is applied to the entire surface of the substrate including the first silicon oxide film using a spin-on glass method, and then a step of baking the second silicon oxide film and etching the entire surface of the second silicon oxide film is performed. on the first wiring and the second wiring of the lower layer wiring.
A step of removing the second silicon oxide film on the wiring and leaving the second silicon oxide film in other areas, and a step of removing a third silicon oxide film on the entire surface of the substrate including the remaining second silicon oxide film using a CVD method. a step of depositing a silicon oxide film; a step of removing the first, second, and third silicon oxide films on the first wiring or the second wiring to form a connection hole; and a step of forming a connection hole on the third silicon oxide film. A method for forming a semiconductor integrated circuit device, comprising the steps of: forming an upper layer wiring connected to the first wiring or the second wiring through the connection hole. 26. Transfer MISF is installed on the main surface of the active region defined by the element isolation insulating film formed in the non-active region of the substrate.
In a method for forming a semiconductor integrated circuit device having an SRAM in which a memory cell is constituted by an ET and a driving MISFET, a ring-shaped planar shape is formed on the main surface of an active region forming region of a substrate, spaced apart from each other and regularly. and forming an element isolation insulating film on the main surface of the non-active region of the substrate by selective oxidation using the oxidation mask. A method for forming a featured semiconductor integrated circuit device. 27. The oxidation mask is arranged in a plurality of rows on the main surface of the active region forming region of the substrate, spaced apart from each other and at the same pitch in the first direction, and the oxidation mask is arranged in a row at the same pitch in the first direction, and the oxidation mask is arranged in a row at the same pitch in the first direction. In the next row in the second direction, the rows are spaced apart from each other and have the same pitch in the first direction, and 2 rows with respect to the previous row.
27. The method of forming a semiconductor integrated circuit device according to claim 26, wherein a plurality of semiconductor integrated circuit devices are arranged in a row with a pitch shifted by one-tenth of a pitch. 28. The memory cell is composed of two transfer MISFETs and two drive MISFETs, and the ring shape of the oxide mask is formed between two memory cells adjacent in the first direction and between these two memory cells. In two memory cells adjacent in the second direction, a total of four memory cells, each
1 transfer MISFET and 1 drive MISFET
, total of 4 transfer MISFETs, 4 drive MISs
28. The method of forming a semiconductor integrated circuit device according to claim 27, wherein the semiconductor integrated circuit device is formed in a shape in which FETs are connected in series. 29. Among the regularly arranged oxide masks, the oxide mask arranged at the end of the memory cell array is formed by a part of the ring shape formed based on the layout rule, and the oxide mask arranged at the end is 29. The semiconductor integrated circuit device according to claim 26, wherein a boundary region between the ring-shaped pattern and the non-active region in the extending direction is formed to be larger than at least a dimension corresponding to a bird's beak. How to form.