KR100192556B1 - Non-volatile memory device and manufacturing method thereof - Google Patents
Non-volatile memory device and manufacturing method thereof Download PDFInfo
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- KR100192556B1 KR100192556B1 KR1019950058904A KR19950058904A KR100192556B1 KR 100192556 B1 KR100192556 B1 KR 100192556B1 KR 1019950058904 A KR1019950058904 A KR 1019950058904A KR 19950058904 A KR19950058904 A KR 19950058904A KR 100192556 B1 KR100192556 B1 KR 100192556B1
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- 239000004065 semiconductor Substances 0.000 claims abstract description 18
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
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- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
본 발명은 비휘발성 메모리 소자 및 제조방법에 관한 것으로, 셀면적을 최대한 작게 형성하더라도 트랜지스터에 비해 특성의 열화정도가 현저히 낮기 때문에 고집적소자 제조에 적합한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device and a manufacturing method, and is suitable for fabricating a high density device because the degree of deterioration of characteristics is significantly lower than that of a transistor even when the cell area is made as small as possible.
본 발명에 따른 비휘발성 메모리 소자는 반도체기판; 상기 반도체기판위에 형성되고 저농도 불순물영역과 제1 및 제2 고농도 불순물영역을 갖는 제1 도전층; 상기 제1 및 제2 고농도 불순물영역상의 상기 제1도 전층상에 형성된 제1 절연막; 상기 저농도 불순물영역의 상기 제1도전층상에 형성된 박막절연부; 상기 박막절연부를 포함한 상기 제1 절연막의 일부분상에 형성된 제2 도전층을 포함하여 구성된다.A nonvolatile memory device according to the present invention includes a semiconductor substrate; A first conductive layer formed on the semiconductor substrate and having a low concentration impurity region and first and second high concentration impurity regions; A first insulating film formed on the first conductive layer on the first and second high concentration impurity regions; A thin film insulator formed on the first conductive layer in the low concentration impurity region; And a second conductive layer formed on a portion of the first insulating film including the thin film insulating portion.
또한 본 발명에 따른 비휘발성 메모리 소자의 제조방법은 반도체기판을 준비하는 단계; 상기 반도체기판상에 제1 도전층을 형성하는 단계; 상기 제1 도전층상에 제1 절연막을 형성하는 단계; 상기 제1 절연막을 제1 도전층의 일부분이 노출되도록 선택적으로 제거하는 단계; 상기 제1도 전층의 노출된 표면을 포함한 상기 제1 절연막상에 제2 절연막을 형성하는 단계; 상기 제2 절연막을 선택적으로 제거하여 박막절연부를 형성하는 단계; 상기 박막절연부와 제1절연막을 열처리하여 상기 제1 도전층에 저농도 불순물영역과 제1 및 제2 고농도 불순물영역을 형성하는 단계; 상기 박막절연부를 포함한 상기 제2 절연막위에 제2 도전층을 형성하는 단계를 포함하여 이루어진다.In addition, the manufacturing method of the nonvolatile memory device according to the present invention comprises the steps of preparing a semiconductor substrate; Forming a first conductive layer on the semiconductor substrate; Forming a first insulating film on the first conductive layer; Selectively removing the first insulating layer to expose a portion of the first conductive layer; Forming a second insulating film on the first insulating film including the exposed surface of the first full layer; Selectively removing the second insulating film to form a thin film insulating part; Heat-treating the thin film insulating portion and the first insulating film to form low concentration impurity regions and first and second high concentration impurity regions in the first conductive layer; And forming a second conductive layer on the second insulating film including the thin film insulating part.
Description
제1도는 종래 비휘발성 메모리 소자의 회로구성도.1 is a circuit diagram of a conventional nonvolatile memory device.
제2도는 본 발명에 따른 비휘발성 메모리 소자의 회로구성도.2 is a circuit diagram of a nonvolatile memory device according to the present invention.
제3a도는 본 발명에 따른 비휘발성 메모리 소자의 레이아웃도.3A is a layout diagram of a nonvolatile memory device according to the present invention.
제3b도는 본 발명에 따른 비휘발성 메모리 소자의 단면도.3B is a cross-sectional view of a nonvolatile memory device in accordance with the present invention.
제4a∼4e도는 본 발명에 따른 비휘발성 메모리 소자의 제조공정도.4A to 4E are manufacturing process diagrams of a nonvolatile memory device according to the present invention.
제5a, 5b도는 본 발명에 따른 비휘발성 메모리 소자의 데이터 쓰기, 읽기동작을 설명하기 위한 개략도.5A and 5B are schematic diagrams for explaining data write and read operations of a nonvolatile memory device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 반도체기판 12 : 제1 절연막11 semiconductor substrate 12 first insulating film
13 : 제1 도전층(비트라인) 13a, 13b : 제1 및 제2고농도영역13: first conductive layer (bit line) 13a, 13b: first and second high concentration regions
13c : 저농도영역 14, 14a : 제2절연막13c: low concentration region 14, 14a: second insulating film
15 : 제3절연막 15a : 박막절연부15: third insulating film 15a: thin film insulating portion
16 : A1층 16a : 제2도전층(워드라인)16: A1 layer 16a: 2nd conductive layer (word line)
본 발명은 비휘발성 반도체소자에 관한 것으로, 특히 소자의 집적도를 향상시킬 수 있도록 한 비휘발성 메모리 소자 및 제조방법에 관한 것이다.The present invention relates to a nonvolatile semiconductor device, and more particularly, to a nonvolatile memory device and a manufacturing method capable of improving the degree of integration of the device.
종래의 비휘발성 메모리 소자를 설명하면 다음과 같다.A conventional nonvolatile memory device is described as follows.
제1도는 종래의 비휘발성 메모리 소자의 회로구성도이다.1 is a circuit diagram of a conventional nonvolatile memory device.
상기 도면에 따르면, 종래의 비휘발성 메모리 소자의 1개의 MOS 트랜지스터(A)와 상기 MOS 트랜지스터(A)에 수평 및 수직방향으로 각각 연결된 비트라인(1)과 워드라인(2)으로 구성된 셀을 하나의 단위로하여 반복배열된 어레이부와, 상기 어레이부내의 특정셀을 선택하기 위한 어드레스 디코더(address decoder)(수직 및 수평디코더) 등을 포함하는 주변회로부로 구성되어 있다.According to the figure, one MOS transistor (A) of the conventional nonvolatile memory device and a cell consisting of a bit line (1) and a word line (2) connected to the MOS transistor (A) in the horizontal and vertical directions respectively And an peripheral circuit portion including an address decoder (vertical and horizontal decoders) for selecting specific cells in the array portion, and the like.
상기 구성으로 된 종래 비휘발성 메모리 소자의 동작을 간략하게 설명하면 다음과 같다.The operation of the conventional nonvolatile memory device having the above configuration will be briefly described as follows.
먼저, 데이터를 기억시키기 위해서는, 제1도와 같이, MOS 트랜지스터(A)의 채널(미도시)하부에 코딩이온주입(coding implant)을 실시하여 MOS 트랜지스터(A)를 선택적으로 온 혹은 오프상태가 되도록 만드는 방법을 사용한다.First, in order to store data, as shown in FIG. 1, a coding implant is performed under a channel (not shown) of the MOS transistor A so that the MOS transistor A is selectively turned on or off. Use the method of making
또는, 제1도와 같이, 콘택(B)마스크를 프로그래밍(programing)하여 선택적으로 콘택(B)을 열거나 닫도록 하는 리소그래픽(lithography) 방법을 사용하여 데이터를 저장한다.Alternatively, as shown in FIG. 1, data is stored using a lithography method of programming the contact B mask to selectively open or close the contact B. FIG.
상기에서 설명한 바와 같이, 종래 비휘발성 메모리 소자에 있어서는 다음과 같은 문제점이 있다.As described above, the conventional nonvolatile memory device has the following problems.
종래 비휘발성 메모리 소자에 있어서는 셀 어레이가 차지하는 면적을 줄이기 위해 소자들간의 격리폭 및 트랜지스터의 게이트 크기등을 작게 하는 것이 중요함을 감안할 때 상기 소자들간의 격리폭을 줄이게 되면 소자간의 격리에 문재가 생길 수 있다.Considering the importance of reducing the isolation width between the devices and the gate size of the transistor in order to reduce the area occupied by the cell array in the conventional nonvolatile memory device, if the isolation width between the devices is reduced, there is a problem in isolation between the devices. Can occur.
또한 종래 비휘발성 메모리 소자에 있어서 트랜지스터의 크기를 작게하는 것은 최소유효채널길이(Leff)에 의해 제한되므로 트랜지스터의 크기감소에 한계가 있다.In addition, in the conventional nonvolatile memory device, reducing the size of the transistor is limited by the minimum effective channel length (Leff), thereby limiting the size of the transistor.
따라서 종래 비휘발성 메모리 소자는 소자의 집적화에 적합하지 못하다고 볼 수 있다.Therefore, the conventional nonvolatile memory device may not be suitable for integration of the device.
본 발명은 상기 종래 문제점을 해결하기 위하여 안출한 것으로, 셀면적을 최대한 줄이더라도 양호한 소자격리가 가능하도록 하므로써 소자의 고집적화에 적합하도록 한 비휘발성 메모리 소자 및 제조방법을 제공함에 그 목적이 있다.Disclosure of Invention The present invention has been made in view of the above-described problems, and an object thereof is to provide a nonvolatile memory device and a manufacturing method suitable for high integration of a device by enabling good device isolation even if the cell area is reduced as much as possible.
상기 목적을 달성하기 위한 본 발명에 따른 비휘발성 메모리 소자는 반도체기판, 상기 반도체기판위에 형성되고 저농도 불순물영역과 제1 및 제2 고농도 불순물영역을 갖는 제1도전층, 상기 제1 및 제2고농도 불순물영역상의 상기 제1도전층상에 형성된 제1절연막, 상기 저농도 불순물영역의 상기 제1도전층상에 형성된 박막절연부, 상기 박막절연부를 포함한 상기 제1절연막의 일부분상에 형성된 제2도전층을 포함하여 구성된다.A nonvolatile memory device according to the present invention for achieving the above object is a semiconductor substrate, a first conductive layer formed on the semiconductor substrate and having a low concentration impurity region and the first and second high concentration impurity regions, the first and second high concentration A first insulating film formed on the first conductive layer on the impurity region, a thin film insulating portion formed on the first conductive layer on the low concentration impurity region, and a second conductive layer formed on a portion of the first insulating film including the thin film insulating portion. It is configured by.
또한 본 발명에 따른 비휘발성 메모리 소자의 제조방법은 반도체기판을 준비하는 단계, 상기 반도체기판상에 제1도전층을 형성하는 단계; 상기 제1도전층상에 제1절연막을 형성하는 단계, 상기 제1절연막을 제1도전층의 일부분이 노출되도록 선택적으로 제거하는 단계, 상기 제2절연막을 선택적으로 제거하여 박막절연부를 형성하는 단계, 상기 제1도전층의 노출된 표면을 포함한 상기 제1절연막상에 제2절연막을 형성하는 단계, 상기 박막절연부와 제1절연막을 열처리하여 상기 제1도전층에 저농도 불순물영역과 제1 및 제2고농도 불순물영역을 형성하는 단계, 상기 박막절연부를 포함한 상기 제2절연막위에 제2도전층을 형성하는 단계를 포함하여 이루어진다.In addition, the method of manufacturing a nonvolatile memory device according to the present invention comprises the steps of preparing a semiconductor substrate, forming a first conductive layer on the semiconductor substrate; Forming a first insulating film on the first conductive layer, selectively removing the first insulating film so that a portion of the first conductive layer is exposed, selectively removing the second insulating film to form a thin film insulating part; Forming a second insulating film on the first insulating film including the exposed surface of the first conductive layer, heat treating the thin film insulating part and the first insulating film to form a low concentration impurity region and first and first layers in the first conductive layer. And forming a second high concentration impurity region, and forming a second conductive layer on the second insulating film including the thin film insulating portion.
본 발명을 첨부된 도면을 참조하여 상세히 설명한다.The present invention will be described in detail with reference to the accompanying drawings.
제2도는 본 발명에 따른 비휘발성 메모리 소자의 회로구성도이다.2 is a circuit diagram of a nonvolatile memory device according to the present invention.
상기 도면에 따르면, 본 발명에 따른 비휘발성 메모리 소자는 1개의 다이오드(Diode)에 수직방향 및 수평방향으로 각각 연결된 워드라인(16a)과 비트라인(13)으로 구성된 셀을 하나의 단위로 하여 반복배열된 어레이(array)부에 상기 어레이부내에 특정셀을 선택하기 위한 어드레스 디코더(address decoder) 등을 포함하는 주변회로부로 구성되어 있다.According to the drawing, a nonvolatile memory device according to the present invention repeats a cell composed of a word line 16a and a bit line 13 connected to one diode in a vertical direction and a horizontal direction, respectively, as one unit. The array unit includes a peripheral circuit unit including an address decoder and the like for selecting a specific cell in the array unit.
또한 제3a도는 본 발명에 따른 비휘발성 메모리 소자의 레이아웃도이다.3A is a layout diagram of a nonvolatile memory device according to the present invention.
상기 도면에 따르면, 본 발명에 따른 비휘발성 메모리 소자는 워드라인(16a)과 비트라인(13)이 서로 교차배열되고, 상기 교차배열되는 부분중 소정부분에 주변보다 더 얇게 박막절연부(15a)가 형성되어 있다.According to the drawing, in the nonvolatile memory device according to the present invention, the word line 16a and the bit line 13 are cross-aligned with each other, and the thin film insulating portion 15a is thinner than a peripheral portion of the cross-arranged portion. Is formed.
그리고 제3b도는 본 발명에 따른 비휘발성 메모리 소자의 단면도이다.3B is a cross-sectional view of the nonvolatile memory device according to the present invention.
상기 도면에 따르면, 본 발명에 따른 비휘발성 메모리 소자는 반도체기판(11)과, 상기 반도체기판(11)상에 형성된 제1절연막(12)과, 상기 제1절연막(12)상에 형성되고 제1 및 제2고농도 영역(13a,13b)들과 저농도 영역(13c)을 같는 제1도전층(13)과, 상기 제1 및 제2고농도영역(13a,13b)들상에 형성된 제2절연막(14a)과, 상기 제1도전층(13)의 저농도영역(13c)상에 형성된 박막절연부(15a)와, 상기 박막졀연부(15a)를 포함한 상기 제2절연막(14a)위에 형성된 제2도전층(16a)을 포함하여 구성된다.According to the drawings, the nonvolatile memory device according to the present invention is formed on the semiconductor substrate 11, the first insulating film 12 formed on the semiconductor substrate 11, and the first insulating film 12. The first conductive layer 13 having the same first and second high concentration regions 13a and 13b and the low concentration region 13c, and the second insulating film 14a formed on the first and second high concentration regions 13a and 13b. ) And a second conductive layer formed on the second insulating film 14a including the thin film insulating portion 15a formed on the low concentration region 13c of the first conductive layer 13 and the thin film insulation portion 15a. It comprises 16a.
여기서, 상기 제1도전층은 비트라인으로 사용되고, 상기 제2도전층(16a)는 워드라인으로 사용된다.In this case, the first conductive layer is used as a bit line, and the second conductive layer 16a is used as a word line.
한편 상기 구성도로된 비휘발성 메모리 소자의 제조방법을 설명하면 다음과 같다.Meanwhile, a manufacturing method of the nonvolatile memory device having the configuration diagram will be described below.
제 4a∼4e도는 본 발명에 따른 비휘발성 메모리 소자의 제조공정도이다.4A to 4E are manufacturing process diagrams of a nonvolatile memory device according to the present invention.
본 발명에 따른 비휘발성 메모리소자는 먼저 제4a도에 도시된 바와 같이 반도체기판(11)을 준비하고, 상기 반도체기판(11)위에 제1절연막(12)과, 상기 제1절연막(12)위에 다결정 실리콘을 증착하여 제1도전층(13) 및 상기 제1도전층(13)위에 PSG(Phospho Silicate Glass) 물질을 증착하여 제2절연막(14)을 각각 형성한다.In the nonvolatile memory device according to the present invention, a semiconductor substrate 11 is first prepared as shown in FIG. 4A, and a first insulating film 12 and a first insulating film 12 are disposed on the semiconductor substrate 11. By depositing polycrystalline silicon, a PSG (Phospho Silicate Glass) material is deposited on the first conductive layer 13 and the first conductive layer 13 to form a second insulating layer 14, respectively.
이때 상기 제1도전층(13)은 비트라인을 사용한다.In this case, the first conductive layer 13 uses a bit line.
이어서 제4b도에 도시된 바와 같이, 상기 제2절연막(14)을 선택적으로 제거하여 상기 제1도전층(13)의 일부분이 노출되도록 한다.Subsequently, as shown in FIG. 4B, the second insulating layer 14 is selectively removed to expose a portion of the first conductive layer 13.
그다음 제4c도에 도시된 바와같이, 상기 제1도전층(13)의 노출된 표면을 포함한 상기 제2절연막(14a)의 노출된 표면위에 절연물질을 증착하여 제3절연막(15)을 형성한다.Next, as shown in FIG. 4C, an insulating material is deposited on the exposed surface of the second insulating layer 14a including the exposed surface of the first conductive layer 13 to form a third insulating layer 15. .
이어서 상기 제3절연막(15)과 상기 제2절연막(14a)의 불순물이 상기 제1도전층(13) 부분에 확산되도록 상기 제3절연막(15)과 상기 제2절연막(14a)을 열처리하여 상기 제2절연막(14a)과 접촉하는 제1도전층(13) 부분에 제1 및 제2고농도영역(13a)(13b)들을 각각 형성하고, 상기 제3절연막(15)과 접촉하는 제1도전층(13) 부분에 저농도영역(13c)을 형성한다.Subsequently, the third insulating layer 15 and the second insulating layer 14a are heat-treated so that impurities of the third insulating layer 15 and the second insulating layer 14a are diffused to the portion of the first conductive layer 13. First and second high concentration regions 13a and 13b are formed in portions of the first conductive layer 13 in contact with the second insulating layer 14a, and the first conductive layer is in contact with the third insulating layer 15. The low concentration region 13c is formed in the portion (13).
그다음 제4d도에 도시된 바와 같이, 상기 제3절연막(15)을 상기 저농도영역(13c)의 상기 제1도전층(13)부분에만 남도록 에치백하여 박막절연부(15a)를 형성한다.Next, as shown in FIG. 4D, the third insulating layer 15 is etched back so as to remain only in the first conductive layer 13 portion of the low concentration region 13c to form a thin film insulating portion 15a.
이때 상기 박막절연부(15a)는 상기 저농도영역(13c)과 접촉하는 부분을 얇게 형성한다.In this case, the thin film insulating part 15a forms a thin portion in contact with the low concentration region 13c.
이어서 상기 박막절연부(15a)를 포함한 상기 제2절연막(14a)의 노출된 표면위에 A1층(16)을 증착한다.Subsequently, an A1 layer 16 is deposited on the exposed surface of the second insulating film 14a including the thin film insulating portion 15a.
그다음 제4e도에 도시된 바와 같이, 사진석판술(photolithography) 및 사진식각공정에 의해 상기 A1층(16)을 선택적으로 제거하여 제2도전층(16a)을 형성하므로써 비휘발성 소자의 제조를 완료한다.Then, as shown in FIG. 4E, the A1 layer 16 is selectively removed by photolithography and photolithography to form the second conductive layer 16a, thereby completing the fabrication of the nonvolatile device. do.
이때 상기 제2도전층(16a)은 워드라인으로 사용한다.In this case, the second conductive layer 16a is used as a word line.
상기와 같이 제조되는 본 발명에 따른 비휘발성 메모리 소자의 동작으로 제5a∼5b도를 참조하여 설명하면 다음과 같다.The operation of the nonvolatile memory device according to the present invention manufactured as described above will be described with reference to FIGS. 5A to 5B.
제5a도는 본 발명에 따른 비휘발성 소자의 1데이터 쓰기동작을 설명하기 위한 개략도이고, 제5b도는 본 발명에 따른 비휘발성 소자의 1데이터 읽기 동작을 설명하기 이한 개략도이다.5A is a schematic diagram for explaining one data write operation of the nonvolatile device according to the present invention, and FIG. 5B is a schematic diagram for explaining one data read operation of the nonvolatile device according to the present invention.
본 발명에 따른 비휘발성 메모리 소자의 1데이터 쓰기동작은, 먼저 제5a도에 도시된 바와 같이, 1데이터를 쓰려고 하는 셀을 선택한 다음 비트라인(13)에 박막절연부(15a)를 구성하는 박막의 파괴전압 보다 큰 전압을 인가하여 상기 박막절연부(15a)의 박막절연층을 파괴하면 셀을 다이오드에 PN접합(Al-n-다결정 실리콘)이 형성된다.In the one-data write operation of the nonvolatile memory device according to the present invention, first, as shown in FIG. When the thin film insulating layer of the thin film insulating portion 15a is applied by applying a voltage larger than the breakdown voltage of, the cell forms a PN junction (Al-n - polycrystalline silicon) in the diode.
한편 본 발명에 따른 비휘발성 메모리 소자의 1데이터 읽기동작은, 제5b도에 도시된 바와 같이, 비트라인(13)과 워드라인(16a) 사이에 전압을 인가하면 PN 접합을 통해 전류가 흐르게 되고, 이 전류를 감지증폭기(sense amplifier)에서 감지하게 된다.Meanwhile, in one data read operation of the nonvolatile memory device according to the present invention, as shown in FIG. 5B, when a voltage is applied between the bit line 13 and the word line 16a, a current flows through the PN junction. This current is then sensed by a sense amplifier.
반대로 데이터가 1이 아닌 경우, 즉 0의 데이터를 쓴 경우는 워드라인(16a)과 비트라인(13) 사이의 박막절연층이 파괴되지 않고 남아 있게 되므로써 전류가 흐르지 못하게 되어 0으로 인식하게 된다.On the contrary, in the case where the data is not 1, that is, when the data of 0 is written, the thin film insulating layer between the word line 16a and the bit line 13 remains unbroken so that current does not flow and is recognized as 0.
상기에서 설명한 바와 같이, 본 발명에 따른 비휘발성 메모리 소자에 있어서는 다음과 같은 효과가 있다.As described above, the nonvolatile memory device according to the present invention has the following effects.
본 발명에 따른 비휘발성 메모리 소자에 있어서는 셀어레이부내에서 통상적인 LOCOS(LOCal Oxidation of Silicon) 공정에 의한 소자격리 방식을 사용하지 않으므로 더 양호하면서 작은 면적의 소자격리가 가능하다.In the non-volatile memory device according to the present invention, since the device isolation method by the LOCOS process is not used in the cell array unit, device isolation of a smaller area is possible.
또한 본 발명에 따른 비휘발성 메모리 소자에 있어서는 셀의 면적을 작게 하더라도 종래의 트랜지스터를 이용한 소자에 비해 특성의 열화정도가 현저히 개선된다.In addition, in the nonvolatile memory device according to the present invention, the degree of deterioration of characteristics is remarkably improved as compared with a device using a conventional transistor even if the cell area is reduced.
그리고 본 발명에 따른 비휘발성 메모리 소자에 있어서는 작은 면적내에서 복수개의 셀어레이를 상, 하 방향으로 적층할 수 있으므로 셀의 집적도를 향상시킬 수 있다.In the nonvolatile memory device according to the present invention, since a plurality of cell arrays can be stacked in a vertical direction within a small area, the degree of integration of cells can be improved.
Claims (4)
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