JPH03234053A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To protect power supply and internal elements from breakdown or damage and to enable quick and efficient current supply by providing a power supply protective circuit for a logic circuit section where the collector and the gate of an isolated gate bipolar transistor having a gate isolation film substantially as thick as an MOS transistor are connected with power supply wiring and the emitter thereof is connected with ground wiring. CONSTITUTION:Collector electrode 72 and gate electrode 73 of an isolated gate bipolar transistor (IGBT 7) having a gate oxide film 74 substantially as thick as a high breakdown strength MOS transistor are connected with power supply winding VDD and the emitter electrode 71 thereof is connected with ground winding VSS, thus forming a power supply protective circuit for a logic circuit section.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and in particular includes a logic circuit section including a MOS transistor and another Mo8 transistor having a gate insulating film thicker than the above-mentioned MOS transistor. The present invention is applied to a semiconductor integrated circuit device having a high voltage output buffer circuit section.

[Conventional technology]

FIG. 2(a) is a sectional view of a conventional semiconductor chip, and FIG. 2(b) is a circuit diagram of its power protection circuit.

This conventional example has a logic circuit section including a pMOS transistor 8 and a high breakdown voltage output including a P-type high breakdown voltage offset gate MO3) transistor 9 and an NPN) transistor 10 having a gate oxide film 94 thicker than the gate oxide film 84 of the pMOS transistor 8. This is a semiconductor integrated circuit device including a buffer circuit section, and a low-voltage power protection diode 11 is inserted into the power protection circuit, and the PN junction reverse breakdown voltage of this diode is appropriately controlled by the amount of ion implantation, etc. For example, if a power supply latch-up occurs at 15V in a semiconductor integrated circuit device with a maximum rated voltage of 7V, it is necessary to appropriately control the amount of ion implantation, etc. By setting the reverse withstand voltage of the power supply diode to, for example, IOV, even if an excessive voltage is momentarily applied between the power supply and the ground, the reverse current of the power supply protection diode will flow, and the logic circuit section will be protected. The voltage rise between the power supply and the ground was suppressed, and destruction and damage to the power supply and internal elements due to power supply latch-up and the like were prevented.

[Problem to be solved by the invention]

In the conventional semiconductor integrated circuit device described above, it is necessary to appropriately control the reverse breakdown voltage of the power protection diode, so conditions such as ion implantation amount and heat treatment conditions must be set to obtain the required reverse breakdown voltage. On the other hand, the P-type diffusion layer of the PN junction anode region 113 used in this power protection diode is similar to the base region 105 of the P-type diffusion layer (for example, NPN) transistor 10 of another element formed on the same chip. , the offset train region 97 of the high voltage offset gate MOS transistor 9, etc.). However, for example, in order to increase the hPE of an NPNt-transistor, it is preferable that the concentration of the base layer, that is, the amount of ions implanted when forming the base layer, is small, but if the amount of ions implanted in the base layer is small, the breakdown voltage of the PN junction of the power protection diode (because the impurity concentration of the junction decreases), and the concentration of the offset part of the offset gate MOS transistor is higher than that of the offset gate MOS transistor.
There is a correlation with the withstand voltage of the S transistor, and in order to obtain the required characteristics of each element, it is desirable to be able to independently set the formation conditions of the P-type diffusion layer, but in the past this was often done under common conditions. Therefore, given the restrictions on the characteristics of the element, especially when giving priority to the withstand voltage setting of the power protection diode,
The disadvantage is that the characteristics of other elements are determined by the conditions, making it difficult to set conditions that will yield the best characteristics of each element.

[Means to solve the problem]

The present invention provides a semiconductor integrated circuit device having a logic circuit section including a first Mo3) transistor and a high voltage output buffer circuit section including a second MOS transistor having a gate insulating film thicker than the first MOS transistor.
A power protection circuit for the logic circuit section, wherein the collector and gate of an insulated gate bipolar transistor having a gate insulating film having substantially the same thickness as the second MOS transistor are connected to a power supply wiring, and the emitter is connected to an installation wiring, respectively. That is what it is.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1(a) is a cross-sectional view of a semiconductor chip showing an embodiment of the present invention, and FIG. 1(b) is a power protection circuit diagram of the embodiment.

This embodiment is a P-type high voltage off-cell transistor including a logic circuit section including a pMOS transistor 8 (first MOS transistor) and a gate oxide film 94 thicker than the pMOS transistor. and NPN) - In a semiconductor integrated circuit device having a high voltage output buffer circuit section including a transistor 10, an insulated gate having a gate oxide film 74 having substantially the same thickness (formed in the same process) as a high voltage MOS transistor. It has a power protection circuit for the aforementioned logic circuit section in which the collector electrode 72 and gate electrode 73 of the bipolar transistor (IGBT7) are connected to the power supply wiring (DD), and the emitter electrode 71 is connected to the ground wiring V55.

When a voltage higher than the threshold voltage VT (for example, 10V) of the IGBT of the power protection circuit is applied between the power supply wiring V1) and the ground wiring VSS, the IGBT turns on and the overvoltage is applied between the power supply wiring and the ground wiring. This can be prevented.

Because it does not use conventional low voltage power protection diodes,
There is no restriction on the diffusion conditions of the offset portion of the high voltage offset gate MOS transistor due to the diffusion conditions of the power supply protection diode. The power supply voltage of the logic circuit section is, for example, 5 volts, and the power supply voltage of the high voltage output buffer circuit section is 100 volts or more.
Although the threshold voltage of the high-voltage offset gate MOS transistor and the IGBT threshold voltage are not unrelated at 200 volts, etc., even if the IGBT threshold voltage is set to the value necessary for power supply protection, the high-voltage output buffer circuit will not operate. It will not cause any hindrance.

Furthermore, IGBTs can operate at higher current densities than ordinary MOS transistors, and have a faster turn-on time than ordinary bipolar transistors, so they can provide efficient and prompt power protection.

Furthermore, since the NPN transistor and the P-type high-voltage offset gate MOS)-run transistor are provided on the same chip, the base of the NPN transistor and the offset gate M
Although it is common to form the offset train of the OS transistors at the same time, there are fewer restrictions on the setting conditions since there is no need to consider the withstand voltage of the power protection diode as in the conventional method.

FIG. 3 is a longitudinal sectional view of a semiconductor chip showing a modification of one embodiment.

A power protection circuit using an IGBT 7 is attached to a logic circuit section consisting of a low-voltage MOS transistor 8 and an nMOS transistor 13, and a high-voltage output buffer circuit is configured with a high-voltage N-channel VDMos transistor 12. Unlike conventional methods, it is not necessary to form the P-type diffusion layer of the low-voltage power protection diode at the same time as the formation of the P-type base of the VDMOS transistor.
It becomes possible to set optimal conditions for transistors. In addition, V
Gate oxide film 124 of DMOS transistor 12 and IG
It is formed in the same process as the gate oxide film 74 of BT, and is thicker than the gate oxide film M84.134 of CMOS.

〔Effect of the invention〕

As explained above, the present invention inserts an IGBT with a gate oxide film thicker than the MOS transistor in the logic circuit section into a power supply protection circuit, and places the gate and collector on the power supply (VDD) side.
By connecting the emitter to the ground (Vss) side, when a voltage higher than the threshold voltage of the IGBT with a thick gate oxide film is applied between the power supply and the ground, this IGBT turns on, and the IGBT is connected between the power supply and the ground. By flowing the on-current of the IGBT between the power supply and ground of the logic circuit, the voltage rise between the power supply and ground of the logic circuit is suppressed, and the power supply and internal elements are prevented from being destroyed or damaged. It can be prevented. Furthermore, IGBTs can allow a larger current to flow per unit area than normal MOSFETs, and the turn-on time is faster than that of normal bipolar transistors, so current can flow efficiently and quickly. In addition, this power supply protection circuit does not have a conventional low-voltage power supply diode, and there is no need to set the reverse breakdown voltage depending on the amount of ion implantation or heat treatment conditions, so a high-voltage output buffer formed on the same chip is used. Elements that make up the circuit (NPN) transistors, high voltage offset gate MOS
Since there are no restrictions on the characteristics of transistors or VDMOS transistors, it is possible to design under conditions that obtain the best characteristics of these elements.

[Brief explanation of drawings]

FIG. 1(a) is a vertical cross-sectional view showing one embodiment of the present invention.
Figure (b) is a circuit diagram of the power supply protection circuit of the embodiment, and Figure 2 (a)
) is a longitudinal sectional view showing a conventional example, FIG. 2(b) is a circuit diagram of a conventional power protection circuit, and FIG. 3 is a longitudinal sectional view showing a modification of the embodiment. 1... P-type St substrate, 2a to 2f... N-type buried layer,
3...P-type punching is a diffusion layer, 4a to 4f...N-type evitacal layer, 5...field oxide film, 6...interlayer isolation film, 7...IGBT, 71...IGBT Emitter electrode of 72...Collector electrode of IGBT, 73
... IGBT gate electrode, 74 ... IGBT gate oxide film, 75 ... IGBT collector region, 76
...IGBT emitter region, 77...IGBT
base region, 8... pMOS transistor, 81...
...PMOS transistor source electrode, 82...p
Drain ti of MOS transistor, 83...pMO
Gate electrode of S transistor, 84... Gate oxide film of pMOS transistor, 85... Source region of pMO3) transistor, 86... Train region of pMOS transistor, 9... High voltage offset gate MOS
Source electrode of transistor, 91...9, 92...
Drain electrode 9, gate electrode 93...9, 94...
...9 gate oxide film, 95...9 source region, 9
6...9 offset train areas, 101.・NP
N) transistor, 101...10 emitter electrodes, 1
02...10 base electrodes, 103...10 collector electrodes, 104...10 emitter regions, 105...
...10 base area, 106...10 collector extraction area, 11...power protection diode, 111...
11 anode electrodes, 112...11 cathode electrodes, 113...11 anode regions, 114...11
cathode region, 12...VDMOS transistor,
121...12 source electrodes, 122...12 gate oxide films, 123...12 drain electrodes, 124
...12 gate oxide film, 125...12 drain lead region, 126...12 source region, 127-
1,127-2...12 P-type base regions, 128-
1,128-2...12 source regions.

Claims (1)

[Claims] In a semiconductor integrated circuit device having a logic circuit section including a first MOS transistor and a high voltage output buffer circuit section including a second MOS transistor having a gate insulating film thicker than the first MOS transistor, the second MOS transistor A power protection circuit for the logic circuit portion is provided, the collector and gate of an insulated gate bipolar transistor having a gate insulating film having substantially the same thickness as that of the transistor are connected to a power supply wiring, and the emitter is connected to a ground wiring. Semiconductor integrated circuit device.