JPH03234028A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03234028A JPH03234028A JP3032390A JP3032390A JPH03234028A JP H03234028 A JPH03234028 A JP H03234028A JP 3032390 A JP3032390 A JP 3032390A JP 3032390 A JP3032390 A JP 3032390A JP H03234028 A JPH03234028 A JP H03234028A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate electrode
- conductive film
- forming
- titanium
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000000034 method Methods 0.000 claims abstract description 11
- 238000000137 annealing Methods 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims abstract description 4
- 230000008569 process Effects 0.000 claims abstract description 3
- 238000001039 wet etching Methods 0.000 claims abstract description 3
- 239000012535 impurity Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 14
- 238000002844 melting Methods 0.000 claims description 6
- 230000008018 melting Effects 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 18
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 10
- 239000011574 phosphorus Substances 0.000 abstract description 10
- 229920005591 polysilicon Polymers 0.000 abstract description 10
- 229910052710 silicon Inorganic materials 0.000 abstract description 10
- 239000010703 silicon Substances 0.000 abstract description 10
- 229910021341 titanium silicide Inorganic materials 0.000 abstract description 9
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 abstract description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052719 titanium Inorganic materials 0.000 abstract description 7
- 239000010936 titanium Substances 0.000 abstract description 7
- 229910052750 molybdenum Inorganic materials 0.000 abstract description 6
- 239000011733 molybdenum Substances 0.000 abstract description 6
- 239000000969 carrier Substances 0.000 abstract description 5
- 230000006866 deterioration Effects 0.000 abstract description 5
- 238000005468 ion implantation Methods 0.000 abstract description 3
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 abstract description 2
- 229910021344 molybdenum silicide Inorganic materials 0.000 abstract description 2
- 125000006850 spacer group Chemical group 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 description 12
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- -1 gradyna Chemical compound 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は半導体装置のＭＯＳ型トランジスタの製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a MOS transistor of a semiconductor device.
［従来の技術］
半導体装置の微細化、高集積化に伴いＭＯＳ型トランジ
スターも微細化されてきている。しかし素子寸法を微細
化することＫよりホットキャリアによる特性劣化という
問題が生じてきている。この問題を解決するためにＬＤ
Ｄ （ＬｉｇｈｔｌｙＤｏｐθｄ Ｄｒａｉｎ ）とい
う構造が提案されているが、このＬＤＤをさらに改良し
た構造が次の文献ニ掲載されティる。（Ｒ，ＩＺＡＷＡ
、Ｔ、ＫＵＲＥ、Ｅ、ＴＡＫＥＤＡ、−ＴＨＥ 工Ｍ
ＰＡＯＴ ＯＦ ＧＡＴＥ−ＤＲＡ 工
Ｎ Ｏ■ ＫＲＬＡＰＰＥＤ ＬＤＤ（ＧＯ
ＬＤ） ＦＯＲＤＫＥＰ ＳＵＢＭＩＯＲＯＭ
ＶＬＳＩ’ Ｓ”、工ＥＤＭ Ｔｅｃｈ
Ｄｉ 、ＰＰ３８−ＰＰ４１１９８７、）この文
献による製造方法を第２図を用いて説明する。第２図に
おいて２０１は、Ｐ型半導体基板、２０２はゲート酸化
膜、２０３は多結晶シリコン膜、２０４は自然酸化膜、
２０５は多結晶シリコン膜、２０６はシリコン酸化膜、
２０７は不純物濃度のうすいル型不純物層、２０８は酸
化膜によるサイドウオール、２０９は不純物濃度の濃い
ル型不純物層、２１０は酸化膜であるまずＰ型半導体基
板２０１を熱酸化することでゲート酸化膜２０２を形成
する。次にＣＶＤ法により多結晶シリコン膜２０３を薄
く形成した後、空気中に放置して５〜１０Ｘの自然酸化
膜２０４を形成する。続いてｃ’ｖｎ法により多結晶シ
リコン膜２０５．シ、リコン酸化膜２０６を順次形成す
る。次に第２図（α）のよりにシリコン醸化膜２０６の
不要部分を写真蝕刻法により除去する。次に、第２図（
ｂ）のように酸化膜２０６をマスクにドライエツチング
を行うことによって多結晶シリコン膜２９５の不要部分
を除去する。次にシリコン酸化膜２０６および多結晶シ
リコン＄２０５をマスクにル型不純物であるリンをイオ
ン注入することによりｎ型不純物層２０７を形成する。[Prior Art] As semiconductor devices become smaller and more highly integrated, MOS transistors are also becoming smaller. However, miniaturization of element dimensions has led to the problem of deterioration of characteristics due to hot carriers. To solve this problem, LD
A structure called D (LightlyDopθd Drain) has been proposed, and a structure that is a further improvement of this LDD is published in the following document. (R, IZAWA
,T,KURE,E,TAKEDA,-THE ENGM
PAOT OF GATE-DRA ENG NO KRLAPPED LDD (GO
LD) FORDKEP SUBMIOROM
VLSI'S", Engineering EDM Tech
Di, PP38-PP411987,) The manufacturing method according to this document will be explained using FIG. In FIG. 2, 201 is a P-type semiconductor substrate, 202 is a gate oxide film, 203 is a polycrystalline silicon film, 204 is a natural oxide film,
205 is a polycrystalline silicon film, 206 is a silicon oxide film,
207 is a rectangular impurity layer with a low impurity concentration, 208 is a side wall made of an oxide film, 209 is a rectangular impurity layer with a high impurity concentration, and 210 is an oxide film. First, the P-type semiconductor substrate 201 is thermally oxidized to oxidize the gate. A film 202 is formed. Next, after forming a thin polycrystalline silicon film 203 by the CVD method, it is left in the air to form a natural oxide film 204 of 5 to 10X. Subsequently, a polycrystalline silicon film 205. is formed using the c'vn method. Then, a silicon oxide film 206 is sequentially formed. Next, as shown in FIG. 2(a), unnecessary portions of the silicon enhancement film 206 are removed by photolithography. Next, see Figure 2 (
As shown in b), unnecessary portions of the polycrystalline silicon film 295 are removed by dry etching using the oxide film 206 as a mask. Next, an n-type impurity layer 207 is formed by ion-implanting phosphorus, which is an R-type impurity, using the silicon oxide film 206 and the polycrystalline silicon $205 as a mask.
次にＣＶＤ法によりシリコン酸化膜２０日を形成後ドラ
イエツチングを行うことにより第２図（Ｃ）のよ５にシ
リコン酸化膜によるサイドウオール絶縁膜２０日を形成
する。次に第２図（ｄ）のようにウェット雰囲気中で８
００℃の酸化を行うことにより酸化膜２１０を形成する
。次にゲート電極２０３．２０５．酸化膜２０６．サイ
ドウオール絶縁膜２０８をマスクにル型不純物であるヒ
素をイオン注入することによりル型不純物層２０９を形
成する。Next, a 20-day silicon oxide film is formed by the CVD method, and then dry etching is performed to form a 20-day sidewall insulating film made of a silicon oxide film as shown in FIG. 2(C). Next, as shown in Figure 2(d), 8
An oxide film 210 is formed by performing oxidation at 00°C. Next, gate electrodes 203.205. Oxide film 206. A R-type impurity layer 209 is formed by ion-implanting arsenic, which is a R-type impurity, using the sidewall insulating film 208 as a mask.
［発明が解決しようとする課題］
しかし、前述の従来技術では酸化膜２１０の横方向の長
さによりＭＯ８型トランジスターの特性が太き（変化す
るが、この横方向の長さは多結晶シリコン膜２０３の膜
圧とウェット雰囲気中の酸化条件により決定されるので
、寸法制御が難しく特にＭＯＳ型トランジスタのゲート
長がサブミクロン領域まで微細化されていると、酸化ｙ
Ｉ２１０の横方向の長さの寸法のバラツキによりトラン
ジスタ特性が大きく変化してしまうという課題を有する
。[Problems to be Solved by the Invention] However, in the above-mentioned conventional technology, the characteristics of the MO8 type transistor are thick (variable) depending on the lateral length of the oxide film 210; Since the film thickness of 203 is determined by the oxidation conditions in the wet atmosphere, it is difficult to control the dimensions, especially when the gate length of a MOS transistor is miniaturized to the submicron region.
There is a problem in that the transistor characteristics change greatly due to variations in the lateral length of I210.
さらに前述の従来技術ではＣＶＤ法でシリコン酸化膜２
０８を形成する際、ゲート電極２０３゜２０５上の酸化
膜２０６がオーバーハングになっているため、第３図の
ように、この部分の酸化膜のつきまわりが悪（なり、空
洞３１１ができてしま５．その結果、ＭＯ５型トランジ
スタの耐湿性が悪（なるという課題を有する。Furthermore, in the prior art described above, a silicon oxide film 2 is formed using the CVD method.
When forming 08, the oxide film 206 on the gate electrodes 203 and 205 has an overhang, so as shown in FIG. 5. As a result, the MO5 type transistor has a problem of poor moisture resistance.
さらに、前述の従来技術では、ＭＯ８型トランジスタを
形成するとチャンネル上の合計の膜厚はゲート酸化膜２
０２と多結晶シリコン膜２０３と自然酸化膜２０４と多
結晶シリコン膜２０５とシリコン酸化膜２０６の合計の
膜厚となるため段差が大きくなってしまう。その結果、
ゲート電極上にさらに配線層を形成して、その配線層が
ゲート電極を横切ると前記段差のため前記ゲート電極上
の配線層に断線が生じたり、前記ゲート電極上の配線層
を形成するときに、エツチング残りによる配線シヲート
が生じたりする。Furthermore, in the prior art described above, when an MO8 type transistor is formed, the total thickness of the gate oxide film on the channel is 2.
02, the polycrystalline silicon film 203, the natural oxide film 204, the polycrystalline silicon film 205, and the silicon oxide film 206, resulting in a large step difference. the result,
If a wiring layer is further formed on the gate electrode and the wiring layer crosses the gate electrode, the wiring layer on the gate electrode may be disconnected due to the step, or when forming the wiring layer on the gate electrode. , wiring seats may occur due to etching residue.
また、前述の従来技術では、ＬＤＤを形成する際、不純
物のイオン注入を２度行う。工程数が長（なる結果とし
てコスト高及び歩留り低下の原因ともなってしまう。Furthermore, in the conventional technique described above, when forming an LDD, impurity ions are implanted twice. The number of steps is long (which results in high costs and a decrease in yield).
そこで本発明は、このよ５な課題を解決するもので、そ
の目的とするところは、トランジスタの特性のバラツキ
の少ない、しかも耐湿性のよい、ゲート電極上の配線層
に断線、 ’／ ＊ ” ）のない半導体装置を低コス
トかつ高歩留りで提供することにある。Therefore, the present invention is intended to solve these five problems, and its purpose is to provide a transistor with less variation in characteristics and good moisture resistance, and to prevent disconnections in the wiring layer above the gate electrode. ) is provided at low cost and with high yield.
［課頭を解決するための手段］
本発明の半導体装置の製造方法は、第１導電型の半導体
基板上に第１の絶縁膜を形成する工程と前記第１の絶縁
膜上に第１の導電膜を、前記第１の導電膜上に第２の導
電膜を順次形成する工程と前記第１導電膜および前記第
２の導電膜によりＭＯＳ型トランジスタのゲート電極を
形成する工程と、前記第１の絶縁膜上と前記ゲート電極
上及び前記ゲート電極の側壁に第３の導電膜を形成する
工程と、熱アニールを加えることにより、前記ゲート電
極を構成する前記第１の導電膜の画壁に第４の導電膜を
形成する工程とウェットエツチングを行い、前記第３の
導電膜をエツチングする工程と、前記ゲート電極と前記
第４の導電膜をマスクに前記第１導電型の半導体基板に
第２導電型の第１不純物を導入する工程から成ることを
特徴とする。[Means for Solving Problems] A method for manufacturing a semiconductor device of the present invention includes a step of forming a first insulating film on a semiconductor substrate of a first conductivity type, and a step of forming a first insulating film on the first insulating film. a step of sequentially forming a second conductive film on the first conductive film; a step of forming a gate electrode of a MOS transistor from the first conductive film and the second conductive film; A third conductive film is formed on the first insulating film, on the gate electrode, and on the side walls of the gate electrode, and by applying thermal annealing, a partition wall of the first conductive film constituting the gate electrode is formed. forming a fourth conductive film on the semiconductor substrate of the first conductivity type using the gate electrode and the fourth conductive film as a mask; performing wet etching to etch the third conductive film; The method is characterized by comprising a step of introducing a first impurity of a second conductivity type.
また、第２の導電膜が高融点金属膜であることを特徴と
する。Further, the second conductive film is a high melting point metal film.
また、第２の導電膜が高融点金属シリサイド膜であるこ
とを特徴とする。Further, the second conductive film is a high melting point metal silicide film.
［実施例コ
以下、本発明について、実施例に基づき詳細に説明する
。[Examples] Hereinafter, the present invention will be explained in detail based on Examples.
第１図は本発明の実施例を工程順に示す図である。まず
、α図の如く、ボロンを不純物として含むＰ型基板シリ
コンウェハー１０１にＤ ｒ ｙ ０２雰囲気中で１０
００℃酸化を行い、１５０Ｘのシリコン酸化膜１０２を
形成する。ざらｙｂ図の如（ＧＶＤ法でポリシリコン膜
１０３を１０００〜３０００Ｘ形成し、ひき続き０図の
如くスパッタで１０００〜５０００にのモリブデン膜１
０４を形成する。次いで、フォトリングラフィにより、
ポジレジスト層を用いてパターン形成後、異方性エツチ
ングを行い、ｄ図の如くモリブデン膜−ポリシリコンか
ら成るｍｏｓ＋−７ンジスタのゲート電極を形成する。FIG. 1 is a diagram showing an embodiment of the present invention in the order of steps. First, as shown in the α diagram, a P-type substrate silicon wafer 101 containing boron as an impurity was exposed to
Oxidation is performed at 00° C. to form a 150× silicon oxide film 102. As shown in the rough diagram (GVD method is used to form a polysilicon film 103 of 1000 to 3000x, and then as shown in Figure 0, a molybdenum film 1 of 1000 to 5000x is formed by sputtering.
Form 04. Then, by photolithography,
After forming a pattern using a positive resist layer, anisotropic etching is performed to form a gate electrode of a MOS+-7 transistor made of a molybdenum film and polysilicon as shown in Figure d.
次にこの上にＯＶＤ法により６図の如（チタン膜ｊ０５
を１０００〜３０００人形成した後、７３０℃のランプ
アニールを３０秒行うと、前記ゲート電極のポリシリコ
ン膜がチタン膜と反応してｆ図の如（チタンシリサイド
１０６が、ゲート電極のポリシリコン膜の側壁にできる
。その後、アンモニア、過酸化水素、水の混合液で、前
記のように形成したチタン膜をウェットエツチングする
。ここで前工程で形成されたＴ１シリサイド部分はエツ
チングされず、１図の様にゲート電極の側壁にチタンシ
リサイドによるスペーサー１０６が形成される。次に４
図のようにル型不純物、ここではリンを加速電圧８０Ｋ
ｅＶ〜２００ＫｅＶ、ドーズ量Ｉ Ｘｌ ０１１ｉ 〜
８Ｘｉ ｐ１５−２でイオン注入するとポリシリコン膜
、モリブデン膜から成るゲート電極がマスクとなってゲ
ート電極以外のシリコン基板に３＋拡散層１０８が形成
される。この時形成されたチタンシリサイド膜の膜厚よ
りリンの飛程よりわずかに厚（設定してお（とチタンシ
リサイド膜下のシリコン基板には上記のよ５に設定した
ドーズ量より少ないリンが打込まれ、ルー拡散層１０７
が形成される。また、このルー拡散層はゲート電極以外
に形成されたｎ＋拡散層より浅くなる。たとえば、形成
されたチタンシリサイド膜の膜厚を２０００Ｘとするこ
の時、リンの飛程をｚｏｏｏＸよりわずかに浅いよう、
注入エネルギー１００Ｋｅ’Ｖ、ドーズ量を５Ｘ１０”
、’ｉ″２に設定するとゲート電極以外のシリコン基板
には、シリコン基板表面からのリンのピーク位置が０．
１２μｍ、ピーク濃度は３×１０２０のｆ＆“拡散層が
形成される。一方、チタンシリサイド膜下のシリコン基
板には、リンのピーク位置がシリコン基板表面付近でピ
ーク濃度が１Ｘ１０１９のルー拡散層が形成される。Next, as shown in Figure 6 (titanium film j05
After forming 1,000 to 3,000 layers, lamp annealing at 730°C for 30 seconds causes the polysilicon film of the gate electrode to react with the titanium film, as shown in Fig. After that, the titanium film formed as described above is wet-etched using a mixture of ammonia, hydrogen peroxide, and water.The T1 silicide portion formed in the previous step is not etched, as shown in Figure 1. A spacer 106 made of titanium silicide is formed on the side wall of the gate electrode as shown in FIG.
As shown in the figure, the R-type impurity, here phosphorus, is accelerated at a voltage of 80K.
eV ~ 200KeV, dose amount I Xl 011i ~
When ions are implanted using 8Xi p15-2, a 3+ diffusion layer 108 is formed in the silicon substrate other than the gate electrode using the gate electrode made of a polysilicon film and a molybdenum film as a mask. The film thickness of the titanium silicide film formed at this time should be set to be slightly thicker than the range of phosphorus (and the silicon substrate under the titanium silicide film will be bombarded with phosphorus at a dose lower than the dose set in 5 above). roux diffusion layer 107
is formed. Further, this roux diffusion layer is shallower than the n+ diffusion layer formed other than the gate electrode. For example, when the thickness of the formed titanium silicide film is 2000X, the range of phosphorus is set to be slightly shallower than zoooX.
Implant energy 100Ke'V, dose 5X10''
, 'i'' is set to 2, the peak position of phosphorus from the silicon substrate surface is 0.
An f&" diffusion layer with a thickness of 12 μm and a peak concentration of 3 x 1020 is formed. On the other hand, on the silicon substrate under the titanium silicide film, a luu diffusion layer with a peak concentration of 1 x 1019 is formed where the peak position of phosphorus is near the silicon substrate surface. be done.
上述の工程を経てできあがった本発明、半導体装置は、
従来の製造方法に比べて、畷回のイオン注入ぐ、ル１拡
散層及びルー拡散層を形成することができるので工程の
短縮ができる。The present invention and the semiconductor device completed through the above-mentioned steps are as follows:
Compared to conventional manufacturing methods, the process can be shortened because the Ru1 diffusion layer and the Roux diffusion layer can be formed by multiple ion implantations.
また、ポリシリコン、モリブデンシリサイドから成るゲ
ート電極が、５−拡散層とオーパーツツブしているので
、ゲートに電圧を加えるとその電界により、ルー拡散層
の見かけ上の抵抗が下がりかつ、ルー拡散層の横方向の
電界が緩和される。In addition, since the gate electrode made of polysilicon and molybdenum silicide is in direct contact with the 5-diffusion layer, when a voltage is applied to the gate, the electric field reduces the apparent resistance of the leu-diffused layer. The lateral electric field is relaxed.
その結果として、本発明トランジスターのドレイン電流
は増加し、微細化にともなっておこるホットキャリアに
よるコンダクタンスの劣化を避けることができる。As a result, the drain current of the transistor of the present invention increases, and conductance deterioration due to hot carriers that occurs with miniaturization can be avoided.
また、本実施例では、ポリシリコンゲート電極上層の高
融点金属膜として、モリブデンを使用したが、タングス
テン、チタン、グラヂナ、コノ（ルト、ニッケル、タン
タルを使用しても同様な効果を得ることができる。また
、これらの高融点金属シリサイド膜を使用することもで
きる。Further, in this example, molybdenum was used as the high melting point metal film on the polysilicon gate electrode, but the same effect can be obtained by using tungsten, titanium, gradyna, aluminum, nickel, or tantalum. It is also possible to use these high melting point metal silicide films.
また、本実施例では、ル型拡散層形成のためのル型不純
物としてリンを使用したが、ヒ素、アンチモンを使用し
てもよい。Further, in this embodiment, phosphorus was used as the R-type impurity for forming the R-type diffusion layer, but arsenic or antimony may also be used.
［発明の効果コ
本発明によれば、ＭＯ８型トランジスタのドレイン電流
が増加し、しかもトランジスタの微細化に伴っておこる
ホットキャリアによるコンダクタンスの劣化が避けられ
る。従って高速かつ高信頼のＭＯＳ型トランジスタを供
給できる。[Effects of the Invention] According to the present invention, the drain current of an MO8 type transistor is increased, and deterioration of conductance due to hot carriers that occurs as transistors are miniaturized can be avoided. Therefore, a high-speed and highly reliable MOS transistor can be provided.
また本発明によれば、ＭＯＳ型トランジスタの特性を左
右する低濃度不純物層によるソース、ドレイン領域とゲ
ート電極のオーバーラツプの長さを精度よ（加工できる
ので、ＭＯＳ型トランジスタのドレイン電流、コンダク
タンスのバラツキを小さ（できる。Furthermore, according to the present invention, the length of the overlap between the source and drain regions and the gate electrode due to the lightly doped impurity layer, which affects the characteristics of the MOS transistor, can be precisely processed (processed), thereby reducing the variation in the drain current and conductance of the MOS transistor. can be made small (can be done).
また本発明によれば、ＭＯＳ型トランジスタの耐湿性は
悪くならない。Further, according to the present invention, the moisture resistance of the MOS transistor does not deteriorate.
また本発明によれば、ゲート電極上の配線層の断線、シ
ヲートが少な（なる。Further, according to the present invention, there are fewer disconnections and seats in the wiring layer above the gate electrode.
また本発明によれば、ＬＤＤをつ（るのにあたり、？拡
散層、ｒＬ−拡散層のイオン打ち込みが１回でできるの
で、工程数を短か（することができるため、コスト低減
及び歩留り向上をはかることができる。Furthermore, according to the present invention, when building an LDD, the ion implantation of the ?diffusion layer and the rL-diffusion layer can be done in one step, so the number of steps can be shortened, resulting in cost reduction and yield improvement. can be measured.
以上のことから、本発明の半導体装置の製造方法によれ
ば、高速、高品質、高信頼性、高歩留りの半導体装置を
製造できる効果がある。From the above, the method for manufacturing a semiconductor device of the present invention has the advantage of being able to manufacture semiconductor devices at high speed, with high quality, with high reliability, and with high yield.
第１図（α）〜（ｉ）は、本発明の半導体装置の製造方
法の一実施例を示す工程順断面図。
第２図（α）〜（ｃＬ）は、従来例の半導体装置の製造
方法の工程順断面図。第３図は従来例による半導体装置
の断面図。
１０１．２ＣＭ・・・・・・第１導電型シリコン基板１
０２．２０２・・・・・・ゲート酸化膜１０５．２０３
，２０５・・・・・・ポリシリコン膜１０４・・・・・
・モリブデン膜
１０５・・・・・・チタン膜
１０６・・・・・・チタンシリサイド
１０７．２０７・・・・・・シリコン基板と反対導電型
の低濃度不純物層
１０８．２０８・・・・・・シリコン基板と反対導電型
の高濃度不純物層
２［１４，２０６，２０８，２１０・・・・・−シリコ
ン酸化膜
５０１・・・・・・空 洞
煽１１の （α）
元 １１刀 （シ）
第１１Ｄ（ｃ）
晃１１２１（ｄ）
聞１１カ
（已）
妬１１
（ｊ）
爆１）目
（ｄ）
ｌ１図（９）
！ｎ１＋力
（Ｌ）
箋１１Ａ
（ねFIGS. 1(α) to (i) are step-by-step sectional views showing an embodiment of the method for manufacturing a semiconductor device of the present invention. FIGS. 2(α) to (cL) are cross-sectional views in the order of steps of a conventional method for manufacturing a semiconductor device. FIG. 3 is a sectional view of a conventional semiconductor device. 101.2CM...First conductivity type silicon substrate 1
02.202...Gate oxide film 105.203
, 205... Polysilicon film 104...
・Molybdenum film 105...Titanium film 106...Titanium silicide 107.207...Low concentration impurity layer of the opposite conductivity type to the silicon substrate 108.208... High concentration impurity layer 2 [14, 206, 208, 210...-Silicon oxide film 501...Cavity fan 11 (α) Original 11 sword (Si) 11th D (c) Akira 1121 (d) Listen 11 Ka (已) Jealous 11 (j) Baku 1) (d) l1 Figure (9)! n1 + force (L) note 11A (ne
Claims (3)
する工程と、前記第１の絶縁膜上に第１の導電膜を、前
記第１の導電膜上に第２の導電膜を順次形成する工程と
、前記第１導電膜および前記第２の導電膜により、ＭＯ
Ｓ型トランジスタのゲート電極を形成する工程と、前記
第１の絶縁膜上と前記ゲート電極上及び前記ゲート電極
の側壁に第３の導電膜を形成する工程と、熱アニールを
加えることにより、前記ゲート電極を構成する前記第１
の導電膜の側壁に第４の導電膜を形成する工程とウェッ
トエッチングを行い、前記第３の導電膜をエッチングす
る工程と、前記ゲート電極と前記第４の導電膜をマスク
に前記第１導電型の半導体基板に、第２導電型の第１不
純物を注入する工程からなることを特徴とする半導体装
置の製造方法。(1) Forming a first insulating film on a semiconductor substrate of a first conductivity type, forming a first conductive film on the first insulating film, and forming a second conductive film on the first conductive film. The process of sequentially forming films, the first conductive film and the second conductive film,
A step of forming a gate electrode of an S-type transistor, a step of forming a third conductive film on the first insulating film, on the gate electrode, and on the sidewalls of the gate electrode, and by applying thermal annealing. The first layer constituting the gate electrode
a step of forming a fourth conductive film on the sidewall of the conductive film; a step of performing wet etching to etch the third conductive film; and a step of etching the third conductive film using the gate electrode and the fourth conductive film as a mask. 1. A method of manufacturing a semiconductor device, comprising the step of implanting a first impurity of a second conductivity type into a semiconductor substrate of a mold type.
る請求項１記載の半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the second conductive film is made of a high melting point metal.
を特徴とする請求項１記載の半導体装置の製造方法。(3) The method for manufacturing a semiconductor device according to claim 1, wherein the second conductive film is a high melting point metal silicide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3032390A JPH03234028A (en) | 1990-02-09 | 1990-02-09 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3032390A JPH03234028A (en) | 1990-02-09 | 1990-02-09 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03234028A true JPH03234028A (en) | 1991-10-18 |
Family
ID=12300598
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3032390A Pending JPH03234028A (en) | 1990-02-09 | 1990-02-09 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03234028A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07153941A (en) * | 1993-12-01 | 1995-06-16 | Nec Corp | Manufacture of ldd-structure fet |
| US5600153A (en) * | 1994-10-07 | 1997-02-04 | Micron Technology, Inc. | Conductive polysilicon lines and thin film transistors |
| US5804838A (en) * | 1995-05-26 | 1998-09-08 | Micron Technology, Inc. | Thin film transistors |
| US6204521B1 (en) | 1998-08-28 | 2001-03-20 | Micron Technology, Inc. | Thin film transistors |
| KR100399926B1 (en) * | 2000-12-29 | 2003-09-29 | 주식회사 하이닉스반도체 | Method of manufacturing a transistor in a semiconductor device |
-
1990
- 1990-02-09 JP JP3032390A patent/JPH03234028A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07153941A (en) * | 1993-12-01 | 1995-06-16 | Nec Corp | Manufacture of ldd-structure fet |
| US5600153A (en) * | 1994-10-07 | 1997-02-04 | Micron Technology, Inc. | Conductive polysilicon lines and thin film transistors |
| US5658807A (en) * | 1994-10-07 | 1997-08-19 | Micron Technology, Inc. | Methods of forming conductive polysilicon lines and bottom gated thin film transistors |
| US5670794A (en) * | 1994-10-07 | 1997-09-23 | Micron Technology, Inc. | Thin film transistors |
| US5985702A (en) * | 1994-10-07 | 1999-11-16 | Micron Technology, Inc, | Methods of forming conductive polysilicon lines and bottom gated thin film transistors, and conductive polysilicon lines and thin film transistors |
| US5804838A (en) * | 1995-05-26 | 1998-09-08 | Micron Technology, Inc. | Thin film transistors |
| US6204521B1 (en) | 1998-08-28 | 2001-03-20 | Micron Technology, Inc. | Thin film transistors |
| KR100399926B1 (en) * | 2000-12-29 | 2003-09-29 | 주식회사 하이닉스반도체 | Method of manufacturing a transistor in a semiconductor device |
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