JPH03233742A - Data check system - Google Patents

Abstract

PURPOSE:To check the errors at a high speed by reading the data out of a storage part for check of errors via the transfer of an address and the data carried out with the DMA control and at the same time performing the addition of all data via an error check circuit. CONSTITUTION:An internal direct memory access DMA control part 12 of a main control part 1 generates the address of a data storage part 2 and sends the address to the part 2 via a data bus 3. Then the part 12 reads the storage data on a designated address to the bus 3 from the part 2. These read data are all added together via an error check circuit 4, and a CPU 11 of the part 1 fetches the result of this addition to a comparator 13. The comparator 13 compares the received result of addition with the added value of data calculated previously and stored in a check code part of the part 2. Thus the presence or absence of an error is automatically checked for the data set to the part 2 this time. Thus the error of the real data on the part 2 can be checked at a high speed despite the increase of data to be treated.

Description

[Detailed Description of the Invention] [Summary] Regarding a data error check method for checking the validity of data set in a data storage unit for processing by a processor CPU, the data error check method is capable of checking the validity of data set in a data storage unit for processing by a processor CPU. The purpose is a data check method that can check errors in the actual data stored in the storage section at high speed, and directly generates addresses and transfers data to and from the accessed storage section via the bus, without going through the processor CPU. A DM^ control unit and a check circuit that generates an address by the DMA111g unit and adds data read from the storage unit onto the bus are provided, and the processor CPU reads the current addition value of the check circuit, and adds the data read from the storage unit to the bus. The configuration is configured to check whether or not there is an error in the setting data stored in the storage unit by comparing the added value with the added value.

[Industrial application field]

The present invention relates to a data check method for checking the validity of data stored in a storage section when a processor CPU processes the data.

In recent years, dedicated processors built into digital signal transport devices have been handling increased amounts of data and functions due to an increase in the number of systems installed in the devices and demands for a monitoring function for the circuits that serve as a load. Reliability of processed data is required. Therefore, it is necessary to quickly and accurately check the data being handled for errors.

[Conventional technology]

The conventional data check method is IA as shown in Figure 4.
When the CPU IIA of the main microcomputer control unit MPU processes the actual data at addresses 01 to FO of the storage section 2A, a check block is executed to check for errors in the actual data.
The CPU IIA starts the program and sequentially reads the actual data in the storage section 2A, that is, the data at addresses 01 to FO, adds all of the data, and stores the result in the storage section 2A.
Check data already written to address 00 of
In other words, the comparator 13A compares the result of adding up all the data at addresses 0l-FO, and checks the validity of the actual data at that time based on whether they are equal or not.

[Problem to be solved by the invention]

Therefore, if the amount of data handled by CPU IIA increases and the size of storage unit 2A increases, CPIJ IIA will reduce the amount of data in storage unit 2A in proportion to the amount of data in order to check for errors in the actual data. There is a problem in that the time required to calculate the check code, which is read out, added, and written to address 00, increases. An object of the present invention is to provide a data check method that can check errors in actual data in a storage unit 2 that stores processed data at high speed even when the amount of data handled by the CPU 11 of the main microcomputer control unit MPU1 increases.

[Means to solve the problem]

This problem is solved by the main control unit MP[I
without going through the processor CPU 11 in i.

DMA control unit 12 that directly generates an address and transfers data to and from the data storage unit 2 to be accessed via the bus 3
Then, data is read from the storage section 2 onto the bus 3 according to the address generated by the DMA 8111 section, and the comparator 13 compares the added value of the data to check for errors in the data. This problem is solved by the present invention, which includes an error check circuit 4 that adds data read from the storage section 2. In the principle diagram of FIG. 1 showing the basic configuration of the data check method of the present invention, l is the main ms section, and the internal processor CPU
11 to process data in the external storage unit 2,
The storage unit 2 to be accessed by another DMAllil unit 12
A bus 3 that generates addresses and sends and receives data to and from each other.
Then, data is read from the storage section 2 and the data read from the storage section 2 is sent to the error check circuit 4.

2 is read out onto the bus 3 for mutually transmitting and receiving data according to the access destination address generated in the DMA1l@ section 12 inside the main control section 1, and the processor CPU 11
This is an external storage unit that stores data processed by the computer.

3 is DIIAII! inside the main control unit l. This is a bus for mutually transmitting and receiving addresses and data between the first section I2 and the external storage section 2.

4 generates the address of the storage section 2 to be accessed by the oMall1 section 12 inside the main control section 1, and when the data is read from the storage section 2 onto the bus 3, the address is checked for errors in the data. This is an error check circuit that adds the data read from the section 2 and temporarily holds it.

[Effect]

In the present invention, the DMA41711 section 1 inside the main control section 1
2 generates an address of the data storage unit 2 to be accessed, sends it to the storage unit 2 via the bus 3, and from the storage unit to the bus 3
Reads the stored data at the specified address. The read data is all added up in the error check circuit 4. Then, the addition result is sent to the CPU 1 of the main control unit l.
1 is loaded into the comparator 13 and compared with the added value of the data that has already been calculated and stored in the check code section of the storage section 2, and automatically determines whether or not there is an error in the data set in the storage section 2 this time. Check.

Therefore, the DMA control section 12 and the bus 3 of the present invention make it possible to read the data stored in the storage section 2, and the error check circuit 4 adds the data consecutively received from the storage section 2. Since the CPU 11 automatically checks whether there are any errors in the data by comparing the added value of the data currently set in the storage unit 2 with the previous added value, high-speed error checking can be realized.
Since P[J 11 does not perform error checking on the setting data, other processing of the data read from the storage unit 2 can be executed during that time, so the problem is solved.

〔Example〕

FIG. 2 is a block diagram showing the configuration of a data check system according to an embodiment of the present invention, and FIG. 3 is a flowchart for explaining its operation.

In FIG. 2, the main control unit 1 includes a processor CPU ti, a DMA control unit 12, and a system memory 10.
and a comparator 13, and when the CPU 11 reads data from the RAM of the external storage unit 2, the third
As shown in the flowchart in the figure, first, DMA @in section 1
2 cents, and the transfer source start address of the RAM is 1.
1, specifies the total amount of data to be transferred (number of bytes) and the transfer destination address in the system memory 10, and starts transfer by DMA. and the RAl via bus 3.
The above data is transferred to 'l', the data of 1RA1'l is output onto the bus 3, and the output data is input to the S[ll'l CHECK circuit of the error check circuit 4. The StlM CHECK circuit of the error check circuit 4 has an adder 4 and a register 42 therein.
is from address 11 of RAM of storage unit 2 to address FF
Add all the data up to the so-called SUM CHECK C0
DE is calculated and the calculation result is stored in register 42.

The processor CP[J 11 can perform other processing while the error check circuit 4 is calculating the above-mentioned 5UII CHECK C0DH. After the calculation process of the error check circuit 4 is completed, the processor CPLI 11 stores the data at address 10 in the check code section C0DH of the RAM of the storage section 2, that is, when the data was previously set from address 11 to FF in the RAM. The old SUM CHECK C0D that calculates and stores
By comparing SOM CHECK C0DE and the new SOM CHECK C0DE set in the register 42 of the check circuit 4, it is automatically determined and confirmed whether the actual data is normal or not while the actual data is stored in the RAM of the storage unit 2. You can.

〔Effect of the invention〕

As described above, according to the present invention, data is read from a storage unit for error checking using address and data transfer under DMA control, and calculation of addition of all data for error checking is performed. Since this is performed by a hardware circuit, the processing time for error checking can be shortened, and since there is no need for the processor CPU to calculate the error check code, the processor CPU can spend that time on other processing. can get.

[Brief explanation of drawings]

FIG. 1 is a principle diagram showing the basic configuration of the data check method of the present invention, FIG. 2 is a block diagram showing the configuration of the data check method of the embodiment of the present invention, and FIG. 3 is a diagram showing the operation of the embodiment of the present invention. Flowchart for Explanation: FIG. 4 is a block diagram of a conventional data check method. In the figure, 1 is the main control unit MP[I, 11 is the processor CPIJ, 12 is the DMA8116 unit, 13 is the comparator, 2 is the data storage unit, 3 is the bus, 4 is the error check circuit, 41 is the adder, 42 is a register.木范明／）Rising Sun %・t77; Fire stem wood O Saki 1 showing 瀀ri zu 寥 16th moon's actual cup J size j ・／7-sided table composition Ob0tsuku island map

Claims (1)

[Claims] In a method for checking the validity of data set in a data storage unit (2) for processing by a processor CPU (11), access is provided not through the processor CPU but through a bus (3). A DMA control unit (12) directly generates an address and transfers data to and from the previous storage unit (2), and reads data from the storage unit onto the bus using the address generated by the DMA control unit. A check circuit (4) is provided, and the processor CPU reads the current addition value of the check circuit and compares it with the previous addition value to check whether there is an error in the setting data in the storage unit. Data check method.