JPH0323020B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to clock synchronization in demodulation of digital data transmission and the like.

(Prior art and its problems) In conventional demodulation of digital data transmission, an analog continuous signal waveform is sampled at a sample rate f _S and data is demodulated from the sample value sequence {a}. Normally, the sample rate f _S is in a synchronous relationship with the baud rate f _B. Therefore, the sample value series {a}
The value of the open eye point of the received signal can be directly obtained from . The clock control in this case is the sample rate
It is sufficient to control f _S so that it is sampled when the eye of the input signal opens.

However, the sample rate f _S is fixed, and
In the case of non-synchronization with the baud rate, the sample value series {a} at the sample rate f _S does not include the values at the open eye points of all received signals. In other words, in some cases the point at which the eye is open is sampled, and in other cases it is sampled at the point in time when the eye is closed, and it is possible to directly obtain all values at the point at which the eye of the received signal is open from this sample value series. do not have. This problem can be solved by passing the sample value series {a} through an interpolation filter to reproduce a continuous signal waveform, and then resampling it at a sample rate f' _S synchronized with the baud rate. This method uses the same method as the conventional clock control described above after interpolating the sample value series and reproducing the continuous signal waveform. In other words, it is just an interpolation filter added to conventional clock control.

This interpolation filter may be configured with an analog filter or a digital filter. In a configuration using an analog filter,
After converting the digitized signal into an analog sample value series and passing it through an interpolation filter,
It must be converted to digital. In this configuration, analog circuits are mixed into the digital processing, so there are many problems such as inefficiency from a digitalization perspective, difficulty in adjustment, and difficulty in converting to an IC. Also, in digital circuits,
The output must have a waveform close to a continuous signal waveform, and a high-speed digital filter is required, but implementation difficulties arise when the clock rate is high. There is a problem in considering all of these as a structure in which an interpolation filter and a clock control are connected in series.

(Object of the Invention) An object of the present invention is to provide a clock control circuit that uses an interpolation filter and can operate at a low speed regardless of whether the sample rate f _S and baud rate f _B are synchronous or asynchronous.

(Structure of the present invention) The present invention includes (a) a sample circuit that samples an input signal with a transmission period T _B with a sample period T _S ; (b) a first sample circuit that is input to the sample circuit and outputted from a calculation section described below; According to a second delay time amount, a first interpolation value and a second interpolation value obtained by interpolating the input with a delay by the first and second delay time amounts are output from the reference time generation circuit described later. (c) an error detection section that observes and outputs the clock phase error △e based on the first and second interpolated values; (d) an output △ of the timing error detection section; Enter e,
First delay time amount △T and second delay time amount △
(e) inputs the output △e of the _timing error detection section, and calculates the transmission period based on the sampling period T _S ;
a reference time generator that supplies a starting pulse to the rate conversion filter with a period equal to the sum of T _B and ΔT (T _B +ΔT), This is a clock control circuit characterized in that it outputs as an aperture point.

(Detailed explanation of the configuration) The configuration of the present invention uses a rate conversion filter that inputs a sample value series of f _S to an interpolation filter and outputs an interpolated sample value series of f _B. The structure is such that clock control is performed by giving a time delay to the clock.
The principle will be described below.

First, the rate conversion filter used in the present invention will be explained. A normal interpolation filter converts the sample value series sampled at f _S to {a( _o T _S )} (T _S =
1/f _S ) The impulse response of the interpolation filter is g
(t), the output s(t) after interpolation is given by the discrete signal convolution theorem as follows: s(t)= _∞ 〓 ^n=-∞ a( _o T _S ) g(t- _o T _S ) …( 1) To obtain the value s(t) at an arbitrary time t from the sample value series {a( _o T _S )} using equation (1), it is sufficient to give a time delay of t to the filter g.

If we take this arbitrary time value as a value for each baud rate, equation (1) becomes s ( _n T _B ) = _∞ 〓 ^n=-∞ a ( _o T _S ) g ( _n T _B − _o T _S ) …(2 ) However, T _B = 1/f _B. Equation (2) is the sample value series of T _S {a( _o T _S )}
This is an expression representing a rate conversion filter that outputs the sample value sequence {s( _n T _B )} of T _B from . In equation (2), if _n T _B in filter g is expressed using T _S , _n T _B = _k T _S + β(m)...(3) β(m) < T _S. This β is the interpolated output value s( _n T _B ) and s( _n
The sample value a( _k T _S ) closest to T _B ) ( _k T _S < _n T _B )
It represents the time difference between. Therefore, equation (2) becomes s( _n T _B )= _∞ 〓 ^n=-∞ a( _o T _S )g{β(m) + (k−n)T _S } (4) where k If −n=i, equation (4) can be expanded as follows: s( _n T _B )= _∞ 〓 ^ki=-∞ a{(ki)T _S }g{β(m) + _i T _S } = _∞ 〓 ^i=-∞ a{(k−i)T _S }g{β(m)+ _i T _S } …(5) In equation (5), the absolute value of i |i| When it becomes large, |g( _i T _S )| becomes a very small value and can be ignored, so it can be approximated by a sufficient finite length -N/2 to i to N/2. Therefore, equation (5) is s( _n T _B )= _N/2 〓 ^i=-N/2 a{(k−i)T _S }g{β(m) + _i T _S } …(6) { FIG. 5 shows the relationship between a}, {S}, and β. As can be seen from Figure 5, in order to output the sample value interpolated by f _B (e.g. s ₂ ), we need to change the time around the previous sample value closest to that point (a ₂ for s ₂ ). The sample value interpolated at f _B can be obtained by interpolating with a filter with a delay (β ⁽²⁾ for s ₂ , a ₂ ).

However, this is the case where there is no timing shift factor such as initial phase. For example, when there is an initial phase shift φ as shown in FIG. 6, the interpolated sample value sequence {s} and time difference β' are As shown in the figure, there is a difference between when there is no initial phase shift and when there is no initial phase shift. Such a sample value sequence {s'} cannot sufficiently reproduce the transmitted information.

Clock control is used to control timing deviations such as the initial phase, and in the present invention, the timing errors are fed back to the time delay characteristics of the filter. Timing error detection includes timing error detection using double sampling. Timing error detection requires not only the open eye point of the input signal as shown in FIG. 5, but also phase error information.
The time from the eye opening point to the phase error information point is
If T _B /2 (midpoint between Eye and Eye), substitute into equation (6) and get s{(1/2+m)T _S }= _N/2 〓 〓 〓 ^i=-N/2 a{(k-i )T _S }g(β(m)+ _i T _S +T _B /2
}...The phase error information is determined by (7).

Figure 7a is a binary digital signal of +1, -1,
Alternatively, it is a diagram showing an eye pattern of a real part or an imaginary part of a demodulated signal of a quadrature phase modulated wave. Figure b shows the sample timing.
The time per clock period (T seconds) indicated by the arrow corresponds to the widest eye opening time of the eye pattern. In the following, this timing will be referred to as signal detection timing. c in the same figure is the previous b
This shows the timing phase shifted by x phase (180°). Hereinafter, this timing will be referred to as clock phase detection timing. At this timing, the 7th
When the waveform in Figure a is sampled, it takes three types of values: a value of ±1 when the transmission code does not change before and after that, and a value near zero when it changes conversely. The waveform in Fig. 7a depends on the roll-off rate and bit pattern of the transmitted pulse, but it is approximately the 8th waveform.
Even if it is simplified as shown in Figure a, there is no problem on average. First, let us consider signal changes as shown by the thick line in FIG. 8a. This change means that the transmission code is +1,
This is a case where -1, +1, -1 are alternately repeated and transmitted. Figures b and c show the signal detection timing and clock phase detection timing, respectively. If the former is delayed by T _e seconds, the eye width of the eye pattern will narrow from W ₀ to W ₁ . Next, let us consider the magnitude of the signal sampled at two successive clock phase detection timings. When T _e =0 in Figure 8c,
The two sample values are 1000 and 1001, which are the same value. On the other hand, if T _e ≠ 0 and T _e < 0 (i.e., sample delay), the two sample values are 1002.
1003, and the difference between the two is non-zero. Also, T _e ＞
When it is 0, it becomes 1004 and 1005, and the difference between them is also non-zero, and the polarity is opposite to that when T _e <0. By utilizing this fact, first, at the signal detection timing, a signal transition (-
It can be seen that the polarity and magnitude of T _e can be estimated by extracting the values (1, +1, -1) and finding the difference between the sample values at the clock phase detection timings before and after that time. Here again, if the signal transition is a thick line
If the thin line 2001 is used instead of 2000, (the signal transition is +1, -1, +1), the polarity of the difference between the sample values before and after the clock phase detection timing with respect to T _e will be opposite to that in the previous example. In practice, the signal transition (-1,
+1, -1) and (+1, -1, +1) can provide more phase difference information as a clock phase difference detector, so it is better to use both. (Reference 1: Patent Application No. 58-016406 ``Clock Phase Control Circuit'').

With this eye open point and phase error information,
A time delay amount r·T _e obtained by multiplying the timing error amount (excess/deficiency) T _e detected by the timing error detection section by a coefficient r is fed back to the filter.

This time delay amount is the timing error time r・
Give a time delay to the output time _n T _B by T _e . Since this is the entire process up to _n T _B , equation (3) is: _n T _B + _n-1 〓 ^j=0 r・T _e ^(j) = kT _S + β ^(m) …(8) β ^{( m)} It can be rewritten as < _TS . As can be seen from equation (8), the timing error is absorbed by k and β ^(m) . Rewriting equations (6) and (7) using equation (8), we get becomes. By the values of these two equations (9), the timing error is made as shown in FIGS. 7 and 8, and the next output interpolation point is controlled. When there is an initial phase φ as shown in Fig. 6, the sample value sequence is {s( _n T _B +φ)}, and in the steady state {s( _n T _B )} where the initial phase is absorbed, − _n-1 〓 ^{j= 0} r・T _e ^(j) φ …(10)

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 is a sample cycle operating at f _S (=1/T _S ). In the figure, reference numeral 2 denotes a rate conversion filter that performs the calculation of equation (9) from the sample value series {a} of the sample circuit for each activation pulse output from the reference time generation circuit 5. 3 in the figure is based on the two values output from the rate conversion filter 2,
As explained using FIG. 8, 4 is a timing error detection section that outputs ΔT (=T _e ), and 4 in the figure inputs ΔT, and ΔT + ΔT + ΔT + ΔT plus T _B /2 hours.
This is an arithmetic unit that outputs T _B /2. 5 in the figure is ΔT
and set the time interval for producing the next interpolated output.
This is a reference time generation circuit that controls T _B +ΔT.

FIG. 2 is a block diagram showing the invention shown in FIG. 1 in more detail. The signal a(t) is sampled by a sample circuit operating at _fS of 10 in the figure, and the sample value series {a} is stored in a first-in-first-out memory (hereinafter referred to as FIFO) 20. In the figure, numeral 30 denotes an acyclic filter, which is composed of a shift register 31 having an N data length, a product-sum circuit 32, and a ROM 33 that stores each tap coefficient.
In the figure, 40 is a timing error detection unit that outputs a timing error of data from the interpolated sample value series output from the acyclic filter 30;
In the figure, 50 is the time delay amount of the filter for inputting the timing error and operating the acyclic filter 30 as a rate conversion filter, and the shift register 3
This is an arithmetic unit that estimates data input to 1 and calculates the time between symbols. In the figure, 60 is a reference time generator, and a clock generator 61 generates a clock of _fA .
and a counter 62 that determines the time between symbols.
and a frequency divider 63 that converts f _A to f _S . In the figure, 70 indicates the output of the acyclic filter 30.
A latch circuit that latches only the open value of the eye and outputs it to the outside. Reference numeral 71 in the figure is a switch that operates the system at calculated symbol intervals.

Below, in Figure 2, f _S = 45kHz, f _B = 32kHz
(symbol rate) as an example. The signal a(t) is sampled at a sample rate of 45 kHz, resulting in a sample value sequence {a}, which is sequentially stored in the FIFO. With FIFO20,
The input and output are asynchronous, and after the FIFO, the symbol rate of _fB is used as one cycle. At the same time as the latch 70 outputs the open point {s} of the eye, the switch 71 closes and the shift register receives L,
The initial address T〓 is output from the calculation unit 50 to the ROM. 31 is a shift register with data length N = 14 (capable of outputting each value), which shifts L estimated data number values of {a} sampled between symbols, and transfers L data numbers from FIFO. Enter {a}.
Each value in the shift register is multiplied by each tap coefficient value stored in the ROM addressed at the initial address T and the interval T _S , and the sum is output as an interpolated value. The ROM contains the impulse response of the interpolation filter at the sample rate f and the symbol _rate .
Common multiple of f _B f _A = 2880kHz (=k・f _B・f _S ; k=2)
A sample value series {g} sampled in is stored. From 60 in the figure, the minimum control time of this system is
T _A = 1/f _A , and this is one count,
A time is set, and for T _B , 90 counts;
64 counts against _T.S. Timing error detection is performed at 40 based on the interpolation output obtained at 30 in the figure, which is equivalent to the value obtained by sampling the waveform at a in FIG. 7 at b and c. Note that the configuration of this timing error detector is described in the above-mentioned document 1. For example, assuming binary transmission, using the fact that the zero-crossing point of the waveform due to the transmission code transition is located between the eyes on average, we can use the fact that 1/ Timing error detection can be performed by determining whether the value of a point _2TB apart, that is, a point 45 counts apart, is before or after the actual zero cross point. Among the values interpolated by double sampling, the point Tβ is set as the point where the eye opens and the latch70
Latch with . If the timing error detection unit increases or decreases the count by +1 or -1 for timing lead or lag, the calculation unit 50 will calculate the following: Since the inter-symbol time N _C is T _B + _r T _e , N _C = 90±1or90. Also, the number of {a} sampled during N _C is estimated as follows. Using Figure 5 as an example,
When calculating the estimated number of samples L ⁽²⁾ , L ⁽²⁾ = int {T _B + β ⁽¹⁾ /T _S } intx is calculated as an integer value of x. In general, considering timing control (T _B = T _B + _r T _e ), the estimated number of samples
L ^(m) can be obtained by L ^(m) = int {T _B + _r T _e ^(m-1) + β ^(m-1) /T _S } (11). The time delay amount Tβ ^(m) (indicated by β ^(m) in the formula) is calculated as β ⁽²⁾ using Fig. 5 as an example.
Determining β ⁽²⁾ = T _B + β ⁽¹⁾ −L ₂・T _S , and like L, considering it as digital control including timing control, T ^(m) 〓=90+Tβ ^(m-1) −64・L ^(m) + _r T _e { ⁰ ₄₅ (12). Clock control is performed by performing the above arithmetic processing for each symbol.

FIG. 3 shows the internal operation for outputting the next interpolated value in this embodiment. The figure shows the operation of each part when there is no timing error ( _r T _e =0). For the current interpolated value output, the sample value system {a} from a ₁ to _{a 14} is stored in the shift register, and the addresses for selecting tap coefficients are at intervals of 43 to 64. From this current interpolated value
The next interpolated value output after T _B (because _r T _e = 0) is (11),
From equation (12), estimated number of samples L = 2, time delay amount
It is calculated that Tβ=5. Therefore, a ₁₅ and a ₁₆ are newly input to the shift register, and the entire data is shifted by two data. The tap coefficients for each shift register value range from 5 to 64. In this case, since there is no timing error, the interval between both interpolated values is T _B.
Therefore, for the same sample value, the tap coefficient is
This is the tap coefficient shifted by T _B. For example, a ₁₂
The tap coefficient has moved from 43 to 133. This difference is 90
Since it is a tap and the tap coefficient is sampled at 2880kHz, 90 taps is 90 taps in time.
It turns out that T _B. FIG. 4 shows the operation of each part when there is a timing error ( _r T _e =+1) in the same way as in FIG. 3. In this case, the interval between the current interpolation value and the next interpolation value is T _B + _r T _e . Similarly to Figure 3, when looking at a ₁₂ , the tap coefficient is from 43 to 134.
is moving to. This difference is 91, which is expressed in time.
Equal to T _B + _r T _e .

(Effects of the Invention) According to the present invention, the value at the time when the signal eye opens can be interpolated and output not only when the sample rate and baud rate are asynchronous, but also when the sample rate is fixed. This is possible, and the hardware configuration is also achievable because there is no high-speed calculation and by using ROM, it becomes a low-speed calculation system.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a first embodiment of the present invention, FIG. 2 is a diagram showing FIG. 1 in more detail, FIGS. 3 and 4 are diagrams showing an example of the operation of the embodiment, FIG. FIG. 6 is a diagram showing the operating state of the rate conversion filter, FIG.
FIG. 8 is a diagram for explaining the operation of the timing error detection section. In the figure, 1...sample circuit, 2...rate conversion filter, 3...timing error detection section, 4...
Arithmetic unit, 5...Reference time generation circuit.

Claims (1)

[Claims] 1 (a) An input signal with a transmission period T _B is sampled at a sampling period.
A sample circuit that samples at T _S , (b) inputs the output of the sample circuit, and converts the input to the first and second time amounts according to the first and second delay time amounts output from the calculation section described later. a rate conversion filter circuit that outputs a first interpolated value and a second interpolated value delayed by the amount of delay for each starting pulse output from the reference time generating circuit described later; (c) the first and second interpolated values; an error detection section that observes and outputs the clock phase error △e based on the interpolated value of (d) inputs the output △e of the timing error detection section;
First delay time amount △T and second delay time amount △
(e) inputs the output △e of the _timing error detection section, and calculates the transmission period based on the sampling period T _S ;
a reference time generating section that supplies a starting pulse to the rate conversion filter with a period equal to the sum of T _B and ΔT (T _B +ΔT), and converts the first interpolated value into the input signal eye A clock control circuit characterized by outputting as an opening point of a pattern.