TW423215B - Interpolation filter implemented by the memory - Google Patents
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4 2 3 21 5 ^ 五、發明說明α) 本發明係有關於一種數位同步技術’特別是利用唯讀 ‘ 記憶體(read only memory,ROM)實現之内插式濾波器 (interpolation filter) ° 在一般數位通訊系統中,數位資料是载於類比型式的 訊咸上進行傳輸’此時數位貧料可以利用像是p S K (p h a s e shift key)或QAM(quadrant amplitude modulation)等等 方式所調變的資料,再藉由像是PAM (pulse amp 1 itude modulation)等等調變方式調變於連續波(continuous wave)上。因此在解調數位資料之前’接收端必須利用類 比轉數位(A/D)的動作,才可以進一步處理真正的數位資 ^ 料’此一類比轉數位動作稱為取樣(samp 1 i ng)。 ” 常見的取樣方式可以分為同步取樣和非同步取樣兩 種’其中同步與非同步是指進行取樣的時脈信號是否與輸 入數位資料的符號速率(Symb〇l rate) —致。 同步取樣是利用與輪入數位資料之符號速率一致的取 樣時鐘(samp 1 ing clock)進行取樣,一般是利用反饋式 (feedback)控制方式來達到兩者的一致性。第1圖表示習 知技術中利用反饋式同步取樣之接收系統的方塊示意圖。 其中,1表示類比處理部分,用來處理載有數位資料的類 j 比訊號。2為取樣器,其根據取樣時脈信號11進行取樣。3 y 表示數位處理部分,對於取樣值進行數位解調的動作,以 產生所需要的數位資料。4表示時脈產生器,用以產生取 樣所需要的取樣時脈信號i丨。在反饋式同步取樣系統中, 時脈產生器4所需要的時序控制信號(timing controi4 2 3 21 5 ^ V. Description of the invention α) The present invention relates to an interpolation filter implemented by a digital synchronization technology 'especially using read only memory (ROM) ° In general digital communication systems, digital data is transmitted on analog signals. At this time, the digital lean material can be modulated using methods such as p SK (phase shift key) or QAM (quadrant amplitude modulation). The data is then modulated on a continuous wave by modulation methods such as PAM (pulse amp 1 amplitude modulation). Therefore, before demodulating digital data, the receiver must use the analog-to-digital (A / D) action to further process the real digital data. This analog-to-digital action is called sampling (samp 1 i ng). Common sampling methods can be divided into two types: synchronous sampling and asynchronous sampling. Among them, synchronous and asynchronous means whether the sampling clock signal is consistent with the symbol rate of the input digital data. Synchronous sampling is Sampling using a sampling clock (samp 1 ing clock) that is consistent with the symbol rate of the round-in digital data, generally uses feedback control to achieve consistency between the two. Figure 1 shows the use of feedback in the conventional technology. A block diagram of a receiving system with synchronous sampling. Among them, 1 is the analog processing part, which is used to process the analog signal with digital data. 2 is the sampler, which samples according to the sampling clock signal 11. 3 y is the digital The processing part performs digital demodulation on the sampled value to generate the required digital data. 4 represents the clock generator, which is used to generate the sampling clock signal i 丨 required for sampling. In the feedback-type synchronous sampling system, Timing control signals required by the clock generator 4 (timing controi
第4頁 4 2 3 215 Mt 五、發明說明(2) signa 1)10是由數位處理部分3根攄解調數位資料所產生。 一般在反饋式同步取樣系統中,時脈產生器4原本所產生 的時脈信號便非常接近於數位資料的符號速率,反饋的機 制主要是使同步更精準。不過在某些情況下,取樣時脈信 號11和數位信號的符號速率不容易達到同步。例如接收器 所接收者包含數種不同速率/頻道的信號,但是系統中沒 有足夠數量和符合規格的振盪器,此時就很難讓兩者同 步。即使透過反饋方式進行控制,效果也不明顯。Page 4 4 2 3 215 Mt V. Description of the invention (2) signa 1) 10 is generated by demodulating digital data from 3 digital processing units. Generally, in a feedback synchronous sampling system, the clock signal originally generated by the clock generator 4 is very close to the symbol rate of the digital data. The feedback mechanism is mainly to make the synchronization more accurate. However, in some cases, it is not easy to synchronize the symbol rates of the sampling clock signal 11 and the digital signal. For example, the receiver receiver contains several signals with different rates / channels, but there is not enough number of oscillators in the system that meet the specifications. At this time, it is difficult to synchronize the two. Even if controlled by feedback, the effect is not obvious.
非同步取樣技術則可以克服上述無法透過同步取樣方 式讓取樣時脈和符號速率一致的問題。第2圖表示習知技 術中利用非同步取樣的接收系統的方塊示意圖。在非同步 取樣系統中’時脈產生器4所產生的取樣時脈信號11具有 一定的頻率。由於未經由同步過程,所以取樣時脈信號j j 的頻率通常不會與輸入數位資料的符號速率—致。由取樣 器2所輸出的取樣"is號(sampled signal),則是利用數位 處理部分3進行數位信號處理,進行速率轉換 conversion),產生與原數位信號符號速率一致的取樣 值。數位處理部分3通常是利用内插式濾波器Asynchronous sampling technology can overcome the above-mentioned problem that the sampling clock and symbol rate cannot be made consistent through the synchronous sampling method. Fig. 2 shows a block diagram of a receiving system using asynchronous sampling in the prior art. In the asynchronous sampling system, the sampling clock signal 11 generated by the 'clock generator 4 has a certain frequency. Because there is no synchronization process, the frequency of the sampling clock signal j j usually does not match the symbol rate of the input digital data. The sampled signal "is" (sampled signal) output by the sampler 2 uses the digital processing section 3 to perform digital signal processing and perform rate conversion (conversion) to generate a sample value that is consistent with the original digital signal symbol rate. The digital processing section 3 usually uses an interpolation filter
(interpolation filter)内插出符合同步條件的取樣信 號,使其具有近乎同步取樣的結果。以下則簡要說明一般 内插式濾波器之工作原理。 假設由取樣器2所產生之取樣信號為x(mxTs),其中Ts 是取樣器2的固定取樣週期,而m = 〇 5l,2,…。此取樣信 號通過内插式濾波器後產生的輪出信號可以表示為此取樣(interpolation filter) Interpolates a sampling signal that meets the synchronization conditions, so that it has a nearly synchronous sampling result. The following briefly describes the working principle of general interpolation filters. Assume that the sampling signal generated by the sampler 2 is x (mxTs), where Ts is the fixed sampling period of the sampler 2, and m = 0 5l, 2, ... The round-out signal generated after this sampling signal passes through the interpolation filter can be expressed as this sampling
第5頁 423215 五、發明說明(3) 信號和内插式濾波器之脈衝響應(impulse resP〇nse)的迴 旋積分值(c ο n v ο 1 u t i ο η)。假設内插式爐波器的脈衝響應 為h(u),u表示連續時間,則輸出信號y(t)可以表示為: y(t〉= Σ x(m . Ts〉 h(t - m · Ts) ⑴ 若Ti表示與符號速率同步的取樣週期’公式(1)可以轉換 為: y(n -^)=^ 1 Ts) h(n ^ - m · Ts) (2) mPage 5 423215 V. Description of the invention (3) The cyclotron integral value (c ο n v ο 1 u t i ο η) of the impulse response (impulse responsion) of the signal and interpolation filter. Assuming that the impulse response of the interpolated furnace wave device is h (u), where u represents continuous time, the output signal y (t) can be expressed as: y (t> = Σ x (m. Ts> h (t-m · Ts) ⑴ If Ti represents the sampling period synchronized with the symbol rate, the formula (1) can be transformed into: y (n-^) = ^ 1 Ts) h (n ^-m · Ts) (2) m
根據公式(2)可以發現,此内插式濾波器的作用即是將固 定取樣的輸入取樣信號(以x(mxTs)表示)’轉換為與輸入 數位資料之符號速率同步的輸出取樣信號(aWnXTi)表 示)。在實際應用公式(2)時’會將其中有關於脈衝響應的 部分進一步加以整理: yin · = Σ x(m _ Ts>· h[ (i + uj _ Ts] (3 > 其中 i = int [n · / Ts] - m un = n ^ / Ts -mn = int [n ^ / ts] n=0,1,2,… 在上述的推導過程中可以得知,只要η X L無法被Ts所 整除,則Un就會是小數。輸出取樣信號y (η X )可以整理 為y[(un + nin)xTs],這表示輸出取樣信號相當於是由輸入 取樣信號(以Ts為取樣周期)移位部分取樣周期(un為小數)According to formula (2), it can be found that the function of this interpolation filter is to convert a fixed sampling input sampling signal (represented by x (mxTs)) 'into an output sampling signal (aWnXTi) that is synchronized with the symbol rate of the input digital data. ) Means). In the practical application of formula (2), 'the part about the impulse response will be further arranged: yin · = Σ x (m _ Ts > · h [(i + uj _ Ts] (3 > where i = int [n · / Ts]-m un = n ^ / Ts -mn = int [n ^ / ts] n = 0,1,2, ... In the above derivation process, we can know that as long as η XL cannot be detected by Ts Dividing, then Un will be a decimal. The output sampling signal y (η X) can be sorted into y [(un + nin) xTs], which means that the output sampling signal is equivalent to being shifted by the input sampling signal (Ts is the sampling period). Partial sampling period (un is decimal)
第6頁 4 23 21 5 五、發明說明(4) 或内插而產生。第3圖表示輪入取樣信號(取樣周期為Ts) 和輸出取樣信號(取樣周期為)的時間關係的時序圖,亦 顯示出此一關係。 其中un在上述推導中是报重要的參數,其決定内插的 結果。在一般系統中’ un是由反饋機制得到,此一部分可 以參考Floyd M· Gardner, "Interpolation in DigitalPage 6 4 23 21 5 V. Invention description (4) or interpolation. Figure 3 shows the timing diagram of the time relationship between the round-robin sampling signal (sampling cycle is Ts) and the output sampling signal (sampling cycle is). This relationship is also shown. Among them, un is an important parameter in the above derivation, which determines the result of interpolation. In the general system, ’un is obtained by the feedback mechanism. This part can refer to Floyd M. Gardner, " Interpolation in Digital
Modems-Part I: Fundamentals, IEEE Transactions on Communications, vol, 41, No. 3, Mar. 1993, PP· 5(U-5 07。在前述說明中,參數Un可能是任意準確度的 小數’但是以數位電路來實現時,必須進行量化,亦即將 浮點數轉換為固定位數的小數(floating p〇int to fixed point)之處理。此量化處理可以將一個原取樣周期%分割Modems-Part I: Fundamentals, IEEE Transactions on Communications, vol, 41, No. 3, Mar. 1993, PP · 5 (U-5 07. In the foregoing description, the parameter Un may be a decimal of arbitrary accuracy 'but the When the digital circuit is implemented, it must be quantized, that is, the process of converting floating point numbers to a fixed number of decimals (floating p0int to fixed point). This quantization process can divide a% of the original sampling period.
為N等份’每一等份則對應於〇〜之一整數值。換言 之,如果將取樣周期Ts視為3 6 0。,則代表内插訊息的參 數1^則表示在取樣周期中的相位(phase)訊息,亦即\ XFor N equal parts', each equal number corresponds to an integer value of 0 ~. In other words, if the sampling period Ts is regarded as 3 6 0. , The parameter representing the interpolation message 1 ^ represents the phase information in the sampling period, that is, \ X
Ts 的解析度(resolution)為360。/N。 目前内插式濾波器主要以兩種方式實現,兩者間主要 的差別在於係數的產生方式不同,至於其他的架構則是相 ^的,如利用乘法器和加法器實現迴旋積分以及利用暫存 器(regUter)來存放待處理的輸入取樣信號和濾波器的脈,:) 衝響應係數。β第—種方式是利用多項式(polynomial)來合 成接近濾波器的脈衝響應波型,例如美國專利 5, 878, 088。第二種方式則是直接將所需要的波型參數 存於特疋的。己隐體中,例如直接燒錄於唯讀記憶體(Κ⑽)The resolution of Ts is 360. / N. At present, interpolation filters are mainly implemented in two ways. The main difference between the two is that the coefficients are generated in different ways. As for the other architectures, they are related, such as the use of multipliers and adders to implement cyclotron integration and the use of temporary storage. Register (regUter) to store the input sample signal and filter pulses to be processed, :) the impulse response coefficient. The first method of β is to use a polynomial to synthesize the impulse response waveform of the proximity filter, for example, US Patent 5,878,088. The second method is to directly store the required wave shape parameters in special mode. In the hidden body, for example, directly burned into the read-only memory (Κ⑽)
第7頁 4 23 215 五、發明說明(5) — 或是在開機時載入隨機存取記憶體(RAM )内,再利用記情 體的適當位址訊息來取出在計算迴旋積分時所需要的係數 參數。第4圖表示習知技術中利用唯讀記憶體實現内插式 — 遽波器之方塊示意圖,其中是以8節點(taps)濾波器為工 例。圖中’201a〜201h表示輸入用暫存器,用以暫存輸入 取樣信號。2 03a〜2 0 3h表示係數用暫存器,用來暫存濾波 器之脈衝響應係數。205a〜205h表示乘法器,用以計算對 應之輸入取樣信號和濾波器係數的乘積。2 〇 7表示唯讀記 憶體’根據一定位址訊息,提供對應的係數至各係數用暫 存器2 0 3 a〜2 0 3 h。2 0 9表示加法器’用以將各乘法器 (205a~205h)的乘積結果相加’產生對應的輸出取樣信 f 號。上述分項的乘法和加法運算,對應著輸入取樣信號和 濾波器係數的迴旋積分,藉以計算出輸出取樣信號。例如 美國專利5793818 ' 5309484 ' 5500874、5612975、 550478 5、5878088中均利用類似於第4圖的方式實現内插 式滤波器。這些内插式濾波器主要是將所有係數直接儲存 於唯讀記憶體中,在計算對應的迴旋積分時,則透過位址 索引出對應的係數值進行計算。 另一方面,當數位資料是利用二維調變(quadrature modulation)調變所產生,例如qaM或是QPSK,則在處理上 Y 會比較複雜。由於二維調變數位資料的信號是存在於二維 向量中’亦即包括I通道成分和q通道成分,因此最早的處 理系統是採用兩套取樣器來分別處理I通道成分和q通道成 分。但是因為兩套取樣器在製作成本上較高,因此目前實Page 7 4 23 215 V. Description of the invention (5) — Or load it into random access memory (RAM) at boot time, and then use the appropriate address information of the memory to take out the information needed to calculate the round integral. Coefficient parameter. Fig. 4 shows a block diagram of the conventional implementation of an interpolator-wavelength filter using read-only memory, in which an 8-node (taps) filter is used as an example. In the figure, '201a to 201h' indicate input registers, which are used to temporarily store input sampling signals. 2 03a ~ 2 0 3h indicates the coefficient register, which is used to temporarily store the impulse response coefficient of the filter. 205a ~ 205h represent multipliers, which are used to calculate the product of the corresponding input sampling signal and filter coefficients. 2 07 means read-only memory. According to a location address message, a corresponding coefficient is provided to each coefficient register 2 0 3 a to 2 0 3 h. 2 0 9 indicates that the adder 'is used to add the product results of the multipliers (205a to 205h)' to generate a corresponding output sampling signal f. The multiplication and addition operations of the above sub-items correspond to the round-robin integration of the input sampling signal and the filter coefficients, thereby calculating the output sampling signal. For example, U.S. Patent Nos. 5,793,818 ', 5,309,484, 5,500,874, 5,612,975, 550,478, 5,587,088,88 all implement interpolation filters in a manner similar to Figure 4. These interpolation filters mainly store all coefficients directly in the read-only memory. When calculating the corresponding convolution integrals, the corresponding coefficient values are indexed through the address for calculation. On the other hand, when digital data is generated using two-dimensional modulation (quadrature modulation), such as qaM or QPSK, Y is more complicated to process. Since the signal of the two-dimensional modulated digital data exists in a two-dimensional vector, that is, it includes the I channel component and the q channel component, the earliest processing system used two sets of samplers to process the I channel component and the q channel component, respectively. However, because the two sets of samplers are relatively expensive to produce,
第8頁 423215 五、發明說明(6) 際作法大多只採用一套取樣器進行取樣,再利用信號選擇 器從取樣6號令選擇出屬於I通道成分或是屬於Q通道成分 的取樣值部分。 第5圖表示在使用單一取樣器和信號選擇器來處理二 維調變數位資料時的信號時序圖。圖中A、B、c、D、E、Page 8 423215 V. Description of the invention (6) Most of the practice uses only a set of samplers for sampling, and then uses the signal selector to select the sampling value part that belongs to the I channel component or the Q channel component from the sampling order 6. Figure 5 shows the signal timing diagram when using a single sampler and signal selector to process 2D modulated digital data. A, B, c, D, E,
F、G、Η表示甴取樣器進行取樣所得到的連續取樣點(取樣 周期為TSAM) ’其中取樣點a、c、Ε、G分配至I通道,取樣 點B、D、F、Η則分配至q通道。此時,I通道和q通道上的 取樣點疋父錯而非對準於相同的時間點上。在一般實際應 用上’會將I通道和Q通道的取樣點在時間上對齊以便後續 的處理°第6圖表示習知技術中用以調整未對準I通道和q 通道取樣點的系統方塊示意圖。其中I通道輸入取樣信號 和Q通道輸入取樣信號類似第5圖所示信號的情況,各通道 内取樣點間隔均為2Tsam。在!通道中的處理單元包括延遲 器21、延遲器22和内插式濾波器2〇。延遲器21和22的延遲 時間均f TSAM,亦即對每個取樣點延遲I,内插式濾波 器20則是用來產生與符號速率一致的1通道輸出取樣信 號。在Q通道中的處理單元包括移相濾波器(phase shift f 11 ter)31和内插式濾波器3〇。移相濾波器31是用來讓Q通 道上的取樣點產生Tsam的相位移,這相當於在兩相鄰取樣 點間的中點。例如在取樣點B 之中點,可以利用兩取樣 點上的取樣值平均數來模擬,若需更精確的模擬則可以採 用更複雜的濾波器。内插式濾波器3〇則是用來產生與符號 速率一致的Q通道輸出取樣信號。因此,分配至[通道和QF, G, and Η indicate the continuous sampling points obtained by the 甴 sampler (sampling cycle is TSAM) 'where sampling points a, c, Ε, and G are assigned to the I channel, and sampling points B, D, F, and Η are assigned To the q channel. In this case, the sampling points on the I and q channels are not aligned at the same time point. In general practical applications, the sampling points of the I and Q channels will be aligned in time for subsequent processing. Figure 6 shows a block diagram of a system used to adjust the misaligned sampling points of the I and Q channels in the conventional technology. . The input sampling signal of I channel and the input sampling signal of Q channel are similar to the signal shown in Figure 5. The sampling point interval in each channel is 2Tsam. in! The processing unit in the channel includes a delayer 21, a delayer 22, and an interpolation filter 20. The delay times of the delayers 21 and 22 are both f TSAM, that is, each sample point is delayed by I, and the interpolation filter 20 is used to generate a 1-channel output sampling signal consistent with the symbol rate. The processing unit in the Q channel includes a phase shift filter 31 and an interpolation filter 30. The phase shift filter 31 is used to cause the sampling point on the Q channel to generate a phase shift of Tsam, which is equivalent to the midpoint between two adjacent sampling points. For example, at the midpoint of sampling point B, you can use the average of the sampling values at the two sampling points to simulate. If you need more accurate simulation, you can use more complex filters. The interpolation filter 30 is used to generate a Q-channel output sampling signal consistent with the symbol rate. So assign to [channel and Q
第9頁 42 3 21 5 五、發明說明(7) 通道的取樣點在時間上可以取得一致。 在習知非同步取樣的處理中尚 分,例如,習知利用唯嘈t p 了以加以改進的部 將對應於各相位量c亦即u χ τ 1 M y所有係數的方式,係 !、处(ψϋη X fs)的脈衡继 於唯讀記憶體中,並沒有44 Μ 胃應係數整個儲存 調變的數位資料而言,也需要利用 J哭=:二維 ,和Q通道的取樣點在時間點上一致。本發日;^針使 =通 广J出有效的處理架構’藉以能夠減少唯讀記憶體内 的儲存資料量以及在不需要蔣如.念、士突从法,σ ±心 你个南罟移相濾波器的情況下達到 ϋ 時間點一致,藉以達到簡化設計和降低成本的目的。, 有鑑於此,本發明的主要目的,在於提供一種利用記 隐體實現之内插式濾波器,不僅能夠減少記憶體内的係數 資料量,同時也可以針對二維調變的數位資料,在不使用 移相濾波器的條件下’達到丨_Q通道間時間點一致性的效 果。 根據上述之目的,本發明提出一種闪插式濾波器,用 以接收一輸入相位量和一輸入取樣信號,產生具有與上述 輪入取樣信號不同取樣周期之一輸出取樣信號,每一相位 里對應於上述内插式濾波器之一組脈衡響應係數,利用上 迷輪入取樣信號和上述輸入相位量所對應之脈衝響應係 數’產生上述輸出取樣信號;上述内插式濾波器包括一記 憶體,用以分別儲存對應於上述輸入相位量之上述脈衝響 應係數,並且對於符合脈衝響應對稱性的第—相位量和第 相位量,儲存一組脈衝響應係數。Page 9 42 3 21 5 V. Description of the invention (7) The sampling points of the channels can be consistent in time. There is still a point in the processing of the conventional asynchronous sampling. For example, the conventionally improved part using only noise tp will correspond to each phase quantity c, that is, all the coefficients of u χ τ 1 M y. The pulse balance of (ψϋη X fs) follows the read-only memory, and there is no 44 Μ gastric response coefficient for the entire stored modulation digital data. J cry =: two-dimensional, and the sampling point of the Q channel is at Consistent in time. This issue date; ^ Need to make = Tong Guang J out of an effective processing architecture ', which can reduce the amount of data stored in the read-only memory and eliminate the need for Jiang Ru. In the case of phase-shifting filters, the time points are consistent, thereby simplifying the design and reducing costs. In view of this, the main object of the present invention is to provide an interpolation filter implemented by a memory, which can not only reduce the amount of coefficient data in the memory, but also can be used for two-dimensionally modulated digital data. Without using a phase-shifting filter, the effect of time point consistency between 丨 _Q channels is achieved. According to the above purpose, the present invention provides a flash plug-in filter for receiving an input phase amount and an input sampling signal, and generating an output sampling signal having a different sampling period from the round-in sampling signal, corresponding to each phase. Based on a set of pulse-balance response coefficients of the interpolation filter, the output sampling signal is generated by using the impulse response coefficient 'corresponding to the input signal and the input phase amount; the interpolation filter includes a memory. To store the above-mentioned impulse response coefficients corresponding to the above-mentioned input phase quantities, and to store a set of impulse response coefficients for the first phase quantity and the first phase quantity that conform to the symmetry of the impulse response.
第10頁 423215 w 五、發明說明(8) -- 另外在上述記憶體中,對應符合上述脈衝響應對稱性 之上述弟一相位1 ’係儲存對應於上述第一相位^之脈衝 響應係數的前半部分;對應符合上述脈衝響應對稱性之上 述第二相位量’係儲存對應於上述第二相位量之脈衝響應 係數的前半部分。 s心 此外’上述内插式濾波器尚包括:一位址產生器,根 據上述輸入相位量,依序產生第一位址訊息和第二位址訊 息至上述記憶體,上述第一位址訊息係根據上述輸入相位 里所產生’上述第二位址訊息係根據與上述輸入相位量符 合脈衝響應對稱性之互補相位量所產生,上述記憶體根據 第一位址訊息,輸出對應於上述輸入相位量的脈衝響應係 數前半部分,上述記憶體根據第二位址訊息’輸出對應於 上述互補相位量的脈衝響應係數前半部分;一輪入暫存器 組’用以儲存上述輸入取樣信號;一多工器組’用以從上 述輪入暫存器組中之上述輸入取樣信號中’依序選擇上述 ,入取樣信號之第一部分以及第二部分;乘法器,分別計 J對應於上述輸入相位量之脈衝響應係數前半部分和上述 取樣信號之第一部分的第一乘積值’以及計算對應於 述互補相位量之脈衝響應係數前半部分和上述輪入取樣 15 ^ ^ 乂弟二部分的第二乘積值;以及一加法器,用以加總 上述漦 ^ at 乘積值和上述第二乘積值’產生上述輪出取樣信 取 $外,上述内插式濾波器亦可以處理二維調變的輸入 ’信銳。其中,上述輸入取樣信號包括第一成分取樣信Page 10 423215 w V. Description of the invention (8)-In addition, in the above-mentioned memory, the first half of the phase corresponding to the above-mentioned impulse response symmetry 1 ′ stores the first half of the impulse response coefficient corresponding to the first phase ^ Part; the second phase amount corresponding to the symmetry of the impulse response is stored in the first half of the impulse response coefficient corresponding to the second phase amount. In addition, the above-mentioned interpolation filter further includes: a bit generator that sequentially generates a first address message and a second address message to the memory according to the input phase amount, and the first address message It is generated based on the input phase. The above-mentioned second address information is generated based on the complementary phase quantity that matches the symmetry of the impulse response with the above-mentioned input phase quantity. The memory outputs the first phase information corresponding to the above-mentioned input phase. The first half of the impulse response coefficient of the amount, the above-mentioned memory according to the second address message 'outputs the first half of the impulse response coefficient corresponding to the complementary phase amount; one round into the register group' for storing the above-mentioned input sampling signal; a multiplex The generator group is used to sequentially select the first and second parts of the input sampling signal from the input sampling signals in the above-mentioned register register; the multiplier counts J corresponding to the input phase amount. The first product value of the first half of the impulse response coefficient and the first part of the above-mentioned sampling signal, and calculating a value corresponding to the complementary phase amount The first half of the impulse response coefficient and the second product value of the above-mentioned in-sampling sample 15 ^ ^; and an adder for summing the above-mentioned product value 漦 ^ at and the second product value 'to generate the above-mentioned sample out In addition to the letter $, the above-mentioned interpolation filter can also process the input of two-dimensional modulation 'Xin Rui. Wherein, the above-mentioned input sampling signal includes a first component sampling signal
第11頁 五、發明說明(9) 號和第一成 產生器’根 取樣信號的 號的第一成 入相位量所 分相位量加 入取樣信號 的相位量值 位量產生第 二分量相位 上述記憶體 量產生,上 符合脈衝響 息係根據上 根據與上述 位量產生; 訊息、第三 分係數、第 分取樣信 據上述輸 第一成分 分相位量 產生,上 或減一常 之取樣周 。上述位 一位址訊 量產生第 ;上述第 述第二位 應對稱性 述第二成 第二成分 上述記憶 位址訊息 二部分係 本發明亦提供一 位量和一輸入取樣信 同取樣周期之一輸出 一成分取樣信號和第 存複數脈 的脈衝響 體,用以儲 息送出對應 括 第 位址 成分 分取樣# 據上述輸 述第一成 為上述輸 内所對應 一分量相 據上述第 ,輸出至 成分相位 分相位量 三位址訊 址訊息係 之互補相 第二位址 之第一部 分係數。 一輸入相 樣信號不 號包括第 一記憶 之位址訊 ,根據上 號,上 入相位 相位量 ,上述 述第二 數所產 期在上 址產生 息和第 三位址 一位址 址訊息 之互補 分相位 相位量 體根據 和第四 數、第 種内插 號*產 取樣信 二成分 衝響應 應係數 述内插 量,產 和對應 第一成 成分相 生。其 述第一 器根據 二位址 訊息和 訊息係 係根據 相位量 量產生 符合脈 上述第 位址訊 三部分 式濾、波 生具有 號,上 取樣信 係數, ;以及 式濾波 生對應 於上述 分相位 位量係 中上述 成分取 輸入之 訊息* 第四位 根據上 與上述 產生, ,上述 衝響應 一位址 息,輪 係數和 器,用 與上述 述輸入 號,其 並且根 一位址 第二成 量係根 根據上 常數係 樣信號 上述第 並且根 址訊息 述第一 第一成 上述第 對稱性 訊息、 出鮮應 第四部 輪入取 取樣信 據接收 產生器Page 11 V. Description of the invention (9) The number of phase components divided by the first component phase quantity of the number of the first sample generator and the number of the first sample generator signal is added to the phase quantity value of the sample signal to generate the second component phase. The volume is generated, and the pulse pulse is generated according to the above according to the above-mentioned bit volume; the message, the third sub-coefficient, and the second sub-sampling signal are generated according to the above-mentioned first component sub-phase amount, and are increased or decreased by a constant sampling period. The above-mentioned one-bit address signal generates the first; the above-mentioned second bit should be symmetrically described as the second component and the second component. The above-mentioned memory address information has two parts. The present invention also provides one-bit and one input sampling signal with the same sampling period. One output one component sampling signal and the pulse body of the stored multiple pulses, used to store interest and send the corresponding sub-address component sub-sampling # According to the above input first becomes a component corresponding to the above input according to the above, output The first partial coefficients of the complementary phase second address of the three-phase address information to the component phase-divided phase vector. An input phase-like signal does not include the address information of the first memory. According to the above number, the phase phase is entered. The above-mentioned second generation period generates information at the previous address and the third address one address information. Complementary phase separation and phase measurement are based on the interpolated amount of the two-component impulse response of the sampling number and the fourth number and the first type of interpolation number, and the product corresponds to the first component. The first device according to the two address information and the message system generates a pulse according to the phase quantity. The three-part filter of the first address signal, the wave generation has a number, the up-sampling signal coefficient, and the formula filter corresponds to the above. The phase quantity is the input information of the above component. The fourth digit is generated according to the above and the above. The above rush responds to a single address, the round coefficient and the device. The input number is the same as the above, and its root is the second. The component system is based on the above constant system sample signal and the root address information describes the first, first, and second symmetry information, and the response should be in the fourth round.
第12頁 4 23 21 5 城 五、發明說明(10) 述輸入相位量,產生對應於上述第一成分取樣信號的第一 成分相位量和對應於上述第二成分取樣信號的第二成分相 位量’做為上述記憶體之位址訊息,其中上述第_成分相 位量係根據上述輸入相位量所產生,上述第二成分相位量 係根據上述第一成分相位量加或減一常數所產生。其中上 述常數係為上述輸入取樣信號之取樣周期在上述第一成分 取樣信號内所對應的相位量值。上述記憶體包括内容相同 之一第一記憶體和一第二記憶體,分別對應於上述第一成 分取樣信號和上述第二成分取樣信號。另外,尚可以包括 一電路,用以對於上述第二成分取樣信號延遲一既定時 間。 1 圖式之簡單說明: 為使本發明之上述目的、特徵和優點能更明顯易僅, 下文特舉一較佳實施例,並配合所附圖式,作詳細說明如 下: 第1圖表示習知技術中採用反饋式同步取樣之接收系 統的方塊示意圖。 第2圖表示習知技術中採用非同步取樣之接收系統的 方塊示意圖。 第3圖表示在非同步取樣之接收系統中輸入取樣信號 , 和輸出取樣k號之間時間關係的時序圖。 第4圖表示習知技術中利用唯讀記憶體所實現之内摘 式濾波器的方塊示意圖。 第5圖表示習知技術中使用單一取樣器處理二維調變Page 12 4 23 21 5 City V. Description of the invention (10) The input phase amount described above generates a first component phase amount corresponding to the first component sampling signal and a second component phase amount corresponding to the second component sampling signal. As the address information of the memory, the _th component phase amount is generated according to the input phase amount, and the second component phase amount is generated according to the first component phase amount plus or minus a constant. The constant is the phase value corresponding to the sampling period of the input sampling signal in the first component sampling signal. The memory includes a first memory and a second memory having the same contents, which respectively correspond to the first component sampling signal and the second component sampling signal. In addition, a circuit may be included for delaying the second component sampling signal by a predetermined time. 1 Brief description of the drawings: In order to make the above-mentioned objects, features, and advantages of the present invention more obvious and easy, the following provides a preferred embodiment and the following detailed description in conjunction with the attached drawings: Figure 1 A block diagram of a receiving system using feedback synchronous sampling in the known technology. Fig. 2 is a block diagram showing a conventional receiving system using asynchronous sampling. FIG. 3 shows a timing diagram of the time relationship between the input sampling signal and the output sampling k number in the receiving system of asynchronous sampling. Fig. 4 shows a block diagram of an in-line filter implemented in a conventional technique using a read-only memory. Figure 5 shows the use of a single sampler to handle two-dimensional modulation in conventional techniques.
第13頁 五、發明說明(11) 數位資料時的時序圖。 第6圖表示習知技術中用以調整未對準之I通道和Q通 道取樣點的方塊示意圖。 第7圖表示本發明實施例中之内插式濾波器的系統方 塊圖。 第8圖表示一般内插式濾波器的典型脈衝響應波形並 且用以說明其波形對稱性的示意圖。 第9圖表示本發明第一實施例之内插式濾波器的方塊 示意圖。 第10圖表示使用單一取樣器處理二維調變數位資料時 的時序圖,用以說明本發明第二實施例中如何調整丨通道 和Q通道之間時間差的原理。 第11圖表示本發明第二實施例中Q通道内插式滤波器 的方塊示意圖。 第1 2圖表示本發明第二實施例中位址產生器的詳細電 路圖。 符號說明: 1〜類比處理部分;2 ~取樣器;3數位處理部分;4〜時 脈產生器;1卜取樣時脈信號;1 0〜取樣時序信號; 201a-2〇lh 、 203a-203h 、 101a-101h 、 105a-105d 、 107a-107d 、 113 、 131a‘131h 、 135a-135d 、 137a-137d 、 143~暫存器;20 53-2 0 511、109&-109(1、13 9&-139(1~乘法 器;207、120、150〜唯讀記憶體;209、111、112、115、 141、142、161〜加法器;21、22〜延遲器;3卜移相濾波Page 13 V. Description of the invention (11) Timing chart for digital data. Fig. 6 shows a block diagram of adjusting the misaligned I-channel and Q-channel sampling points in the conventional technique. Fig. 7 shows a system block diagram of the interpolation filter in the embodiment of the present invention. Fig. 8 shows a typical impulse response waveform of a general interpolation filter and is a schematic diagram for explaining the waveform symmetry. Fig. 9 is a block diagram showing an interpolation filter according to the first embodiment of the present invention. FIG. 10 shows a timing diagram when a single sampler is used to process two-dimensional modulated digital data, and is used to explain the principle of how to adjust the time difference between the channel and the Q channel in the second embodiment of the present invention. Fig. 11 is a block diagram showing a Q-channel interpolation filter in the second embodiment of the present invention. Fig. 12 shows a detailed circuit diagram of the address generator in the second embodiment of the present invention. Explanation of symbols: 1 ~ analog processing part; 2 ~ sampler; 3 digital processing part; 4 ~ clock generator; 1b sampling clock signal; 10 ~ sampling timing signal; 201a-2〇lh, 203a-203h, 101a-101h, 105a-105d, 107a-107d, 113, 131a'131h, 135a-135d, 137a-137d, 143 ~ registers; 20 53-2 0 511, 109 & -109 (1, 13 9 &- 139 (1 ~ multiplier; 207, 120, 150 ~ read-only memory; 209, 111, 112, 115, 141, 142, 161 ~ adder; 21, 22 ~ delayer; 3 phase shift filter
4 23 215 五、發明說明(12) 器;20、30、100~ 内插式濾波器;1〇3&—i〇3d、ιΐ7、 i33a-i33d、:63〜多工器;165〜反相器;ΐ7〇ι通道位 息;1 8 0、1 8卜Q通道位址訊息。 ° 實施例: 本發明主要是提出-種可以適用於非同步取樣接 統内的内插式m架構’其主要是利用記憶體(特別是' 唯讀記憶體)儲存脈衝響應係數的方式加以實現,但是 於習知技術,不僅可以減少所需儲存的係數資料量,同 可以在處理二維調變數位資料時不需要使用到移相渡波 器。4 23 215 V. Description of the invention (12); 20, 30, 100 ~ interpolation filter; 10 & -i03d, ιΐ7, i33a-i33d,: 63 ~ multiplexer; 165 ~ inverter Device; ΐ70 〇 channel information; 180, 18 Q channel address information. ° Example: The present invention mainly proposes an interpolation m architecture that can be applied to an asynchronous sampling system, which is mainly implemented by using a memory (especially a 'read-only memory') to store impulse response coefficients. However, in the conventional technology, not only the amount of coefficient data to be stored can be reduced, but also the phase-shifting wave wave does not need to be used when processing two-dimensional modulated digital data.
第7圖表示本發明中内插式濾波器的系統方塊圖。内 插式遽波器1〇〇主要是接收輸入取樣信號x(mTs),用以產 生與數位資料符號速率同步的輸出取樣信號以^。,另— 個輸入則是相位量Φ °在本發明中,内插式濾波器1〇〇是 利用内部的唯讀記憶體來儲存係數,其根據輸入的相位量 Φ ’從唯讀記憶體中找出與其對應的濾波器脈衝響應係 數’與輸入取樣信號x(mTs)進行迫旋積分處理後產生所需 要的輸出取樣信號y (nD。如果兩個輸入取樣值(取樣周 期為Ts)之間量化為N等分,則相位量φ在〇〜(N _丨)的範圍 内。參數N可以選擇為2的次方值,例如2 5 6 ( = 28) 〇另外, 本發明中的内插式濾波器係以8節點濾波器為例,因此每 個相位量φ對應於8個濾波器係數值。但是必須說明的 是,上述量化等分和濾波器節點數量皆非用以限定本發 明,可依照實際應用而加以調整。FIG. 7 is a system block diagram of the interpolation filter in the present invention. The interpolator 100 mainly receives the input sampling signal x (mTs), which is used to generate an output sampling signal synchronized with the symbol rate of the digital data. The other input is the phase quantity Φ ° In the present invention, the interpolation filter 100 uses the internal read-only memory to store coefficients, which is obtained from the read-only memory according to the input phase quantity Φ ' Find the corresponding filter impulse response coefficient 'and the input sampling signal x (mTs) for forced integration to produce the required output sampling signal y (nD. If between two input sampling values (sampling cycle is Ts) When quantized as N, the phase amount φ is in the range of 0 ~ (N 丨). The parameter N can be selected as the power of 2, such as 2 5 6 (= 28). In addition, the interpolation in the present invention This filter uses an 8-node filter as an example, so each phase amount φ corresponds to 8 filter coefficient values. However, it must be noted that the above-mentioned quantization division and the number of filter nodes are not used to limit the present invention. It can be adjusted according to the actual application.
4 23 215 五、發明說明(13) 第一實施例: 本實施例主要是利用濾波器脈衝響應波形對稱的特 性,減少唯讀記憶體所需要儲存的係數數量,同時利用此 一特性,也可以減少計算迴旋積分時所需要的乘法 法器。 加 第8圖表不内插式濾波器的典型脈衝響應波形的波形 意垃圖二脈衝響應為對稱於謂的波型。内插式攄波器 1 00接收到相位量Φ時所輸出的係數值,即 取樣點T1〜T8上的數值;另外,當接收到相位量為4 23 215 V. Description of the invention (13) First embodiment: This embodiment mainly uses the characteristic of the filter impulse response waveform symmetry to reduce the number of coefficients that the read-only memory needs to store. At the same time, using this characteristic, it is also possible Reduces the multiplier needed to calculate the round integral. The waveform of a typical impulse response waveform of the non-interpolated filter in Figure 8 is shown in Figure 2. The impulse response of Figure 2 is symmetrical to the so-called waveform. The coefficient output when the interpolating wave filter 1 00 receives the phase amount Φ, that is, the value at the sampling points T1 to T8; In addition, when the received phase amount is
Q = 6_Φ)時所輸出的係數值,則為標示為取樣點S1〜S8上的 數值。根據脈衝響應波形的對稱性可知,n=s8, 特性,儲存於唯讀記憶體中的資料實際 ^ 存對應的8個係數/利用相疋位對旦於量州心)儲 性,嗔讀記憶體中對每個相位相的對稱 得到,因此可以查 相位量Ν_Φ(以下稱互補相位量) 例中是對應= 半的目的。雖然本實施 減半,但是實際上仍有I他;J的方式達到資料 僅儲存前N/2個相位景「 '鈿減方式,例如也可以 值,而後N/2個相位量方可17 )所對應的8個係數 @ Q窗I 1 亦可以由相稱性找出。 第9圖表不本實施例中根據減半 所建構之内插式滹浊哭沾 里之唯頊圮憶體 攻器的方塊圖。在第9圖中,1〇ia〜i〇ih 第16頁 A2321 5 五、發明說明(14) 表示用來儲存輸入取樣信號的暫存器。1〇3a〜1〇3(i為多工 器’用來在一次迴旋積分計算中分兩次取出輪入取樣信號 的前4個取樣值(儲存於暫存器以及後4個取樣 值(儲存於暫存器101e〜101h) M05a〜105d為暫存器,用來 儲存從多工器103a~103d所選擇的前半部和後半部輸入取 樣信號。107a~107d是暫存器,用來儲存從唯讀記憶體uo 所送出的係數值。109a〜10 9d是乘法器,用以計算對應輸 入取樣信號和係數之間的乘積值。1 11是加法器,用以計 算乘法器109a〜109d所輸出乘積值的總和。113是暫存器, 用以暫存第一次乘積值。112是加法器,用以計算兩次乘 積值的總和。唯讀記憶體120是用來儲存内插式濾波器ι〇〇 的脈衝響應係數’對於每個相位量φ分別儲存前4個係數 值。114為位址產生器(address generator),其包含加法 器11 5和多工器11 7 ’用來對唯讀記憶體丨2 〇提供兩次定址 訊息。 根據先前所述’在唯讀記憶體120中,每個相位量φ 只有儲存4個對應的係數’其餘4個係數必須由互補相位量 N- Φ找出。因此,當輸入為相位量①時,必須使用兩次位 址索引才可以取得完整的係數值,一次利用相位量φ,另 一次則利用互補相位量N- φ。因此整個迴旋積分的計算必 須分兩個步驟進行。 在第一次計算步驟中’多工器117選擇相位量φ做為 定址訊息,送至准讀記憶體1 2 〇中。唯讀記憶體丨2 〇則將對 應的4個係數送出並儲存於暫存器丨ο。] 〇7d。另一方面,The value of the coefficient output when Q = 6_Φ) is the value marked at the sampling points S1 to S8. According to the symmetry of the impulse response waveform, it can be known that n = s8, the characteristic, the data stored in the read-only memory is actually ^ stores the corresponding 8 coefficients / uses the relative bit to compare to the heart of the state.) The symmetry of each phase in the body is obtained, so you can check the phase amount N_Φ (hereinafter referred to as the complementary phase amount). In the example, the purpose is corresponding = half. Although this implementation is halved, there are still others; the way of J is to store the data and only store the first N / 2 phase scenes. "'Decrement method, for example, it can also be a value, and the last N / 2 phase quantities can be 17) The corresponding 8 coefficients @ Q 窗 I 1 can also be found by proportionality. The 9th chart is not based on the interpolation type constructed in this embodiment based on halving. Block diagram. In Figure 9, 10a ~ i〇ih Page 16 A2321 5 V. Description of the invention (14) represents the register used to store the input sampling signal. 103a ~ 103 (i is The multiplexer 'is used to take out the first 4 sampling values of the round-in sampling signal (stored in the temporary register and the last 4 sampling values (stored in the temporary register 101e ~ 101h) M05a ~ 105d is a register used to store the input sampling signals from the first half and the second half selected by the multiplexers 103a to 103d. 107a to 107d are used to store the coefficient values sent from the read-only memory uo 109a ~ 10 9d is a multiplier used to calculate the product value between the corresponding input sampling signal and the coefficient. 1 11 is an adder used to calculate Calculate the sum of product values output by multipliers 109a to 109d. 113 is a temporary register to temporarily store the first product value. 112 is an adder to calculate the sum of two product values. Read-only memory 120 is The impulse response coefficient 'used to store the interpolation filter ι〇〇 stores the first four coefficient values for each phase amount φ. 114 is an address generator, which includes an adder 115 and a multiplexer. The device 11 7 ′ is used to provide two addressing information to the read-only memory 丨 2 0. According to the foregoing description, in the read-only memory 120, each phase quantity φ only stores 4 corresponding coefficients, and the remaining 4 coefficients It must be found by the complementary phase amount N- Φ. Therefore, when the input is the phase amount ①, the address index must be used twice to obtain the complete coefficient value, once using the phase amount φ, and the other time using the complementary phase amount N -φ. Therefore, the calculation of the entire convolution integral must be performed in two steps. In the first calculation step, the multiplexer 117 selects the phase amount φ as the addressing message and sends it to the quasi-read memory 1 2 0. Read-only Memory 丨 2 〇 will correspond to The 4 coefficients are sent and stored in the temporary register. 丨 ο. 〇7d. On the other hand,
4 2 3 215 五、發明說明(15) 多工器103a〜103d則選擇儲存於暫存器1〇la〜1〇ld的前 取樣值’送至暫存器1 0 5a〜1 〇5d。必須說明的是,為了 得係數和取樣值的傳送時間一致,在實作上暫存器 l〇5a〜l〇5d可能包含一個或多個d型正反器,笋 遲:乘法器i i _則計算前4個輸入取樣=^/延 存器105a〜105d)以及對應之4個係數(儲存於暫存器 l〇7a~l〇7d)的乘積,而乘積值則送至加法器ln算^出第一 次的乘積總和值後,儲存於暫存器i丨3中。 在第二次計算步驟中,多工器117則選擇由加法哭 所得之互補相位量N- Φ做為定址訊息,送至唯讀記憶°°體 120中。唯讀記憶體12〇則將對應於互補相位量①的^ ^數送出到暫存器107a~1〇7d,其等於對應於相位量①的 後個係數,不過其中次序顛倒。另一方面,多工器 1〇3&〜1〇3(1則選擇儲存於暫存器1〇16~1〇1[1 值’送至暫存器,同樣的,其次序也^^ ,聚=法器l〇9a〜1〇9d則計算後4個輸入取樣值(儲存於 存器105a〜105d)以及對應之4個係數(儲存於暫存器 〜4!°Jd)的乘積,並且將乘積值分別送至加法器111, :2 ί二次乘積總和值。最後將第一次乘積總和值和第 中對應的取樣值。 相加即產生輸出取樣信號 本實施例的内插式濾波器之優點在於: 體的存於唯讀記憶體的係數資料量減半,降低記憶4 2 3 215 V. Description of the invention (15) The multiplexers 103a ~ 103d choose to store the pre-sampled values in the temporary registers 10la ~ 10ld and send them to the temporary registers 105a ~ 105d. It must be noted that, in order to obtain the same transmission time of the coefficients and sample values, in practice the registers 105a to 105d may include one or more d-type flip-flops. Calculate the product of the first 4 input samples = ^ / delay registers 105a ~ 105d) and the corresponding 4 coefficients (stored in the temporary registers 107a ~ 107d), and the product value is sent to the adder ln to calculate ^ After the first product sum value is obtained, it is stored in the temporary register i 丨 3. In the second calculation step, the multiplexer 117 selects the complementary phase amount N-Φ obtained by the addition as an addressing message and sends it to the read-only memory °° 120. The read-only memory 120 sends the ^ ^ number corresponding to the complementary phase amount ① to the registers 107a to 107d, which is equal to the latter coefficient corresponding to the phase amount ①, but the order is reversed. On the other hand, the multiplexers 103 & 103 (1 is selected to be stored in the temporary register 1016 ~ 101 [1 value 'and sent to the temporary register. Similarly, the order is also ^^, The poly = method 109a ~ 109d calculates the product of the four input sample values (stored in the registers 105a ~ 105d) and the corresponding four coefficients (stored in the register ~ 4! ° Jd), and Send the product values to the adder 111, respectively: 2 ί The sum of the second product. Finally, the sum of the first product and the corresponding sample value in the first. Add to produce the output sample signal. Interpolation filtering in this embodiment The advantages of the device are: The amount of coefficient data stored in the read-only memory is halved, which reduces the memory
第18頁 4 23 21 5 五、發明說明(16) " ---- (2 )進行適旋積分所需要的乘法器和加法器 半,降低元件成本。 ° 减 必須說明的是,由於在本實施例中是對每個相位旦八 別儲存4個係數的方式實施,所以需要進行兩次記憶體$ 77 取’但是若改變唯讀記憶體1 2 〇内的資料儲存方式f也广 以在減半係數資料量的條件下’僅需一次計算即可完成*、回 旋積分運算;例如在唯讀記憶體中僅儲存相位量φ為趣 ^(N/2-l)的部分’但是對於每個相位量都儲存完整的係 數。輸入的相位量φ無論是小於或大於N/2,都可以—文 取出所有的係數值。 =Page 18 4 23 21 5 V. Description of the invention (16) " ---- (2) Multiplier and adder required for performing the spin integral half, reducing component cost. ° Subtraction must be explained, because in this embodiment, 4 coefficients are stored for each phase, it is necessary to perform two memory $ 77 fetches, but if you change the read-only memory 1 2 〇 The data storage method f is also widely used under the condition of halving the amount of coefficient data ', which can be completed with only one calculation *, convolution integral operation; for example, only storing the phase amount φ in the read-only memory is interesting ^ (N / Part of 2-l) 'but the complete coefficients are stored for each phase quantity. The input phase amount φ can be less than or greater than N / 2, and all coefficient values can be taken out. =
第二實施例: 本實施例除了利用脈衝響應波形對稱性來減半所需要 儲存的係數資料量,更進一步對於二維調變數位資料但只 使用單一取樣器進行取樣的情況’利用嗔讀記憶體的係數 資料架構進行處理,不需要使用到移相濾波器。 :) 參考第10圖,其表示以單一取樣器、取樣周期為TSAM 進行取樣,並且將各取樣值分配至I通道和Q通道上的時序 圖。其中,取樣點A、C、E屬於I通道,取樣點B、D、F則 屬於Q通道。在同一通道内的相鄰取樣點間的時間間隔為 2TSAM。因此,若在某一通道中利用内插式濾波器在連續兩 點間做内差,其全部相位量360 °等於2TSAM。換言之,實 際取樣相鄰點間(例如取樣點A和B)的相位量Φ等於N/2。 在本實施例中,主要是將I通道和Q通道間時間的對準合併 於内插式濾波器中一併處理。換言之’即是利用不同的位Second embodiment: In this embodiment, in addition to using the symmetry of the impulse response waveform to halve the amount of coefficient data that needs to be stored, it further takes the case of two-dimensionally modulating digital data but using only a single sampler for sampling. The coefficient data structure of the volume is processed without using a phase shift filter. :) Refer to Figure 10, which shows the timing diagram of sampling with a single sampler, sampling period for TSAM, and allocating the sampled values to the I and Q channels. Among them, sampling points A, C, and E belong to the I channel, and sampling points B, D, and F belong to the Q channel. The time interval between adjacent sampling points in the same channel is 2TSAM. Therefore, if an interpolation filter is used to make the internal difference between two consecutive points in a channel, the total phase amount of 360 ° is equal to 2TSAM. In other words, the phase amount Φ between adjacent points of actual sampling (for example, sampling points A and B) is equal to N / 2. In this embodiment, the time alignment between the I channel and the Q channel is mainly combined in an interpolation filter and processed together. In other words ’is to use different bits
第19頁 ^^321 5 五、發明說明(17) 址索引訊息來處理I通道和Q通道的取樣點’在本實施例中 是利用I通道進行内插式濾波器處理所使用的相位量Φ, 加上或減去一常數’產生Q通道進行内插式濾波器處理所 使用的相位量。以下先說明其工作原理。 Μ 假設系統決定出點X為需要的新取樣點,則會對I通道 的内插式滤波Is送入點X和取樣點C之間的相位量φ i,也 就是對於取樣點C進行多少修正後可以在點X上產生新取樣 值。由圖可知’相位量小於N/2,並且在點X上的新取 樣值是利用取樣點C和取樣點E上的取樣值以相位量内 差產生。若要在Q通道上的點X上產生新取樣值,則必須利 用取樣點B和取樣點D進行内差,此時所使甩的相位量為φ + N/2。 另一方面,假設系統決定出點γ為需要的新取樣點, 其與點X的情況稍微不同。此時對I通道的内插式濾波器送 入點Υ和取樣點c之間的相位量φ2,其大於Ν/2。在點γ上 的新取樣值是利用取樣點C和取樣點Ε上的取樣值以相位量 Φ2内差產生,但是若要在Q通道上的點γ上產生新取樣 值’則必須利用取樣點D和取樣點Φ進行内差,此時所使 用的相位量為φ—Ν/2。 總結而言,系統利用反饋機制可以決定出I通道内插 式滤波器所對應的相位量φ ’而根據此相位量φ是否小於 Ν/2 ’可以決定出Q通道内插式濾波器所對應的相位量是φ + Ν/ 2或是Φ-ν/2 ’藉此I通道和Q通道上所内插產生的新取 樣點’便可以在時間點上取得一致。Page 19 ^^ 321 5 V. Description of the invention (17) Address index information to process the sampling points of I channel and Q channel 'In this embodiment, the phase amount used by I channel for interpolation filter processing Φ Add or subtract a constant 'to generate the amount of phase used by the Q channel for interpolation filter processing. The working principle is explained below. Μ Assuming that the system decides that the output point X is the new sampling point required, the phase amount φ i between the input point X and the sampling point C of the interpolation filter Is of the I channel, that is, how much correction is made to the sampling point C A new sample value can then be generated at point X. It can be seen from the figure that the phase amount is smaller than N / 2, and the new sample value at the point X is generated by using the sample values at the sampling point C and the sampling point E as the phase difference. If a new sampling value is to be generated at point X on the Q channel, the internal difference between sampling point B and sampling point D must be used. At this time, the phase amount to be shaken is φ + N / 2. On the other hand, suppose that the system decides that the point γ is the required new sampling point, which is slightly different from the case of the point X. At this time, the phase amount φ2 between the input point Υ and the sampling point c for the interpolation filter of the I channel is larger than N / 2. The new sampling value at point γ is generated by using the sampling value at sampling point C and sampling point E as the internal difference of the phase amount Φ2, but to generate a new sampling value at point γ on the Q channel, you must use the sampling point. D and the sampling point Φ perform an internal difference, and the phase amount used at this time is φ-N / 2. In summary, the system uses the feedback mechanism to determine the phase amount φ 'corresponding to the I-channel interpolation filter, and according to whether this phase amount φ is less than N / 2', it is possible to determine the phase corresponding to the Q-channel interpolation filter. The phase amount is φ + Ν / 2 or Φ-ν / 2 'the new sampling points generated by interpolation on the I channel and the Q channel' can be consistent at the time point.
第20頁 423215 五、發明說明(18) 斗如松 a 如果將此I-Q通道處理^與第一實施例中所述結 合 則可以歸納出以下-條:(二:稱條件… (1)類似點X的情況,其 /2 第一次計算: Μ !通道:使用相位用點C、E進行内插❹ Q通道:使用相位耋Φ + Ν’2 ’利用點B、D進行内插 第二次計算 φ,利用點C、E進行内插 I通道:使用相位實τ小、χτ . /善(Ν—φ)-Ν/2’利用點Β、Ρ進仃 道:使用相徂奥 m 通 内插 中 Φ 2N/2 (2)類似點Y的情況 第—次計算: I通道:使用相位量Φ N1用點C、E進行内插 ㈣道:使用相位耋Φ —N/2,利用點D、F進行内插 ^ ^ ^ ^ f ;NI #,J ^ . E ^ ^ (3通道:使用相位耋(N ) + N/2 ’利用點D、F進行 内插 以下說明其實現方式。中,1通道和Q通道 的取樣值是分別送到對應的慮波器中。1通道的内 插式濾波器基本架構與第9 m目:,’此處不再贅述。 第11圖表示本實施例中〇通二 式遽波器的方塊圖,其 中位址產生器1β〇對於I通道和Q通道内插式渡波器3 、 的部分。在第11圖中,131a~131h表示用來儲存Q疋、用 現輸入_Page 20 423215 V. Description of the invention (18) Dou Songsong a If this IQ channel is processed ^ combined with the description in the first embodiment, the following can be summarized: (two: the conditions ... (1) similarities In the case of X, its / 2 is calculated for the first time: Μ! Channel: Interpolate with points C and E using phase ❹ Q channel: Interpolate with phase 耋 Φ + Ν'2 'Use points B and D for the second time Calculate φ, use points C and E to interpolate I channel: use phase real τ small, χτ. / Good (N—φ) -N / 2 ′ use points B, P to enter the channel: use phase 徂 m m pass Interpolation Φ 2N / 2 (2) Cases similar to point Y First calculation: Channel I: Use phase amount Φ N1 Interpolate with points C and E E Channel: Use phase 耋 Φ —N / 2, use point D Interpolate with F and ^ ^ ^ ^ f; NI #, J ^. E ^ ^ (3 channels: use phase 耋 (N) + N / 2 'interpolate with points D and F. The following describes its implementation. Medium The sampling values of the 1 channel and the Q channel are sent to the corresponding wave filter. The basic structure of the 1-channel interpolation filter and the 9th item: "'No further description here. Figure 11 shows this implementation In the example The block diagram of the conventional two-wave generator, in which the address generator 1β〇 for the I-channel and Q-channel interpolating wave generator 3, in Figure 11. In Figure 11, 131a ~ 131h are used to store Q 疋, use Enter _ now
第21頁 423215 五、發明說明(19) 取樣信號的暫存器。133a〜133d為多工器,用來在一次迴 旋積分計算中分兩次取出Q通道輸入取樣信號的4個取樣 值。參考前述之條件I,對於I通道的相位量φ小於或大於 N/2的不同情況,Q通道進行内插的取樣點則會不同。因 此’多工器133a〜133d為4:1的多工器,必須根據相位量φ 與N/2之間的比較結果,調整進行内插的取樣點位置,也 就是可以選擇性地對q通道上的取樣值延遲巧娜時間(在q 通道中間隔一個暫存器取出取樣值’即對應於2 了咖)。另 外’在I通道部分的這組多工器僅需使用2:1多工器,其架 構與第一實施例中情況相同。1 35a〜丨35d則是用來儲存從 多工器133a〜133d所選擇之輸入取樣信號的暫存器。 137a〜137d則是用來儲存從唯讀記憶體15〇所送出係數的暫 存器。139a〜139d是乘法器,用以計算對應輸入取樣信號 和係數之間的乘積值β 1 4 1是加法器’用以計算乘法写 139a〜139d所輸出乘積值的總和。143是暫存器,用以^暫存 第一次乘積總和值。i 42是加法器,用以計算兩次乘 和值的加總。 〜 唯讀記憶體1 50是用來儲存内插式濾波器的脈衝響應 係數值,對於每個相位量分別儲存前4個係數值。在丄實 施例中,唯讀記憶體1 5〇可以同時提供& j通道和Q通首 行存取,也可以利用兩個内容相同的唯讀記憶體模纟/,八 別供I通道和Q通道進行存取。後者的優點在於^道刀雨 道可以=時處理,II以加快處理的速度,不過所需要二 的係數資料則較前者增加一倍。丨6 0為位址產生器,在本Page 21 423215 V. Description of the invention (19) Register for sampling signals. 133a to 133d are multiplexers, which are used to take out the four sampling values of the input sampling signal of the Q channel twice in one cycle integral calculation. Referring to the aforementioned condition I, for different cases where the phase amount φ of the I channel is less than or greater than N / 2, the sampling points for the Q channel interpolation are different. Therefore, the multiplexers 133a to 133d are 4: 1 multiplexers, and the positions of the sampling points to be interpolated must be adjusted according to the comparison result between the phase quantities φ and N / 2, that is, the q channel can be selectively selected. The sampled value is delayed by Qiao Na time (the sampled value is taken out in a register in the q channel, which corresponds to 2). In addition, this group of multiplexers in the I-channel portion need only use a 2: 1 multiplexer, and its structure is the same as that in the first embodiment. 1 35a ~ 35d is a register for storing the input sampling signals selected from the multiplexers 133a ~ 133d. 137a ~ 137d are temporary registers used to store the coefficients sent from the read-only memory 150. 139a to 139d are multipliers, which are used to calculate the product value β 1 4 1 between the corresponding input sampled signal and the coefficient, which are adders' used to calculate the sum of the multiplied output values written by 139a to 139d. 143 is a temporary register for temporarily storing the sum of the first product. i 42 is an adder that calculates the sum of two multiplications and sums. ~ The read-only memory 1 50 is used to store the impulse response coefficient values of the interpolation filter, and the first 4 coefficient values are stored for each phase amount. In the embodiment, the read-only memory 150 can provide & j channel and Q pass first-line access at the same time, or two read-only memory modules with the same content can be used. Q channel for access. The advantage of the latter is that it can be processed at one time, and II can speed up the processing speed, but the coefficient data required for the two is doubled compared with the former.丨 60 is the address generator.
4 23 21 5 ) _ 五、發明說明(20) 實施例中,根據輪入的相位量Φ可以產生唯讀記憶體1 5〇 的I通道位址訊息以及Q通道位址訊息。 在第11圖中必須進一少說明者為位址產生器160,除 了多工器133a~ 133d可以選擇性地對於Q通道上的取樣點延 遲2TSAM ’其餘部分動作基本上與第一實施例中相同。位址 產生器1 6 0可以直接利用前述的條件I加以實現。亦即,I 通道的位址訊息可以直接利用相位量Φ和互補相位量N - φ 產生;Q通道的位址訊息則是根據相位量Φ小於或大於N / 2 以及第幾次步驟的不同情況,將I通道的位址訊息加上N / 2 或減去N/2來產生。 事實上,上述的條件I可以簡化成較易實現的形式。 設I通道所使用的相位量為Θ ’ 0可能是Φ或是N- Φ。根 據0是否小於N/2,可以歸納出下列條件(以下稱條件 II): (1) 當6KN/2,則Q通道的相位量為0+N/2 (2) 當0 2N/2,則Q通道的相位量為Θ-Ν/2 本實施例中主要根據條件11來實現位址產生器i 6 〇。 第1 2圖表示本實施例中位址產生器1 6 〇的詳細電路圖。如 圖所示,位址產生器160包括加法器161、多工器163和反 相器1 6 5。另外’ 1 7 〇表示I通道位址訊息;1 8 0〜1 8 1則表示 Q通道位址訊息’其中180為第1個至第(本實施例 中為7 )個位元,1 81為第1 〇g2N (本實施例中為8 )個位元。 首先說明I通道位址訊息170的產生方式。參考前述的 條件I ’可知在第一次計算步驟中,i通道位址訊息丨7〇等4 23 21 5) _ V. Description of the invention (20) In the embodiment, the I-channel address information and Q-channel address information of the read-only memory 150 can be generated according to the phase amount Φ in turn. In Fig. 11, a little explanation is needed for the address generator 160. Except for the multiplexers 133a to 133d, the sampling point on the Q channel can be selectively delayed by 2TSAM. The rest of the operations are basically the same as in the first embodiment. . The address generator 160 can be directly implemented by using the foregoing condition I. That is, the address information of the I channel can be directly generated using the phase quantity Φ and the complementary phase quantity N-φ; the address information of the Q channel is based on the phase quantity Φ less than or greater than N / 2 and the number of different steps. Add the address information of I channel to N / 2 or subtract N / 2 to generate. In fact, the above-mentioned condition I can be simplified into a form that is easier to implement. Let the phase amount used by the I channel be Θ '0, which may be Φ or N- Φ. According to whether 0 is less than N / 2, the following conditions can be summarized (hereinafter referred to as condition II): (1) When 6KN / 2, the phase quantity of the Q channel is 0 + N / 2 (2) When 0 2N / 2, then The phase amount of the Q channel is Θ-N / 2. In this embodiment, the address generator i 6 0 is mainly implemented according to the condition 11. FIG. 12 shows a detailed circuit diagram of the address generator 16 in this embodiment. As shown in the figure, the address generator 160 includes an adder 161, a multiplexer 163, and an inverter 165. In addition, '1 7 〇 means I channel address information; 1 0 0 ~ 1 8 1 means Q channel address information', where 180 is the first to the (7 in this embodiment) bits, and 1 81 is 10 g2N (8 in this embodiment) bits. First, the generation method of the I-channel address information 170 will be described. With reference to the aforementioned condition I ′, it can be known that in the first calculation step, the address information of the i-channel 丨 7〇, etc.
第23頁Page 23
五、發明說明(21) 於輸入的相位量φ ;在第二次計算步驟中,I通道位址訊 息1 70則等於互補相位量Φ。加法器1 61和多工器丨6 3即 用來直接產生I通道位址訊息17〇。加法器161產生互補相 位量N- φ,與相位量Φ 一併輪入至多工器163。多工器163 則在第一次計算步驟和第二次計算步驟時分別選擇出相位 量F和互補相位量N - Φ做為I通道位址訊息1 7 0。 Q通道位址訊息(1 8 0、1 81 )的產生方式則根據條件 II。在條件I I中’只考慮Ϊ通道位址訊息1 70 (以Θ表示, 可能為Φ或N- Φ )便可以決定Q通道位址訊息。條件丨〖的實 現方式可以直接將Θ的最面位元(most significant bit ’ MSB)進行反相來達成。當0小於N/2時,Θ的最高位 元為"0 ” ’此時需要將Θ加上Ν / 2來得到Q通道位址訊息, 也就是將β的最高位元變為”1” ,而其他位元不變。另一 方面,當0大於Ν/2時,0的最高位元為"1",此時需要將 Θ減去Ν/2來得到Q通道位址訊息,也就是將θ的最高位元 變為"(Τ’而其他位元不變。換言之,無論右是大於或小 於Ν/2 ’只要將θ的最高位元反相(即第12圖之181),其他 位兀維持不變(即第12圖之182),便可以得到完整的Q通道 ,址訊息。如果Θ等於Ν/2為—特殊情況,這表示前後兩 -欠的I通道位址訊息17〇(分別為①和Ν_φ)均為Ν/2,此時 對應的Q通道位址訊息(1 8 0、1 8 1 )分別為0和Ν。此部分可 以=用其他特殊處理電路加以處理,此處則不再贅述。利 12圖所二之電路來實現位址產生器160,不僅在電路 貝現上較·為簡潔,同時I通道和Q通道的位址訊息幾乎是在5. Description of the invention (21) The input phase amount φ; in the second calculation step, the I channel address information 1 70 is equal to the complementary phase amount Φ. The adder 161 and the multiplexer 63 are used to directly generate the address information of the I channel 170. The adder 161 generates a complementary phase amount N- φ and turns it into the multiplexer 163 together with the phase amount Φ. In the first calculation step and the second calculation step, the multiplexer 163 selects the phase amount F and the complementary phase amount N-Φ as the address information of the I channel 1 70 respectively. The generation of the Q channel address information (180, 1 81) is based on condition II. In the condition I I, only considering the channel address information 1 70 (indicated by Θ, which may be Φ or N-Φ), the Q channel address information can be determined. The implementation of the condition 丨 can be achieved by directly inverting the most significant bit ’MSB of Θ. When 0 is less than N / 2, the most significant bit of Θ is " 0 '' 'At this time, Θ needs to be added to N / 2 to obtain the Q channel address information, that is, the most significant bit of β is changed to "1" , But the other bits are not changed. On the other hand, when 0 is greater than N / 2, the highest bit of 0 is " 1 ". At this time, it is necessary to subtract Θ / 2 to obtain the Q channel address information. It is to change the highest bit of θ to " (T 'and the other bits are unchanged. In other words, whether the right is greater than or less than N / 2', just invert the highest bit of θ (ie, 181 in Figure 12) If the other bits remain unchanged (ie, 182 in Figure 12), you can get the complete Q channel address information. If Θ is equal to N / 2, it is a special case, which means that the two channels before and after the I channel address information are owed. 17〇 (respectively ① and N_φ) are both N / 2, and the corresponding Q channel address information (1 0 0, 1 8 1) is 0 and N, respectively. This part can be processed by other special processing circuits. The circuit in Figure 12 is used to implement the address generator 160, which is not only simpler in the circuit, but also the address information of the I channel and the Q channel. Almost at
第24頁 42 321 5 五、發明說明(22) m '--------- 同時間内計算出,因此可以得到 最後必須說明的是,本實施例=效能。 訊Page 24 42 321 5 V. Description of the invention (22) m '--------- Calculated at the same time, so it can be obtained Finally, it must be explained that this embodiment = performance. Information
職一常數 習知技術中所使用移相濾波装从值 Η I本- 及态的優點。 本發明雖以一較佳實施彳 定本發明,任何熟習此項技蓺者J如上,然其並非用以限 和範圍内’當可做些許的更二者、’在不脫離本發明之精神 範圍當視後附之申請專利飾,因此本發明之保 视圍所界定者為準D I 的處理技術與第一實施例中減少係雖然結合對1 -Q通道 可以單獨實施。亦即,無論唯譫_、的技術,但是兩者均 半,只要對於Q通道取樣點選擇性叫體内的係數是否減 息是由工通道位址訊息加;^„^延€以及讓^道位址 知技術中所使用移相濾波器的=:同樣可以達到去除Position-constant The phase-shift filter used in the conventional technique has the advantage of the value Η I-and the state. Although the present invention defines the present invention with a preferred implementation, any person skilled in the art is the same as above, but it is not intended to be used within the scope and scope of 'a few more,' without departing from the spirit of the present invention. When the attached patent application is regarded as attached, the processing technology of DI according to the definition of the protection scope of the present invention is the same as the reduction in the first embodiment, although the 1-Q channel can be implemented separately in combination. That is, regardless of the technology of 谵 _, but both are half, as long as the Q channel sampling points are selectively called whether the coefficient in the body is reduced by interest, the channel address information is added; ^ „^ Extend € and let ^ The phase shift filter used in the channel address knowing technology =: can also be removed
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Application Number | Priority Date | Filing Date | Title |
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TW88115969A TW423215B (en) | 1999-09-16 | 1999-09-16 | Interpolation filter implemented by the memory |
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TW88115969A TW423215B (en) | 1999-09-16 | 1999-09-16 | Interpolation filter implemented by the memory |
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