TW423215B - Interpolation filter implemented by the memory - Google Patents

Abstract

An interpolation filter is used to reduce the filter coefficients required by the memory and the phase shift filter required by the two-dimensional modulation digital data using a single sampler. The interpolation filter comprises a memory for storing the impulse response coefficients corresponding to the phase magnitudes respectively; and storing a set of impulse response coefficients for the two phase magnitudes corresponding to the symmetric impulse response waveform so as to reduce the amount of coefficient data to a half. Further, the address generator in the interpolation filter is used to generate the memory address message corresponding to the I channel and Q channel, and the address message of the Q channel can be generated by adding or deducting a constant from the address message of the I channel, and selectively delaying the sampling value of the Q channel a certain period of time so as to achieve a consistent time point.

Description

4 2 3 21 5 ^ V. Description of the invention α) The present invention relates to an interpolation filter implemented by a digital synchronization technology 'especially using read only memory (ROM) ° In general digital communication systems, digital data is transmitted on analog signals. At this time, the digital lean material can be modulated using methods such as p SK (phase shift key) or QAM (quadrant amplitude modulation). The data is then modulated on a continuous wave by modulation methods such as PAM (pulse amp 1 amplitude modulation). Therefore, before demodulating digital data, the receiver must use the analog-to-digital (A / D) action to further process the real digital data. This analog-to-digital action is called sampling (samp 1 i ng). Common sampling methods can be divided into two types: synchronous sampling and asynchronous sampling. Among them, synchronous and asynchronous means whether the sampling clock signal is consistent with the symbol rate of the input digital data. Synchronous sampling is Sampling using a sampling clock (samp 1 ing clock) that is consistent with the symbol rate of the round-in digital data, generally uses feedback control to achieve consistency between the two. Figure 1 shows the use of feedback in the conventional technology. A block diagram of a receiving system with synchronous sampling. Among them, 1 is the analog processing part, which is used to process the analog signal with digital data. 2 is the sampler, which samples according to the sampling clock signal 11. 3 y is the digital The processing part performs digital demodulation on the sampled value to generate the required digital data. 4 represents the clock generator, which is used to generate the sampling clock signal i 丨 required for sampling. In the feedback-type synchronous sampling system, Timing control signals required by the clock generator 4 (timing controi

Page 4 4 2 3 215 Mt V. Description of the invention (2) signa 1) 10 is generated by demodulating digital data from 3 digital processing units. Generally, in a feedback synchronous sampling system, the clock signal originally generated by the clock generator 4 is very close to the symbol rate of the digital data. The feedback mechanism is mainly to make the synchronization more accurate. However, in some cases, it is not easy to synchronize the symbol rates of the sampling clock signal 11 and the digital signal. For example, the receiver receiver contains several signals with different rates / channels, but there is not enough number of oscillators in the system that meet the specifications. At this time, it is difficult to synchronize the two. Even if controlled by feedback, the effect is not obvious.

Asynchronous sampling technology can overcome the above-mentioned problem that the sampling clock and symbol rate cannot be made consistent through the synchronous sampling method. Fig. 2 shows a block diagram of a receiving system using asynchronous sampling in the prior art. In the asynchronous sampling system, the sampling clock signal 11 generated by the 'clock generator 4 has a certain frequency. Because there is no synchronization process, the frequency of the sampling clock signal j j usually does not match the symbol rate of the input digital data. The sampled signal "is" (sampled signal) output by the sampler 2 uses the digital processing section 3 to perform digital signal processing and perform rate conversion (conversion) to generate a sample value that is consistent with the original digital signal symbol rate. The digital processing section 3 usually uses an interpolation filter

(interpolation filter) Interpolates a sampling signal that meets the synchronization conditions, so that it has a nearly synchronous sampling result. The following briefly describes the working principle of general interpolation filters. Assume that the sampling signal generated by the sampler 2 is x (mxTs), where Ts is the fixed sampling period of the sampler 2, and m = 0 5l, 2, ... The round-out signal generated after this sampling signal passes through the interpolation filter can be expressed as this sampling

Page 5 423215 V. Description of the invention (3) The cyclotron integral value (c ο n v ο 1 u t i ο η) of the impulse response (impulse responsion) of the signal and interpolation filter. Assuming that the impulse response of the interpolated furnace wave device is h (u), where u represents continuous time, the output signal y (t) can be expressed as: y (t> = Σ x (m. Ts> h (t-m · Ts) ⑴ If Ti represents the sampling period synchronized with the symbol rate, the formula (1) can be transformed into: y (n-^) = ^ 1 Ts) h (n ^-m · Ts) (2) m

According to formula (2), it can be found that the function of this interpolation filter is to convert a fixed sampling input sampling signal (represented by x (mxTs)) 'into an output sampling signal (aWnXTi) that is synchronized with the symbol rate of the input digital data. ) Means). In the practical application of formula (2), 'the part about the impulse response will be further arranged: yin · = Σ x (m _ Ts > · h [(i + uj _ Ts] (3 > where i = int [n · / Ts]-m un = n ^ / Ts -mn = int [n ^ / ts] n = 0,1,2, ... In the above derivation process, we can know that as long as η XL cannot be detected by Ts Dividing, then Un will be a decimal. The output sampling signal y (η X) can be sorted into y [(un + nin) xTs], which means that the output sampling signal is equivalent to being shifted by the input sampling signal (Ts is the sampling period). Partial sampling period (un is decimal)

Page 6 4 23 21 5 V. Invention description (4) or interpolation. Figure 3 shows the timing diagram of the time relationship between the round-robin sampling signal (sampling cycle is Ts) and the output sampling signal (sampling cycle is). This relationship is also shown. Among them, un is an important parameter in the above derivation, which determines the result of interpolation. In the general system, ’un is obtained by the feedback mechanism. This part can refer to Floyd M. Gardner, " Interpolation in Digital

Modems-Part I: Fundamentals, IEEE Transactions on Communications, vol, 41, No. 3, Mar. 1993, PP · 5 (U-5 07. In the foregoing description, the parameter Un may be a decimal of arbitrary accuracy 'but the When the digital circuit is implemented, it must be quantized, that is, the process of converting floating point numbers to a fixed number of decimals (floating p0int to fixed point). This quantization process can divide a% of the original sampling period.

For N equal parts', each equal number corresponds to an integer value of 0 ~. In other words, if the sampling period Ts is regarded as 3 6 0. , The parameter representing the interpolation message 1 ^ represents the phase information in the sampling period, that is, \ X

The resolution of Ts is 360. / N. At present, interpolation filters are mainly implemented in two ways. The main difference between the two is that the coefficients are generated in different ways. As for the other architectures, they are related, such as the use of multipliers and adders to implement cyclotron integration and the use of temporary storage. Register (regUter) to store the input sample signal and filter pulses to be processed, :) the impulse response coefficient. The first method of β is to use a polynomial to synthesize the impulse response waveform of the proximity filter, for example, US Patent 5,878,088. The second method is to directly store the required wave shape parameters in special mode. In the hidden body, for example, directly burned into the read-only memory (Κ⑽)

Page 7 4 23 215 V. Description of the invention (5) — Or load it into random access memory (RAM) at boot time, and then use the appropriate address information of the memory to take out the information needed to calculate the round integral. Coefficient parameter. Fig. 4 shows a block diagram of the conventional implementation of an interpolator-wavelength filter using read-only memory, in which an 8-node (taps) filter is used as an example. In the figure, '201a to 201h' indicate input registers, which are used to temporarily store input sampling signals. 2 03a ~ 2 0 3h indicates the coefficient register, which is used to temporarily store the impulse response coefficient of the filter. 205a ~ 205h represent multipliers, which are used to calculate the product of the corresponding input sampling signal and filter coefficients. 2 07 means read-only memory. According to a location address message, a corresponding coefficient is provided to each coefficient register 2 0 3 a to 2 0 3 h. 2 0 9 indicates that the adder 'is used to add the product results of the multipliers (205a to 205h)' to generate a corresponding output sampling signal f. The multiplication and addition operations of the above sub-items correspond to the round-robin integration of the input sampling signal and the filter coefficients, thereby calculating the output sampling signal. For example, U.S. Patent Nos. 5,793,818 ', 5,309,484, 5,500,874, 5,612,975, 550,478, 5,587,088,88 all implement interpolation filters in a manner similar to Figure 4. These interpolation filters mainly store all coefficients directly in the read-only memory. When calculating the corresponding convolution integrals, the corresponding coefficient values are indexed through the address for calculation. On the other hand, when digital data is generated using two-dimensional modulation (quadrature modulation), such as qaM or QPSK, Y is more complicated to process. Since the signal of the two-dimensional modulated digital data exists in a two-dimensional vector, that is, it includes the I channel component and the q channel component, the earliest processing system used two sets of samplers to process the I channel component and the q channel component, respectively. However, because the two sets of samplers are relatively expensive to produce,

Page 8 423215 V. Description of the invention (6) Most of the practice uses only a set of samplers for sampling, and then uses the signal selector to select the sampling value part that belongs to the I channel component or the Q channel component from the sampling order 6. Figure 5 shows the signal timing diagram when using a single sampler and signal selector to process 2D modulated digital data. A, B, c, D, E,

F, G, and Η indicate the continuous sampling points obtained by the 甴 sampler (sampling cycle is TSAM) 'where sampling points a, c, Ε, and G are assigned to the I channel, and sampling points B, D, F, and Η are assigned To the q channel. In this case, the sampling points on the I and q channels are not aligned at the same time point. In general practical applications, the sampling points of the I and Q channels will be aligned in time for subsequent processing. Figure 6 shows a block diagram of a system used to adjust the misaligned sampling points of the I and Q channels in the conventional technology. . The input sampling signal of I channel and the input sampling signal of Q channel are similar to the signal shown in Figure 5. The sampling point interval in each channel is 2Tsam. in! The processing unit in the channel includes a delayer 21, a delayer 22, and an interpolation filter 20. The delay times of the delayers 21 and 22 are both f TSAM, that is, each sample point is delayed by I, and the interpolation filter 20 is used to generate a 1-channel output sampling signal consistent with the symbol rate. The processing unit in the Q channel includes a phase shift filter 31 and an interpolation filter 30. The phase shift filter 31 is used to cause the sampling point on the Q channel to generate a phase shift of Tsam, which is equivalent to the midpoint between two adjacent sampling points. For example, at the midpoint of sampling point B, you can use the average of the sampling values at the two sampling points to simulate. If you need more accurate simulation, you can use more complex filters. The interpolation filter 30 is used to generate a Q-channel output sampling signal consistent with the symbol rate. So assign to [channel and Q

Page 9 42 3 21 5 V. Description of the invention (7) The sampling points of the channels can be consistent in time. There is still a point in the processing of the conventional asynchronous sampling. For example, the conventionally improved part using only noise tp will correspond to each phase quantity c, that is, all the coefficients of u χ τ 1 M y. The pulse balance of (ψϋη X fs) follows the read-only memory, and there is no 44 Μ gastric response coefficient for the entire stored modulation digital data. J cry =: two-dimensional, and the sampling point of the Q channel is at Consistent in time. This issue date; ^ Need to make = Tong Guang J out of an effective processing architecture ', which can reduce the amount of data stored in the read-only memory and eliminate the need for Jiang Ru. In the case of phase-shifting filters, the time points are consistent, thereby simplifying the design and reducing costs. In view of this, the main object of the present invention is to provide an interpolation filter implemented by a memory, which can not only reduce the amount of coefficient data in the memory, but also can be used for two-dimensionally modulated digital data. Without using a phase-shifting filter, the effect of time point consistency between 丨 _Q channels is achieved. According to the above purpose, the present invention provides a flash plug-in filter for receiving an input phase amount and an input sampling signal, and generating an output sampling signal having a different sampling period from the round-in sampling signal, corresponding to each phase. Based on a set of pulse-balance response coefficients of the interpolation filter, the output sampling signal is generated by using the impulse response coefficient 'corresponding to the input signal and the input phase amount; the interpolation filter includes a memory. To store the above-mentioned impulse response coefficients corresponding to the above-mentioned input phase quantities, and to store a set of impulse response coefficients for the first phase quantity and the first phase quantity that conform to the symmetry of the impulse response.

Page 10 423215 w V. Description of the invention (8)-In addition, in the above-mentioned memory, the first half of the phase corresponding to the above-mentioned impulse response symmetry 1 ′ stores the first half of the impulse response coefficient corresponding to the first phase ^ Part; the second phase amount corresponding to the symmetry of the impulse response is stored in the first half of the impulse response coefficient corresponding to the second phase amount. In addition, the above-mentioned interpolation filter further includes: a bit generator that sequentially generates a first address message and a second address message to the memory according to the input phase amount, and the first address message It is generated based on the input phase. The above-mentioned second address information is generated based on the complementary phase quantity that matches the symmetry of the impulse response with the above-mentioned input phase quantity. The memory outputs the first phase information corresponding to the above-mentioned input phase. The first half of the impulse response coefficient of the amount, the above-mentioned memory according to the second address message 'outputs the first half of the impulse response coefficient corresponding to the complementary phase amount; one round into the register group' for storing the above-mentioned input sampling signal; a multiplex The generator group is used to sequentially select the first and second parts of the input sampling signal from the input sampling signals in the above-mentioned register register; the multiplier counts J corresponding to the input phase amount. The first product value of the first half of the impulse response coefficient and the first part of the above-mentioned sampling signal, and calculating a value corresponding to the complementary phase amount The first half of the impulse response coefficient and the second product value of the above-mentioned in-sampling sample 15 ^ ^; and an adder for summing the above-mentioned product value 漦 ^ at and the second product value 'to generate the above-mentioned sample out In addition to the letter $, the above-mentioned interpolation filter can also process the input of two-dimensional modulation 'Xin Rui. Wherein, the above-mentioned input sampling signal includes a first component sampling signal

Page 11 V. Description of the invention (9) The number of phase components divided by the first component phase quantity of the number of the first sample generator and the number of the first sample generator signal is added to the phase quantity value of the sample signal to generate the second component phase. The volume is generated, and the pulse pulse is generated according to the above according to the above-mentioned bit volume; the message, the third sub-coefficient, and the second sub-sampling signal are generated according to the above-mentioned first component sub-phase amount, and are increased or decreased by a constant sampling period. The above-mentioned one-bit address signal generates the first; the above-mentioned second bit should be symmetrically described as the second component and the second component. The above-mentioned memory address information has two parts. The present invention also provides one-bit and one input sampling signal with the same sampling period. One output one component sampling signal and the pulse body of the stored multiple pulses, used to store interest and send the corresponding sub-address component sub-sampling # According to the above input first becomes a component corresponding to the above input according to the above, output The first partial coefficients of the complementary phase second address of the three-phase address information to the component phase-divided phase vector. An input phase-like signal does not include the address information of the first memory. According to the above number, the phase phase is entered. The above-mentioned second generation period generates information at the previous address and the third address one address information. Complementary phase separation and phase measurement are based on the interpolated amount of the two-component impulse response of the sampling number and the fourth number and the first type of interpolation number, and the product corresponds to the first component. The first device according to the two address information and the message system generates a pulse according to the phase quantity. The three-part filter of the first address signal, the wave generation has a number, the up-sampling signal coefficient, and the formula filter corresponds to the above. The phase quantity is the input information of the above component. The fourth digit is generated according to the above and the above. The above rush responds to a single address, the round coefficient and the device. The input number is the same as the above, and its root is the second. The component system is based on the above constant system sample signal and the root address information describes the first, first, and second symmetry information, and the response should be in the fourth round.

Page 12 4 23 21 5 City V. Description of the invention (10) The input phase amount described above generates a first component phase amount corresponding to the first component sampling signal and a second component phase amount corresponding to the second component sampling signal. As the address information of the memory, the _th component phase amount is generated according to the input phase amount, and the second component phase amount is generated according to the first component phase amount plus or minus a constant. The constant is the phase value corresponding to the sampling period of the input sampling signal in the first component sampling signal. The memory includes a first memory and a second memory having the same contents, which respectively correspond to the first component sampling signal and the second component sampling signal. In addition, a circuit may be included for delaying the second component sampling signal by a predetermined time. 1 Brief description of the drawings: In order to make the above-mentioned objects, features, and advantages of the present invention more obvious and easy, the following provides a preferred embodiment and the following detailed description in conjunction with the attached drawings: Figure 1 A block diagram of a receiving system using feedback synchronous sampling in the known technology. Fig. 2 is a block diagram showing a conventional receiving system using asynchronous sampling. FIG. 3 shows a timing diagram of the time relationship between the input sampling signal and the output sampling k number in the receiving system of asynchronous sampling. Fig. 4 shows a block diagram of an in-line filter implemented in a conventional technique using a read-only memory. Figure 5 shows the use of a single sampler to handle two-dimensional modulation in conventional techniques.

Page 13 V. Description of the invention (11) Timing chart for digital data. Fig. 6 shows a block diagram of adjusting the misaligned I-channel and Q-channel sampling points in the conventional technique. Fig. 7 shows a system block diagram of the interpolation filter in the embodiment of the present invention. Fig. 8 shows a typical impulse response waveform of a general interpolation filter and is a schematic diagram for explaining the waveform symmetry. Fig. 9 is a block diagram showing an interpolation filter according to the first embodiment of the present invention. FIG. 10 shows a timing diagram when a single sampler is used to process two-dimensional modulated digital data, and is used to explain the principle of how to adjust the time difference between the channel and the Q channel in the second embodiment of the present invention. Fig. 11 is a block diagram showing a Q-channel interpolation filter in the second embodiment of the present invention. Fig. 12 shows a detailed circuit diagram of the address generator in the second embodiment of the present invention. Explanation of symbols: 1 ~ analog processing part; 2 ~ sampler; 3 digital processing part; 4 ~ clock generator; 1b sampling clock signal; 10 ~ sampling timing signal; 201a-2〇lh, 203a-203h, 101a-101h, 105a-105d, 107a-107d, 113, 131a'131h, 135a-135d, 137a-137d, 143 ~ registers; 20 53-2 0 511, 109 & -109 (1, 13 9 &- 139 (1 ~ multiplier; 207, 120, 150 ~ read-only memory; 209, 111, 112, 115, 141, 142, 161 ~ adder; 21, 22 ~ delayer; 3 phase shift filter

4 23 215 V. Description of the invention (12); 20, 30, 100 ~ interpolation filter; 10 & -i03d, ιΐ7, i33a-i33d,: 63 ~ multiplexer; 165 ~ inverter Device; ΐ70 〇 channel information; 180, 18 Q channel address information. ° Example: The present invention mainly proposes an interpolation m architecture that can be applied to an asynchronous sampling system, which is mainly implemented by using a memory (especially a 'read-only memory') to store impulse response coefficients. However, in the conventional technology, not only the amount of coefficient data to be stored can be reduced, but also the phase-shifting wave wave does not need to be used when processing two-dimensional modulated digital data.

FIG. 7 is a system block diagram of the interpolation filter in the present invention. The interpolator 100 mainly receives the input sampling signal x (mTs), which is used to generate an output sampling signal synchronized with the symbol rate of the digital data. The other input is the phase quantity Φ ° In the present invention, the interpolation filter 100 uses the internal read-only memory to store coefficients, which is obtained from the read-only memory according to the input phase quantity Φ ' Find the corresponding filter impulse response coefficient 'and the input sampling signal x (mTs) for forced integration to produce the required output sampling signal y (nD. If between two input sampling values (sampling cycle is Ts) When quantized as N, the phase amount φ is in the range of 0 ~ (N 丨). The parameter N can be selected as the power of 2, such as 2 5 6 (= 28). In addition, the interpolation in the present invention This filter uses an 8-node filter as an example, so each phase amount φ corresponds to 8 filter coefficient values. However, it must be noted that the above-mentioned quantization division and the number of filter nodes are not used to limit the present invention. It can be adjusted according to the actual application.

4 23 215 V. Description of the invention (13) First embodiment: This embodiment mainly uses the characteristic of the filter impulse response waveform symmetry to reduce the number of coefficients that the read-only memory needs to store. At the same time, using this characteristic, it is also possible Reduces the multiplier needed to calculate the round integral. The waveform of a typical impulse response waveform of the non-interpolated filter in Figure 8 is shown in Figure 2. The impulse response of Figure 2 is symmetrical to the so-called waveform. The coefficient output when the interpolating wave filter 1 00 receives the phase amount Φ, that is, the value at the sampling points T1 to T8; In addition, when the received phase amount is

The value of the coefficient output when Q = 6_Φ) is the value marked at the sampling points S1 to S8. According to the symmetry of the impulse response waveform, it can be known that n = s8, the characteristic, the data stored in the read-only memory is actually ^ stores the corresponding 8 coefficients / uses the relative bit to compare to the heart of the state.) The symmetry of each phase in the body is obtained, so you can check the phase amount N_Φ (hereinafter referred to as the complementary phase amount). In the example, the purpose is corresponding = half. Although this implementation is halved, there are still others; the way of J is to store the data and only store the first N / 2 phase scenes. "'Decrement method, for example, it can also be a value, and the last N / 2 phase quantities can be 17) The corresponding 8 coefficients @ Q 窗 I 1 can also be found by proportionality. The 9th chart is not based on the interpolation type constructed in this embodiment based on halving. Block diagram. In Figure 9, 10a ~ i〇ih Page 16 A2321 5 V. Description of the invention (14) represents the register used to store the input sampling signal. 103a ~ 103 (i is The multiplexer 'is used to take out the first 4 sampling values of the round-in sampling signal (stored in the temporary register and the last 4 sampling values (stored in the temporary register 101e ~ 101h) M05a ~ 105d is a register used to store the input sampling signals from the first half and the second half selected by the multiplexers 103a to 103d. 107a to 107d are used to store the coefficient values sent from the read-only memory uo 109a ~ 10 9d is a multiplier used to calculate the product value between the corresponding input sampling signal and the coefficient. 1 11 is an adder used to calculate Calculate the sum of product values output by multipliers 109a to 109d. 113 is a temporary register to temporarily store the first product value. 112 is an adder to calculate the sum of two product values. Read-only memory 120 is The impulse response coefficient 'used to store the interpolation filter ι〇〇 stores the first four coefficient values for each phase amount φ. 114 is an address generator, which includes an adder 115 and a multiplexer. The device 11 7 ′ is used to provide two addressing information to the read-only memory 丨 2 0. According to the foregoing description, in the read-only memory 120, each phase quantity φ only stores 4 corresponding coefficients, and the remaining 4 coefficients It must be found by the complementary phase amount N- Φ. Therefore, when the input is the phase amount ①, the address index must be used twice to obtain the complete coefficient value, once using the phase amount φ, and the other time using the complementary phase amount N -φ. Therefore, the calculation of the entire convolution integral must be performed in two steps. In the first calculation step, the multiplexer 117 selects the phase amount φ as the addressing message and sends it to the quasi-read memory 1 2 0. Read-only Memory 丨 2 〇 will correspond to The 4 coefficients are sent and stored in the temporary register. 丨 ο. 〇7d. On the other hand,

4 2 3 215 V. Description of the invention (15) The multiplexers 103a ~ 103d choose to store the pre-sampled values in the temporary registers 10la ~ 10ld and send them to the temporary registers 105a ~ 105d. It must be noted that, in order to obtain the same transmission time of the coefficients and sample values, in practice the registers 105a to 105d may include one or more d-type flip-flops. Calculate the product of the first 4 input samples = ^ / delay registers 105a ~ 105d) and the corresponding 4 coefficients (stored in the temporary registers 107a ~ 107d), and the product value is sent to the adder ln to calculate ^ After the first product sum value is obtained, it is stored in the temporary register i 丨 3. In the second calculation step, the multiplexer 117 selects the complementary phase amount N-Φ obtained by the addition as an addressing message and sends it to the read-only memory °° 120. The read-only memory 120 sends the ^ ^ number corresponding to the complementary phase amount ① to the registers 107a to 107d, which is equal to the latter coefficient corresponding to the phase amount ①, but the order is reversed. On the other hand, the multiplexers 103 & 103 (1 is selected to be stored in the temporary register 1016 ~ 101 [1 value 'and sent to the temporary register. Similarly, the order is also ^^, The poly = method 109a ~ 109d calculates the product of the four input sample values (stored in the registers 105a ~ 105d) and the corresponding four coefficients (stored in the register ~ 4! ° Jd), and Send the product values to the adder 111, respectively: 2 ί The sum of the second product. Finally, the sum of the first product and the corresponding sample value in the first. Add to produce the output sample signal. Interpolation filtering in this embodiment The advantages of the device are: The amount of coefficient data stored in the read-only memory is halved, which reduces the memory

Page 18 4 23 21 5 V. Description of the invention (16) " ---- (2) Multiplier and adder required for performing the spin integral half, reducing component cost. ° Subtraction must be explained, because in this embodiment, 4 coefficients are stored for each phase, it is necessary to perform two memory $ 77 fetches, but if you change the read-only memory 1 2 〇 The data storage method f is also widely used under the condition of halving the amount of coefficient data ', which can be completed with only one calculation *, convolution integral operation; for example, only storing the phase amount φ in the read-only memory is interesting ^ (N / Part of 2-l) 'but the complete coefficients are stored for each phase quantity. The input phase amount φ can be less than or greater than N / 2, and all coefficient values can be taken out. =

Second embodiment: In this embodiment, in addition to using the symmetry of the impulse response waveform to halve the amount of coefficient data that needs to be stored, it further takes the case of two-dimensionally modulating digital data but using only a single sampler for sampling. The coefficient data structure of the volume is processed without using a phase shift filter. :) Refer to Figure 10, which shows the timing diagram of sampling with a single sampler, sampling period for TSAM, and allocating the sampled values to the I and Q channels. Among them, sampling points A, C, and E belong to the I channel, and sampling points B, D, and F belong to the Q channel. The time interval between adjacent sampling points in the same channel is 2TSAM. Therefore, if an interpolation filter is used to make the internal difference between two consecutive points in a channel, the total phase amount of 360 ° is equal to 2TSAM. In other words, the phase amount Φ between adjacent points of actual sampling (for example, sampling points A and B) is equal to N / 2. In this embodiment, the time alignment between the I channel and the Q channel is mainly combined in an interpolation filter and processed together. In other words ’is to use different bits

Page 19 ^^ 321 5 V. Description of the invention (17) Address index information to process the sampling points of I channel and Q channel 'In this embodiment, the phase amount used by I channel for interpolation filter processing Φ Add or subtract a constant 'to generate the amount of phase used by the Q channel for interpolation filter processing. The working principle is explained below. Μ Assuming that the system decides that the output point X is the new sampling point required, the phase amount φ i between the input point X and the sampling point C of the interpolation filter Is of the I channel, that is, how much correction is made to the sampling point C A new sample value can then be generated at point X. It can be seen from the figure that the phase amount is smaller than N / 2, and the new sample value at the point X is generated by using the sample values at the sampling point C and the sampling point E as the phase difference. If a new sampling value is to be generated at point X on the Q channel, the internal difference between sampling point B and sampling point D must be used. At this time, the phase amount to be shaken is φ + N / 2. On the other hand, suppose that the system decides that the point γ is the required new sampling point, which is slightly different from the case of the point X. At this time, the phase amount φ2 between the input point Υ and the sampling point c for the interpolation filter of the I channel is larger than N / 2. The new sampling value at point γ is generated by using the sampling value at sampling point C and sampling point E as the internal difference of the phase amount Φ2, but to generate a new sampling value at point γ on the Q channel, you must use the sampling point. D and the sampling point Φ perform an internal difference, and the phase amount used at this time is φ-N / 2. In summary, the system uses the feedback mechanism to determine the phase amount φ 'corresponding to the I-channel interpolation filter, and according to whether this phase amount φ is less than N / 2', it is possible to determine the phase corresponding to the Q-channel interpolation filter. The phase amount is φ + Ν / 2 or Φ-ν / 2 'the new sampling points generated by interpolation on the I channel and the Q channel' can be consistent at the time point.

Page 20 423215 V. Description of the invention (18) Dou Songsong a If this IQ channel is processed ^ combined with the description in the first embodiment, the following can be summarized: (two: the conditions ... (1) similarities In the case of X, its / 2 is calculated for the first time: Μ! Channel: Interpolate with points C and E using phase ❹ Q channel: Interpolate with phase 耋 Φ + Ν'2 'Use points B and D for the second time Calculate φ, use points C and E to interpolate I channel: use phase real τ small, χτ. / Good (N—φ) -N / 2 ′ use points B, P to enter the channel: use phase 徂 m m pass Interpolation Φ 2N / 2 (2) Cases similar to point Y First calculation: Channel I: Use phase amount Φ N1 Interpolate with points C and E E Channel: Use phase 耋 Φ —N / 2, use point D Interpolate with F and ^ ^ ^ ^ f; NI #, J ^. E ^ ^ (3 channels: use phase 耋 (N) + N / 2 'interpolate with points D and F. The following describes its implementation. Medium The sampling values of the 1 channel and the Q channel are sent to the corresponding wave filter. The basic structure of the 1-channel interpolation filter and the 9th item: "'No further description here. Figure 11 shows this implementation In the example The block diagram of the conventional two-wave generator, in which the address generator 1β〇 for the I-channel and Q-channel interpolating wave generator 3, in Figure 11. In Figure 11, 131a ~ 131h are used to store Q 疋, use Enter _ now

Page 21 423215 V. Description of the invention (19) Register for sampling signals. 133a to 133d are multiplexers, which are used to take out the four sampling values of the input sampling signal of the Q channel twice in one cycle integral calculation. Referring to the aforementioned condition I, for different cases where the phase amount φ of the I channel is less than or greater than N / 2, the sampling points for the Q channel interpolation are different. Therefore, the multiplexers 133a to 133d are 4: 1 multiplexers, and the positions of the sampling points to be interpolated must be adjusted according to the comparison result between the phase quantities φ and N / 2, that is, the q channel can be selectively selected. The sampled value is delayed by Qiao Na time (the sampled value is taken out in a register in the q channel, which corresponds to 2). In addition, this group of multiplexers in the I-channel portion need only use a 2: 1 multiplexer, and its structure is the same as that in the first embodiment. 1 35a ~ 35d is a register for storing the input sampling signals selected from the multiplexers 133a ~ 133d. 137a ~ 137d are temporary registers used to store the coefficients sent from the read-only memory 150. 139a to 139d are multipliers, which are used to calculate the product value β 1 4 1 between the corresponding input sampled signal and the coefficient, which are adders' used to calculate the sum of the multiplied output values written by 139a to 139d. 143 is a temporary register for temporarily storing the sum of the first product. i 42 is an adder that calculates the sum of two multiplications and sums. ~ The read-only memory 1 50 is used to store the impulse response coefficient values of the interpolation filter, and the first 4 coefficient values are stored for each phase amount. In the embodiment, the read-only memory 150 can provide & j channel and Q pass first-line access at the same time, or two read-only memory modules with the same content can be used. Q channel for access. The advantage of the latter is that it can be processed at one time, and II can speed up the processing speed, but the coefficient data required for the two is doubled compared with the former.丨 60 is the address generator.

4 23 21 5) _ V. Description of the invention (20) In the embodiment, the I-channel address information and Q-channel address information of the read-only memory 150 can be generated according to the phase amount Φ in turn. In Fig. 11, a little explanation is needed for the address generator 160. Except for the multiplexers 133a to 133d, the sampling point on the Q channel can be selectively delayed by 2TSAM. The rest of the operations are basically the same as in the first embodiment. . The address generator 160 can be directly implemented by using the foregoing condition I. That is, the address information of the I channel can be directly generated using the phase quantity Φ and the complementary phase quantity N-φ; the address information of the Q channel is based on the phase quantity Φ less than or greater than N / 2 and the number of different steps. Add the address information of I channel to N / 2 or subtract N / 2 to generate. In fact, the above-mentioned condition I can be simplified into a form that is easier to implement. Let the phase amount used by the I channel be Θ '0, which may be Φ or N- Φ. According to whether 0 is less than N / 2, the following conditions can be summarized (hereinafter referred to as condition II): (1) When 6KN / 2, the phase quantity of the Q channel is 0 + N / 2 (2) When 0 2N / 2, then The phase amount of the Q channel is Θ-N / 2. In this embodiment, the address generator i 6 0 is mainly implemented according to the condition 11. FIG. 12 shows a detailed circuit diagram of the address generator 16 in this embodiment. As shown in the figure, the address generator 160 includes an adder 161, a multiplexer 163, and an inverter 165. In addition, '1 7 〇 means I channel address information; 1 0 0 ~ 1 8 1 means Q channel address information', where 180 is the first to the (7 in this embodiment) bits, and 1 81 is 10 g2N (8 in this embodiment) bits. First, the generation method of the I-channel address information 170 will be described. With reference to the aforementioned condition I ′, it can be known that in the first calculation step, the address information of the i-channel 丨 7〇, etc.

Page 23

5. Description of the invention (21) The input phase amount φ; in the second calculation step, the I channel address information 1 70 is equal to the complementary phase amount Φ. The adder 161 and the multiplexer 63 are used to directly generate the address information of the I channel 170. The adder 161 generates a complementary phase amount N- φ and turns it into the multiplexer 163 together with the phase amount Φ. In the first calculation step and the second calculation step, the multiplexer 163 selects the phase amount F and the complementary phase amount N-Φ as the address information of the I channel 1 70 respectively. The generation of the Q channel address information (180, 1 81) is based on condition II. In the condition I I, only considering the channel address information 1 70 (indicated by Θ, which may be Φ or N-Φ), the Q channel address information can be determined. The implementation of the condition 丨 can be achieved by directly inverting the most significant bit ’MSB of Θ. When 0 is less than N / 2, the most significant bit of Θ is " 0 '' 'At this time, Θ needs to be added to N / 2 to obtain the Q channel address information, that is, the most significant bit of β is changed to "1" , But the other bits are not changed. On the other hand, when 0 is greater than N / 2, the highest bit of 0 is " 1 ". At this time, it is necessary to subtract Θ / 2 to obtain the Q channel address information. It is to change the highest bit of θ to " (T 'and the other bits are unchanged. In other words, whether the right is greater than or less than N / 2', just invert the highest bit of θ (ie, 181 in Figure 12) If the other bits remain unchanged (ie, 182 in Figure 12), you can get the complete Q channel address information. If Θ is equal to N / 2, it is a special case, which means that the two channels before and after the I channel address information are owed. 17〇 (respectively ① and N_φ) are both N / 2, and the corresponding Q channel address information (1 0 0, 1 8 1) is 0 and N, respectively. This part can be processed by other special processing circuits. The circuit in Figure 12 is used to implement the address generator 160, which is not only simpler in the circuit, but also the address information of the I channel and the Q channel. Almost at

Page 24 42 321 5 V. Description of the invention (22) m '--------- Calculated at the same time, so it can be obtained Finally, it must be explained that this embodiment = performance. Information

Position-constant The phase-shift filter used in the conventional technique has the advantage of the value Η I-and the state. Although the present invention defines the present invention with a preferred implementation, any person skilled in the art is the same as above, but it is not intended to be used within the scope and scope of 'a few more,' without departing from the spirit of the present invention. When the attached patent application is regarded as attached, the processing technology of DI according to the definition of the protection scope of the present invention is the same as the reduction in the first embodiment, although the 1-Q channel can be implemented separately in combination. That is, regardless of the technology of 谵 _, but both are half, as long as the Q channel sampling points are selectively called whether the coefficient in the body is reduced by interest, the channel address information is added; ^ „^ Extend € and let ^ The phase shift filter used in the channel address knowing technology =: can also be removed

Claims (1)

: 23 ... S9 VI. _ Please patent scope 1 · An interpolation filter 'receives an input phase amount and an input sampling signal to generate two rounds of sampling signals with different sampling periods from the input sampling signal' Each input phase quantity corresponds to a set of impulse response coefficients of the above-mentioned interpolation wavelet, and the above-mentioned input sampling signal and the above-mentioned impulse response coefficient corresponding to the above-mentioned input phase quantity are used to generate the above-mentioned output sampling signal; the above-mentioned interpolation filtering The device includes a memory for storing the above-mentioned impulse response coefficients corresponding to the above-mentioned input phase quantities, and for a first phase quantity and a second phase quantity that conform to the symmetry of the impulse response, a set of impulse response coefficients is stored. 2 ^ The interpolation filter as described in item 1 of the scope of patent application, wherein in the memory, the ^ fth amount corresponding to the symmetry of the impulse response is stored corresponding to the first phase amount. The half of the impulse response coefficient; the half of the impulse response coefficient corresponding to the second phase amount is stored in the second phase corresponding to the symmetry of the impulse response. 3 · The interpolation filter according to item 2 of the scope of patent application, wherein the interpolation filter further includes: an address generator, which sequentially generates the first address information and the second address according to the input phase amount. The address information to the memory, the first address information is generated according to the input phase amount, and the second address signal is not.) According to the complementary phase amount corresponding to the pulse response symmetry with the input phase amount, The first half of the impulse response coefficient corresponding to the input phase is output according to the first address information, and the memory outputs the impulse response coefficient corresponding to the complementary phase amount according to the second address address. Page 26 4-23 215 6. Half of the scope of patent application; an input register group 'for storing the above-mentioned input sampling signal; a multiplexer group' for sampling from the above input in the above-mentioned input register group In the signal, 'the first part and the second part of the above-mentioned input sampling signal are sequentially selected; a multiplier' calculates the first product value of the first half of the impulse response coefficient corresponding to the above-mentioned input phase amount and the first part of the above-mentioned input sampling signal, respectively. 'And calculating a second product value of the first half of the impulse response coefficient corresponding to the complementary phase amount and the second part of the input sampling signal; and An adder is used for summing the first product value and the second product value 'to generate the output sampling signal. 4 · The interpolation filter as described in item 3 of the scope of patent application, which further includes: a first register group, placed between the multiplexer group and the multiplier, to temporarily store the multiplier The first part and the second part of the above-mentioned input sampling signal outputted by the worker; and a first register group, which is placed between the memory and the multiplier 'to temporarily store the impulse response output from the memory coefficient. 5 · The interpolation filter according to item 1 of the scope of the patent application, wherein the above-mentioned input sampling signal includes a first component sampling signal and a second component sampling signal. The generator generates a first component phase amount corresponding to the first component sampling signal and a second component corresponding to the second component sampling signal according to the input phase amount. 4 2 3 215. From the scope of patent application Phase ‘The first component phase is only measured by you according to the input phase’ The second component phase is generated by adding or subtracting a constant from the first component phase. κ 6. The interpolation filter as described in item 5 of the scope of the patent application, wherein the constant is a phase value corresponding to the round-robin sampling based on the sampling period in the first component sampling signal. 7 'The interpolation filter as described in item 6 of the scope of the patent application, in the upper j memory, the first phase quantity corresponding to the symmetry of the impulse response is stored, and the pulse corresponding to the first phase quantity is stored. The first half of the response coefficient; the second phase quantity corresponding to the symmetry of the impulse response corresponds to the first half of the impulse response coefficient corresponding to the second phase quantity. The above-mentioned first-position mass-produced body; the above-mentioned first response to the above-mentioned second-born; the third-digit, first, such as the patent application scope item 7 address generator 'which is based on the input address information and the second The third address information and the fourth address information of the fourth address are generated based on the two address information. The two component phase quantities are generated according to the complementary phase quantities with the above. The upper component phase quantities are in accordance with the pulse response memory. According to the two-part coefficients of the first address information and the fourth address information, and the above-mentioned first points of the interpolation described in the third part, and the address information mentioned above is the first, and the above-mentioned fourth addresses should be symmetrical. The output coefficients and the third information are based on the first component of the first round of information. The fourth part of the corresponding filter quantity phase is described in the second out to the top. Phase two address coefficient of the first part, in which the quantity generating component and the phase memory are generated. The combined pulse is based on the data and the mass production information and the system. Page 28 4 ^ 3215, patent application scope 9 The interpolation filter as described in item 8 of the patent application scope, wherein the memory includes a first memory and a second memory having the same content, and the first memory is used for Receiving the first address information and the second address information, and outputting the corresponding first partial coefficient and the second partial coefficient; the second memory is used to receive the third address message and the fourth address The message 'output corresponds to the above-mentioned third-part coefficient and the above-mentioned fourth-part coefficient. 10. The interpolation filter according to item 8 of the scope of the patent application, which further includes: an input register group for storing the above-mentioned round-sampling signal, and a multiplexer group for receiving from the above Among the above input sampling signals in the input register group, 'the first part sampling signal, the second part sampling signal, the third part sampling signal, and the fourth part sampling signal are sequentially selected; a multiplier' calculates the first part coefficients and A first product value of the first partial sample signal, a second product value of the second partial coefficient, and a second product value of the second partial sample signal, a third product value of the second partial coefficient, and the third partial sample signal, the first The fourth product coefficient and the fourth product value of the fourth part of the sampled signal; and 'the γ ·· ν an adder' for summing the first product value and the second value to generate a first component corresponding to the first component The first round out of the sampling signal takes the pi number, and the third product value and the fourth product value are added up to produce a second output sampling signal that should be generated from the second component sampling signal. . Health pair 11. The interpolation filtering as described in item 10 of the patent application scope also includes: Page 29 4 23 215 Sixth, the scope of the application for a patent-the first-temporary storage room, used for the number, the second kind of signal; the first room, used for the second part of 12 · Enter one of the sampling period and enter the upper part of the temporary storage and 2. Temporarily store the upper and first internal signals, and output the sampler group, which is placed in the above-mentioned first part of the sampling signal sample number h, third in the multiplexer group and the multiplier of the multiplier. The partial sampling signal and the fourth partial sampling signal and the first-recorded address are the first component sampling information, which is generated by adding or subtracting a constant 13 · The above constant component sampling 14 * The above memory The message sending address generates the sub-sampling signal produced by the above-mentioned second number. If the application number is within the signal, such as applying for a body wrapper group, the memory three-part plug-in filter generates a signal *. The second component of the root signal is placed in the coefficient and the fourth wave generator output from the recorder, and is used to obtain the sampling signal from the input and the input, and store the impulse response of the complex pulse according to the first input. Phase phase amount, the amount of phase components of the first phase quantity based component system according to the students. Patent range The corresponding patent range for the above input is the above-mentioned first and second partial coefficients of the memory and the multiplier. Receiving an input phase quantity and an input sampling signal with different sampling cycles 4¾ said that it includes a first component which includes: a response coefficient, and according to the connection coefficient; and a phase quantity 'produced corresponding to the upper quantity and corresponding to the second as the above The address of the memory is based on the input component, the first component phase quantity, and the phase filter of the sampling signal entered in item 12 of item 12. The interpolation filter described in item 12, whose sampling period is The above-mentioned interpolation filter of the first tenth, a memory and a second memory Page 30 4 2 321 5 v 6. The scope of the patent application corresponds to the above-mentioned first component sampling signal and the above-mentioned second component sampling signal, respectively. 15. The interpolator as described in item 12 of the scope of patent application, which further includes a circuit for delaying the second component sampling signal by a predetermined time. Page 31