JPH04318782A - Continuous variable time axis compression and expansion circuit - Google Patents

Abstract

PURPOSE:To attain time axis conversion while a sampling frequency of an output is unchanged from that of an input by using employing a buffer memory to convert the time axis and a sampling frequency converter using a time change coefficient filter. CONSTITUTION:An input signal is a data (indicated in black dots) sampled by a sine wave fs as shown in figure 2-a. The data is inputted to a buffer memory 1 at the sampling frequency fs and read at a sampling frequency fs' slower than the frequency fs. As a result, the time axis is expanded and the data is converted into a sinusoidal wave data string as shown in figure 2-b. Since the frequency fs' is not in the relation of an integral number with the frequency fs, no data among the data subject to time expansion is in existence at an output sampling point of time. Thus, data (indicated in white dots) on a point of time of the sampling of the frequency fs are interpolated by a frequency multiplier circuit 2 from the data (indicated in black dots) subject to time axis expansion to obtain an output data. Thus, the continuous variable time axis compression expansion circuit is realized, in which an optional time axis conversion ratio is compressed/expanded.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a time axis compression and decompression circuit, and particularly to a digital signal processing device.
This invention relates to a continuously variable time axis compression/expansion circuit that can continuously vary the time axis conversion ratio of a signal.

0002

2. Description of the Related Art Since digital signal processing involves sampling, the time axis can be easily compressed and expanded by changing the sampling time interval. Therefore, information compression and signal multiplexing systems that apply this time axis compression and expansion are often used. By the way, time axis compression/expansion is basically the same operation as sampling frequency conversion; time axis compression involves sampling frequency reduction (thinning), and time axis expansion involves sampling frequency multiplication (interpolation).
This is signal processing equivalent to

Conventionally, in this conversion of sampling frequencies, the ratio of sampling frequencies has often been selected to be a power of 2 for ease of construction. If the sampling frequency ratio is not a simple integer ratio, the sampling frequency must be set to the least common multiple of the sampling frequencies before and after conversion, but this is generally a very high frequency and is not possible. There were many cases. The interpolation method described in Japanese Patent Application No. 15633/1980 is a method that performs this interpolation using a time-varying coefficient filter and makes it possible to convert the sampling frequency even when the ratio of the sampling frequencies is not a simple integer ratio. be.

0004

Problems to be Solved by the Invention When converting the sampling frequency necessary for time axis compression/expansion, signals other than desired signal components are generated. That is, according to the sampling theorem, a sampled signal has a signal spectrum in which frequency components up to 1/2 of the sampling frequency are folded back. Therefore, when the sampling frequency is increased, harmonics are generated, and when the sampling frequency is decreased, an aliasing phenomenon occurs. In the latter case, so-called aliasing distortion occurs that cannot be removed after converting the sampling frequency. Therefore, an aliasing removal filter is essential for sampling frequency conversion accompanying time axis compression/expansion.

[0005] Depending on the application, there may be cases where it is desired to continuously vary the time compression/expansion ratio. In such a case, the characteristics of the aliasing removal filter need to be continuously varied in accordance with the time conversion ratio.

The first object of the present invention is to provide a time compression/expansion circuit with a time conversion ratio that is not a simple integer ratio. A second object is to obtain a time compression/expansion circuit that can change the cutoff frequency of the aliasing removal filter in accordance with the setting of the time conversion ratio. A third object of the present invention is to provide a continuously variable time base compression/expansion circuit that can continuously change the time conversion ratio.

[0007]

Means for Solving the Problems In order to achieve the above object, a filter function is added to the interpolation method described in the prior art section and applied to a time axis compression/expansion circuit. First, the time-varying coefficient FIR described in the above-mentioned patent application No. 15633/1982
An interpolation method using a filter will be explained.

According to the sampling theorem, as shown in FIG. 4, from the data sequence f(nT1) (indicated by a black circle) sampled at period T1, the original time function f(t) is Sinc(t
)=sint/t using f(t)=f(nT)Sinc{π(t+n
T1)/T1}=Σf(nT1)Sc(n,τ)
(Equation 1) Here τ=t
/T1 is the fraction of output time t measured in T1 period, S
c(n, τ)=sin {π(τ+n)}/(τ+n). Equation 1 shows that when predicting the data value at time t by linear combination of discrete data fn=f(nT1), the coupling coefficient Sc(n
, τ) is a function of t. Time-varying coefficient α
n(τ) = Sc(n, τ) is Sinc(t
) and various other functions can be used.

When Equation 1 is approximated by a finite number of data N, the interpolated value f(t) is obtained as the output of an acyclic (FIR) filter with time-varying coefficients Sc(n, τ). This shows that interpolation (or sampling frequency conversion) can be implemented in hardware using a time-varying coefficient filter. The hardware configuration of the digital interpolator is shown in FIG. In FIG. 5, 511, . . . , 51N are delay elements, 52
0,521,~,52N are coefficient multipliers, 531,~,
53N is an adder, 54 is a ROM, 55 is a counter, 56
is a latch register. The delay element, coefficient multiplier, and adder constitute an FIR filter that operates at the input sampling frequency fs1.

The parameter τ that determines the time-varying coefficient Sc(n, τ) is determined by the data output time t given by the output sampling period T2=1/fs2, t=nT1+τ=mT2

(Math. 2) To obtain τ using hardware (see FIG. 5), the counter 7 that receives a clock pulse that is sufficiently faster than T1 must be reset at the T1 period, the counted value must be read out at the T2 period, and held in the latch register 56. This can be achieved with Time-varying coefficient Sc(
n, τ) is written in the ROM 54 in advance, read it out using the obtained τ, and supplies it to the coefficient multipliers 520, 521, . Ru. τ is the output time t given by the output sampling period
Since it is determined by and independent of the input sampling period,
It can be seen that the configuration shown in FIG. 5 provides an interpolation device in which the ratio of sampling frequencies can be set freely.

Next, a method of adding an aliasing removal filter function to an interpolation device using a time-varying coefficient filter will be explained. The time-varying coefficient Sc(n, τ) used in Equation 1 is also the impulse response of an ideal LPF with a cutoff frequency fs1/2. This interpolation device remains as it is and becomes an LPF with a cutoff frequency of fs1/2. Therefore, in the case of fs1<fs2, ie, sampling frequency multiplication, no aliasing removal filter is required. However, in the case of fs1>fs2 (sampling frequency decreasing), the output Nyquist frequency (
fs2/2), signals with higher frequency components are folded back and output. Therefore, by shifting the frequency fs1 of the interpolation function Sinc(x) to fs2, the cutoff frequency of the time-varying coefficient filter of the interpolator can be changed. That is, the aliasing removal filter can be realized by modifying the time-varying coefficients. Transforming Sinc(x)=sinx/x, x
=ω1t/2=πfs1(nT1+τ), fs
If 1=fs2*r (at the time of gradual decrease, r>1), then Sinc(x)=sin{π(n+τ)*r
}/{π(n+τ)*r}=Sc′(n, τ, r) (
Equation 3) is obtained. Here, x=π(n+τ)*r. The modified time-varying coefficient Sc'(n, τ, r) is given as a function of the coefficient tap order n, the interpolation time τ, and the sampling frequency ratio r.

FIG. 6 shows the hardware configuration of a digital interpolator with an added aliasing filter function. In FIG. 6, 610,~,61N-1,61N are coefficient multipliers, 621,~,62N are delay elements, and 631,~,63
N is an adder, 64 is a ROM, 65 is a counter, 66,6
7 is a latch register, and 68 is an adder/subtractor. The delay element, coefficient multiplier, and adder constitute an FIR filter that operates at the input sampling frequency fs1. However, it has a different format from the configuration shown in FIG. The circuit function is exactly the same for both types. Time-varying coefficient Sc′(n, τ, r
)=sampling frequency ratio r=fs1 that determines αn(τ, r)
To determine /fs2=T2/T1, T1 and T
2 (here, it is assumed that the input sampling period T1 is already known). In order to obtain T2, the difference between successive interpolation times τn and τn-1 is determined. From equation 2, the difference T
2' is T2'=τn-τn-1=T2-kT1

(Equation 4). In equation 4, k is an integer. Therefore, T2 can be obtained by adding the correction of T1 to the difference in interpolation time. Even if T2 fluctuates, the range of fluctuation is T
Since it is smaller than 1, this correction calculation can be easily performed. Figure 6
In the configuration example, τ obtained by the latch registers 66 and 67
n and τn-1 are input to the adder/subtractor 68 to find the difference T2'. Input this to ROM64, and in ROM64, T2'
and the calculation of r=T1/T2. As a result, the sampling frequency ratio r is obtained, and the time-varying coefficient αn(
τ, r) can be determined.

As explained above, FI with time-varying coefficients
It has been found that by using an R filter and slightly modifying its coefficients, it is possible to perform sampling frequency conversion and filter processing with one circuit configuration. By applying this, a continuously variable time axis compression/expansion circuit can be easily configured.

The time-base compression/expansion circuit can be realized by using the above-mentioned digital interpolator and buffer memory. Two configurations are possible depending on how the interpolator and memory are combined. First, from an input data string fn (t=nT) with a sampling period T, compression and decompression time t'=nT'
Interpolate the data values at with an interpolator. Next, time is moved to the original sampling time t in the buffer memory. In the second method, the input data string is moved in time to the compression/expansion time, and then the data at the sampling time is obtained by interpolation. In either method, if the interpolator is used as a multiplier, time will be expanded, and if a step-down operation is performed, time can be compressed.

[0015]

[Operation] By the method described above, the sampling frequency conversion ratio (or time axis compression/expansion ratio) can be set to any ratio other than a power of 2. This method can also continuously vary the time compression/expansion ratio. In either case, the digital interpolator itself has an aliasing removal filter function, and the cutoff frequency of the aliasing removal filter changes depending on the time axis compression/expansion ratio, so there is no need to prepare a variable characteristic filter.

[0016] When reproducing the original signal, on the receiving side,
The process is the opposite of that on the transmitting side, and the time compression/expansion ratio is either predetermined between the transmitter and receiver, or it is encoded and transmitted. for example,
By performing time compression on the transmitter side and time expansion on the receiver side, the information transmission speed can be reduced, and the information transmission speed can be reduced by multiplexing other information or using a transmission path with a narrow band. It can be used for. In addition, ATM (Asy
nchronous TransmissionMod
e) It is possible to flexibly respond to transmission methods with changing transmission speeds, such as transmission.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of a time base expansion circuit according to the present invention. In FIG. 1, 1 is a buffer memory, and 2 is a sampling frequency multiplier circuit. The operation of the embodiment shown in FIG. 1 will be explained with reference to the operation signal waveform diagram shown in FIG. The input signal is 2
−a is sampled data (represented by black dots) at fs. This is input into buffer memory 1 at sampling frequency fs, and sampling frequency fs' slower than fs
Read it with . The time axis is stretched and converted into a data string representing a sine wave as shown in 2-b. However, fs
' is not in an integer ratio relationship with fs, so the time-expanded data has no data at the output sampling point (an integer multiple of fs-1). Therefore, from the time axis expanded data (black dots), the data at the fs sample time point (white dots) is transferred to the frequency multiplier circuit 2.
Interpolate with and obtain output data. As the sampling frequency multiplication circuit, the digital interpolator shown in FIG. 5 can be used. The time-varying coefficient FIR filter portion in FIG. 5 may be configured as shown in FIG. 6.

FIG. 3 shows another embodiment of the time base expansion circuit according to the present invention. In FIG. 3, 3 is a sampling frequency multiplier circuit, and 4 is a buffer memory. The input data string is input to the sampling frequency multiplier circuit 3 at the sampling frequency fs,
It is converted to a sampling frequency fs' which is faster than fs. The time stretching ratio is fs'/fs. The data string interpolated by the sampling frequency multiplier 3 is input to the buffer memory 4 and read out at the original sampling frequency fs. In this way, a data string is obtained in which the time of the interpolated data is extended and the sampling frequency is fs.

FIG. 7 shows an embodiment of a time base compression circuit according to the present invention. In FIG. 7, 5 is a sampling frequency reduction circuit, and 6 is a buffer memory. The operation of the embodiment shown in FIG. 7 will be explained with reference to the operation signal waveform diagram shown in FIG. As an example of the input signal, data (represented by black dots) obtained by sampling a sine wave at fs as shown in 8-a will be used. This is input to the sampling frequency reduction circuit 5, and data with a sampling frequency fs' slower than fs is interpolated (white circle). The time compression ratio is fs'/fs. When the interpolated data is input to the buffer memory 6 and read out at the original sampling frequency fs, time axis compression is performed and converted into a data string representing a sine wave as shown in 8-b.

[0020] When performing time axis compression, the sampling frequency is gradually decreased, so the input signal contains frequency components higher than 1/2 of the sampling frequency (fs') after compression. This causes aliasing noise. Therefore, a low-pass filter is required to remove the aliasing component in advance. However, in the present invention, this processing is unnecessary because the sampling frequency reduction circuit 5 having an aliasing removal filter function is used. As the sampling frequency reduction circuit 5, the digital interpolator shown in FIG. 6 can be used. The time-varying coefficient FIR filter portion in FIG. 6 can also be configured as shown in FIG.

FIG. 9 shows another embodiment of the time base compression circuit according to the present invention. In FIG. 9, 7 is a buffer memory, 8
is a sampling frequency reduction circuit. The input data string is input to the buffer memory 7 at a sampling frequency fs, read out at a sampling frequency fs' faster than fs, and time-compressed. The time compression ratio is fs/fs'. In order to interpolate the data at the sampling frequency fs of the read data string,
The data string read from the memory is input to the sampling frequency reduction circuit 8, and the sampling frequency is converted to fs. In this way, time-compressed output data is obtained. Although the sampling frequency is decreased in this embodiment as well, as in the embodiment of FIG. 7, a digital interpolator having an aliasing removal filter function is used, so no separate filter is required.

As explained above, according to the present invention, the time axis of a sample value data sequence can be compressed and expanded to an arbitrary ratio. In conventional methods, when the time axis conversion ratio is not a power of 2, data interpolation becomes complicated and difficult to implement. In the present invention, sampling frequency conversion of arbitrary ratio is possible.
By employing a digital interpolator, it has become possible to compress and expand the time axis at any ratio. Furthermore, when performing time axis expansion, an aliasing removal filter is required, but since the digital interpolator has this filter function, there is no need to use a new filter.

Furthermore, the time axis compression/expansion circuit of the present invention:
The time axis conversion ratio can be changed continuously. In this case, the cutoff frequency of the aliasing filter is also changed accordingly.
This is automatically achieved by the digital interpolator used in the present invention, as described above.

[0024]

According to the present invention, a continuously variable time axis compression/expansion circuit capable of compression/expansion at an arbitrary time axis conversion ratio can be realized. It also has an aliasing removal filter function required with time axis compression, and its cutoff frequency automatically changes according to the setting of the time axis conversion ratio. Therefore, there is no need to newly provide a variable filter, and the configuration can be simplified. Furthermore, it can be applied to a multiplex transmission system using time axis compression/expansion, and it can also be applied to a transmission system that performs transmission using a transmission path with a narrow band or that varies the transmission speed.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of one embodiment of a time base expansion circuit according to the present invention.

FIG. 2 is an explanatory diagram of operation signal waveforms in the embodiment of FIG. 1;

FIG. 3 is a configuration diagram of a second embodiment of the present invention.

FIG. 4 is a diagram explaining the principle of a digital interpolator used in the present invention.

FIG. 5 is a configuration diagram of a digital interpolator.

FIG. 6 is another configuration diagram of the digital interpolator.

FIG. 7 is a configuration diagram of an embodiment of a time base compression circuit according to the present invention.

8 is an explanatory diagram of operation signal waveforms in the embodiment of FIG. 7; FIG.

FIG. 9 is a configuration diagram of a fourth embodiment of the present invention.

[Explanation of symbols]

1, 4, 6, 7...Buffer memory, 2, 3...Sampling frequency multiplication circuit, 5,8...Sampling frequency reduction circuit, 511,
~, 51N, 621, ~, 62N...delay element, 520,
521, ~, 52N, 610, ~, 61N-1, 61N
...Coefficient multiplier, 531, ~, 53N, 631, ~, 63
N... Adder, 54, 64... ROM, 55, 65... Counter, 56, 66, 67... Latch register, 68... Addition/subtraction device.

Claims (5)

[Claims] 1. An input data string with a sampling frequency fs is input to a buffer memory, read out at a sampling frequency fs' different from fs, subjected to time axis compression or expansion, and a sample is cascaded to a subsequent stage of the buffer memory. 1. A time axis compression and expansion circuit, which is a frequency conversion circuit that converts a sampling frequency into fs and outputs the converted signal. 2. A buffer memory which inputs an input data string at a sampling frequency fs to a sampling frequency conversion circuit and converts it to a sampling frequency fs' different from fs, and which is connected in cascade after the sampling frequency conversion circuit. 1. A time-base compression and expansion circuit, characterized in that it performs time-base compression or expansion by inputting data to the original sampling frequency fs and reading it out at the original sampling frequency fs. 3. In the time axis expansion circuit according to claim 1 and claim 2, the sampling frequency conversion circuit is controlled by a clock device which is periodically initialized at an input sampling frequency fs1 to obtain an output sampling frequency fs2. The input signal sequence sampled at the input sampling period is sampled at the output sampling frequency using a time-varying coefficient filter having a filter coefficient determined by the output sampling time. 1. A continuously variable time axis expansion circuit, characterized in that it uses a sampling frequency conversion circuit configured to convert into a recoded output signal sequence. 4. The time axis compression circuit according to claim 1 and claim 2, wherein the sampling frequency conversion circuit is controlled to have an output sampling frequency fs2 by a clock device which is periodically initialized at an input sampling frequency fs1. The time of the sampling pulse is measured, and the output sampling time and the ratio r=fs1 of the input sampling frequency fs1 and the output sampling frequency fs2 are calculated.
/fs2, and is configured to convert the input signal sequence sampled at the input sampling period into an output signal sequence sampled at the output sampling frequency using a time-varying coefficient filter having a filter coefficient determined by /fs2. A continuously variable time-base compression circuit characterized by using a sampling frequency conversion circuit. 5. A time base compression circuit and a time base expansion circuit according to claim 1 or 2, or a continuously variable time base expansion circuit according to claim 3 and a continuously variable time base compression circuit according to claim 4. 1. A continuously variable time base compression/expansion circuit comprising a circuit, and further comprising a time base conversion ratio of the compression circuit and the expansion circuit that is determined in advance, or a common time base conversion ratio control signal.