SU1467786A1 - Device for receiving discrete signals with low-ratio relative-phase manipulation - Google Patents

Description

The invention relates to telecommunications and can be used in a data transmission technique.

The purpose of the invention is to improve noise immunity under the conditions of pulsed and multiplicative interference.

FIG. Figures 1 and 2 depict the structural electrical circuit of the proposed device.

The device contains an automatic level controller 1, a band-pass filter 2, an analog-to-digital converter 3, a Hilbert digital converter 4, a clock synchronization unit 5, a first gate unit 6, a digital equalizer 7, a second gate block 8, a demodulator 9, a correlator 10, delay unit 11, decision block 12, decoder 13.

The device works as follows.

The received signal arrives at the input of the automatic controller of the I level, which ensures the normal functioning of the device for receiving discrete signals when the input signal level changes by +, 6 1 g dB relative to the nominal

value.

Next, the received signal is fed to the input of a band-pass filter 2 providing suppression of out-of-band additive noise. From the output of the bandpass filter 2, the signal is fed to the input of the analog-to-digital converter 3 and to the control input of the automatic level controller 1. The introduction of an automatic adjustment of the level of the received signal by the Los filter 2 into the adjustment circuit reduces the influence of the additive

O5

vl h |

00 05

noise on the transmission coefficient of the automatic controller 1 level.

From the output of the analog-to-digital converter 3, samples of the received signal, taken at a sampling frequency 6 times higher than the tracking frequency of single elements, are fed to the input of the Hilbert digital converter 4. The choice of the sampling frequency was determined by meeting the accuracy requirements for determining the derivative in the clock synchronization unit 5, the initial data for tuning of which is removed from the delay line of the digitizer of Hilbert 4. The purpose of the digitizer of Hilbert 4 is to form the square draturnoy component of the received signal in accordance with

jr x

by expression

BUT

 Z d

(one)

g de x „.

N

the sample of the received signal, taken from the k-ro removal of the delay line of the digital converter of Hilbert 4 on the nth unit interval k-coefficient of the impulse response of the digital converter of Hilbert 4, k -N, ..., - 1, 0,1, ... N, the total number of coefficients of the Hilbert digitizer 4.

The Hilbert 4 digital converter is a non-recursive digital filter with an skew-symmetric impulse response defined by an odd number of constant coefficients. It is implemented on the basis of a delay line with taps taken through one sixth unit interval T. A multiplier is connected to each branch of the delay line, providing the operation of multiplying the received signal by the coefficient of the impulse response of the Hilbert digital converter 4. Signals from the outputs of multipliers go to adders, which provide a calculation of the quadrature component of the received signal x in accordance with the expression (1). The in-phase component of the received signal is removed from the 0th retraction of the delay line and is fed to the first output of the Hilbert 4 digital converter. The quadratic component of the post

467786

goes to the second output of the Hilbert 4 digital converter. From the (-1) -th and 1st taps of the delay line, samples of the received signal are taken

five

0

five

Q j

x ". and x, which are fed to the third and fourth outputs of the Hilbert 4 digital converter and then used in block 5 of the clock synchronization.

The in-phase and square-wave components of the received signal count appear on the first and second outputs of a Hilbert digital converter.

5 4 through the interval T / 6 and enter the gating unit 6. The purpose of the building unit 6 is to puncture the sequence of samples of the received signal, which allows to ensure the interval of the following samples of the received signal at the input of the digital equalizer 7, equal to T / 2, Gating blocks 6 and 8 can be implemented on the basis of parallel registers, the recording signal information in which comes from the second and third outputs of the block 5 clock synchronization, respectively, for gating blocks 6 and 8.

Digital equalizer 7 is a non-recursive digital filter with constant complex coefficients. It is implemented on the basis of a delay line with taps taken at intervals of T / 2. The correction algorithm is described by the expression

about X "t, s

-ej

(2)

- complex reading of the received signal at the output of the digital compromise equalizer 7 on the nth unit

five

and e

+.

 hc

SLIM interval,

+

her

0

- complex counting of the received signal in the 1st branch of the delay line of corrector 7,

+

-complex coefficient of the impulse response of the digital equalizer 7,

-the total number of coefficients of the digital equalizer 7.

The coefficients of digital equalizer 7 are calculated by solving the Wiener-Hopf equation in a vector-matrix form with complex coefficients.

g with

Jces

L + 1

The choice of the sampling frequency of the received signal in the digital equalizer 7 in accordance with Kotelnikov's theorem assumes in this case the sampling of the signal at T / 2 intervals, which provides additional suppression of out-of-band additive noise and excludes the possibility of transforming phase-frequency and coefficients into amplitude-frequency ones with unsuccessful phase selection builds.

Since the received signal at the compromise correction stage is built with the sampling frequency, twice the tracking frequency of single elements, the corrected signal before being fed to the input of demodulator 9 is punctured with the frequency of tracking of single elements in the second building block 8. The control signal arrives in the strobe unit 8 from the third output of the unit 5 clock synchronization.

The corrected signal samples are received with a period equal to the unit interval T, to the input of demodulator 9, which carries the transfer of the received signal to the band of the equivalent low-frequency channel. The operation of the demodulator 9 is described by the equation

- (.)

“S“ e

(3)

where y is the complex sample of the demodulated signal on

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It has a significant effect on noise immunity, since the proposed device uses the optimal non-coherent reception method.

The demodulator 9 represents a multiplier of two complex signals, one of which is the reading of the corrected signal S ,, and the second is the time reference of the reference oscillation corresponding to it.

The reference oscillation samples are formed by a digital generator, which is part of the demodulator 9. 15 The digital reference oscillator can be made on the basis of a permanent storage device (ROM) of the required capacity, controlled by the address inputs with a cheater. 20 The read-out codes of the reference oscillation with the initial phase f, taken at a sampling frequency equal to the single-element tracking frequency, are stored in the ROM. The ROM volume and the counter conversion factor 25 are generally determined by the multiplicity of the unit frequency (clock frequency) and the frequency of the reference waveform. The change in the state 30 of the counter occurs in accordance with (3) once per single inte-hol.

Before deciding on the transmitted information symbols, the optimal incoherent algorithm for receiving 3g discrete signals with relative phase modulation involves calculating the following expression in the correlator 10:

nth unit interval;

initial phase incoherent 40

reference oscillation, the cyclic frequency of the reference oscillation is equal to the nominal value of the carrier frequency recommended by CCITT for a given information transfer rate.

In the proposed device, the demodulator 9 provides for the elimination at the receiving side of the non-information phase shift of the carrier oscillation for a single interval, resulting from the absence of frequency multiplicity of the carrier and clock oscillations. Differences in the frequencies and phases of the carrier and reference oscillations due to the non-synchronism and non-synchness of the respective generators, in this case not

,,

 I y „/ e,

/Y..../ e (4)

where v and

sh

lm - the absolute values of the phases 5 of the complex samples of the demo. dulirovanny signal at the n-th and (n-l) -M unit intervals;

/ u, / and 0 / U, -, /

five

demodulated signal sample modules, which, in the case of relatively phase modulation, are usually equal to one. Since, as follows from (4), the counting of the demodulated signal, obtained at the previous unit interval, participates in the block diagram of the receiving device

entered line n delay. Expression (4) implies the reduction of relativity introduced at the transmission. The absolute phase of the complex signal at the input of the decision block 12, under ideal conditions, corresponds to the information phase shift of the carrier oscillation and H, introduced at the transmission.

Decision unit 12 performs an item-by-element evaluation of information symbols in accordance with the equation

a .. mm;

{(Rei -a, .f +

+ (1t1 „- ES;)},

(five)

where a „

f- jSj is the estimate of the information symbol on the nth unit interval, and a and its in-phase and quadrature components, respectively,

min- II

a, - is a function equal to the information symbol a; + and the expression delivering the minimum value in curly brackets (5). It is obvious that the procedure for evaluating an information symbol consists in calculating the expression in curly brackets of equation (5) for all possible values of a a on each unit interval. ja and the choice of such a, which corresponds to the minimum value of the expression in brackets.

The decision block 1 2 contains adders and squaring schemes, connected in accordance with the expression in braces (5), as well as the comparison circuit, the counter, the first and second registers, and the ROM of the standards. In the standards ROM, the values of the in-phase and quadrature components of all information symbols are entered in pairs. The counter provides a sequential enumeration of all a- involved in the calculations by formula (5). The result of the calculation for each value of a enters the comparison circuit, where it is compared with the contents of the register and entered into it if the result of the calculation is less than the contents of the register. In parallel with updating the contents of the register, the contents of the counter are recorded in another register. If before the start of the implant

about

five

0

five

0 5

0 5 Q

the register is the maximum representable number, then after all the values of a are searched, the register will have the minimum value of the expression in curly brackets (5), and in the other register of the corresponding value of the reference information symbol a. it

17

the value is an estimate of the received information character a & a and is generated at the output of the standards ROM when the counter is loaded from another register. The score thus obtained for the information symbol &. pop

steps out of the ROM standards at the output of the decision block 12.

From the output of the decision block 12, the reference value of the received signal is fed to the decoder 13, where the information symbol is converted into a code in which information is transmitted to the consumer. The clock synchronization block 5 is designed to obtain an optimal estimate of the phase of the strobment moment of the received signal in analog - digital converter 3 and gating blocks 6 and 8. The optimality criterion is generally chosen as the maximum of the likelihood function of the received signal.

The clock synchronization unit 5 contains an adder, a CALCULATING sum of samples of the received signal taken from the 1st and (-1) taps of the delay line of the Hilbert 4 digital converter, a multiplier, the inputs of which receive the result of calculating the sum of samples and the counting component of the received signal (-x), a multiplier used to multiply the phase error values by a factor of "i", and an adder providing gaps of the moment of gating. The evaluation of the gating moment phase arrives at the control input of the controllable frequency divider connected to the master oscillator. The signals necessary for the synchronous operation of the analog-digital converter 3, the first 6 and second 8 gating devices are generated using dividers 3 and 2.

Claims (1)

Invention Formula A device for receiving discrete signals with a low-multiplicity relative-phase modulation, containing serially connected automatic level control, bandpass filter and analog-to-digital converter, as well as a demodulator, a decisive unit whose outputs are connected to the decoder inputs, characterized in that, in order to improve noise immunity under the influence of pulsed and multiplicative interference, Hilbert's digital converter, clock synchronization unit, correlator, delay unit and serially connected first gating unit, digital corrector and second gating unit, strip output Vågå filter is connected to the control input of the automatic level controller, output of the analog-digital converter - digital converter to the input Hilbert, the first and second outputs of which are connected to the inputs of the first gating unit, the outputs of the second gating unit are connected to the inputs of the demodulator, the outputs of which are connected to the inputs of the delay unit and the first and second inputs of the correlator, the third and fourth inputs of which are connected to the corresponding outputs of the delay unit , the outputs of the correlator are connected to the inputs of the decision block, the second, third and fourth outputs of the Hilbert digital converter are connected to the corresponding inputs of the clock synchronization block, The first, second and third outputs of which are connected respectively to the control inputs of the analog-digital converter, the first and second gates. Editor N. Dumbass Compiled by N. Lazarev Tehred L. Serdyukova Order 3108 Circulation 626 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab. 4/5 --- 1 - Production and Publishing Combine Patent, Uzhgorod, st. Gagarin, 101 cvj Proofreader L. Pilipenko Subscription