JPH01286509A - Timing generating circuit for digital filter - Google Patents

Abstract

PURPOSE:To always obtain an accurate digital value by stopping the count of a counter when a sample clock and an internal clock are asymmetrical or five clocks or over exist between shift clocks. CONSTITUTION:If an internal clock (A) and a sample clock (C) are asynchronous or if the relation of width of internal clock (A) X 4 < sample clock 2(C) exists, an output of a counter 3 is '0100', signals QD, QC among the clocks are given to the ENABLE terminal of the counter 3 via a 2-1 selector 5 to hold the count of the counter 3 till the next clear (E) signal comes. Thus, a normal address is given to a ROM in which a tap coefficient is stored and an accurate value is outputted.

Description

[Detailed description of the invention] [General! ! ] Regarding the timing generation circuit of a digital filter, the purpose is to be able to output accurate filter values even when the internal clock and sample clock are not synchronized. a first differentiating circuit that receives an internal clock (A>) and a sample clock (C) having twice the frequency of the sample clock (B);
A) as a counter clock, a counter that receives the output of the second differentiating circuit as a clear (E) signal, and one that receives the outputs of the first and second differentiating circuits and shifts one of them to the delay circuit of the digital filter. a 2-1 selector outputting as a clock, and a 3rd . 4th output Qc
, a 2-1 selector that receives Qo and supplies one of them to the enable input of the counter, and outputs an AND signal of the 2-1t7 selector and the internal clock (A>) as a delayed data capture output. It consists of a gate.

Field of Industrial Application] The present invention relates to a timing generation circuit for a digital filter.

When a certain type of signal is taken into the device as digital data, it is sampled at a predetermined cycle timing, the sampled data is converted to digital data by an A/D converter, and this digitized data is Various types of processing (including filter circuit processing) are performed.

In this case, the timing of the digital filter circuit becomes a problem when the internal clock of the device and the sampling clock are not synchronized, that is, when they are asynchronous.

[Prior Art] FIG. 4 is a conceptual diagram of the configuration of a digital filter (transversal filter). Input data converted into digital data by the A/D converter is sequentially transmitted to multi-stage (N stages) delay elements 1. Then, the data delayed by the sampling clock are taken into the delay element 1, and the data are input into the multiplier 2 and are given tap coefficients at the same time.
(i=Q~N-1) is multiplied. The output of each multiplier 2 is an addition Ii! [It enters unit 3, is added, and is output.

FIG. 5 is an explanatory diagram of sampling. For the input shown in (a), A with the sampling period shown in (0)
/D conversion yields sampling data as shown in (c). This sampling data becomes the input data in FIG.

FIG. 6 is a diagram showing a detailed configuration example of a digital filter. The input data string is roughly divided into (I) column and (Ir) column,
When the number of samples is 4, the (I) column becomes the input data, and when the number of samples is 2, the (1) column and the (■) column each become the input for one channel. In the figure, F1 to F26
is D type 7 lip flop (FF), M1~M12
is a 2-1 selector that selects one of the two human forces, N1 to N4 is an 8-1 selector that selects one of the eight human forces, and B1.8 receives input data.
2 is a buffer. All of the 2-1 selectors M1 to M12 in the figure contain select signals (A when the number of samples is 2, and B when the number of samples is 4).

In the circuit configured in this way, when the number of samples is 2, the select signal selects A of the 2-1 selectors M1 to M12, and the data input (1) is sent to the flip 70 block F.
1 to F7, the output of the flip-flop 70 block F7 enters the 7-lip 70 block F21, and the output of each stage of each 7-lip flop goes to the 8-1 selector N1. N2
The signals are sequentially selected by , added to the adder by 1, and outputted through the flip 70 tube F27.

In this case, the shift clock 5CLKG is input to the flip 70 knob of each stage, and the 8-1 selector N1. N2 contains a select signal (H>).

On the other hand, the data input (II) is sequentially delayed from the flip-flop F8 through the 2-1 selector M7 to F20, and the output of each 7-lip, 70-tub stage is output to the 8-1 selector N3. After being sequentially selected by N4 and added to the adder by 2, it is outputted via flip 70 and F28.

When the number of samples is 4, the output of the flip-flop F7 passes through the 2-1 selector M7 and enters the flip-flop F9, and the output of the flip-flop F20 passes through the 2-1 selector M4 and enters the flip-flop F21. ing. As a result, 26 stages of flip-flops are connected in series.

FIG. 7 is a diagram showing an example of a conventional configuration of a timing generation circuit that generates a timing signal for the digital filter shown in FIG. 6. The internal clock (A) is connected to the buffer gate G1.
Internal voltage 0 via inverter G2 and buffer 7 gate G3
Output as tsk(0). Sample clock 1 (B
) is a clock of frequency f, which enters the first differentiating circuit 1 via the buffer gate G4. The output of the differentiating circuit v1 is input to the counter CA as a clear signal (CLR) (E). Sample clock 2 (C) with frequency 2f
enters the second differentiator V2 via the buffer gate G5. Then, the output of the differentiating circuit v2 is the 2-1 selector M
It is in one input of 20. 2-1 selector M20
The output of the first differentiating circuit 1 is input to the other input of the . Then, the output of the 2-1 selector M20 passes through the buffer gate G6, and then passes through the aforementioned shift clock 5CLK (G
> is output.

The internal clock (D> is included in the counter CA as a counting clock.The output from the lower three pits of the counter CA becomes an address to the ROM (not shown) in which the tap coefficients are stored via the gate G7. .Also, the same 3
The bit output passes through the gate circuit G8 and is output as a select (H) signal to the 8-1 selectors N1 to N4. Furthermore, the counter address enters one input of gate G10 via gate G9, and the internal clock (A) enters the other input of gate G10. Then, the output of the gate G10 passes through the buffer gate G11, and the signal LCLK for detecting the filter value at the end of the adder output.
is output as In this conventional circuit, at the time of two samples, a pulse obtained by differentiating the sample clock 1 (B) is shifted to the shift clock 5CLK of 7 lip-flops F1 to F26.
(G), and at 4 samples, sample clock 2 (C
) shift clock 5CLK (G)
It is used as Here, the case of 4 samples, which is problematic in the conventional circuit, will be explained.

FIGS. 8 and 9 are timing cheats showing the operation of each part of the conventional system. In the figure, (A) is the internal clock (A),
(B) Sample clock 1 (B), (C) Sample clock 2 (C), (D) Internal clock (D), (E) CLR (E) signal that clears counter GA, (F) is the counter address (F) as a ROM address output from counter CA, (g) is the clock 5CLK for flip 70 rotation (G), and (ch) is ■～■
The input data up to (S) is the output (J) of 8-1 selector N1, (NU) is the output (K) of 8-1 selector N2, (
117) Output (N), (O) is the ROM output where the tap coefficient is stored, (W) is the output of the 2-1 selector M7, (Power) is the adder multiplied by the tap coefficient. The outputs (filter values) are shown respectively.

The figure shows a case where the internal clock (Δ) and the sample clock (B) or (C) are in phase and synchronized. In this case, the output 1 of the 8-1 selector N1 and the output of the 8-1 selector N2 are sequentially added and outputted. Then, after this output value is multiplied by the tap coefficient, the adder output (power)
The final data is output as .

Now, with the differentiated shift clock 5CLK (G),
Sample data (I) is converted to an external Δ/D converter (not shown).
However, due to this circuit structure, the internal clock (
A) and sample clock 2 (C) are synchronized as shown in Figure 8, and the width of internal clock (A) x 4 - sample clock 2 (C)
) The data string of the output of flip-flops F1 to F26 that functions as a shift register only when the width relationship holds.■
The relationship between ~@ and the select (H) signal which is the counter output is maintained normally, and the 8-1 selector N1. Output of N2 (J
), (K). Here, since the tap coefficients of this digital filter are symmetrical, symmetrical data is converted to tK′Iv
#Shiru.

[Problems to be Solved by the Invention] However, as shown in FIG. 9, the internal clock (A) and the sample clock 2 (C) may be asynchronous, or the width of the internal clock 1 (A) x 4 Number clock 2 (
C) When it comes to width, shift register (flip-flop) F1~
Select (H) which is the data string of F26 and the counter output
If the relationship with the signal is not maintained normally, the 8-1 selector N1. Output of N2 (J).

Inappropriate data is placed on (K) (see Figure 9 (L)),
There was a problem in that the filter value obtained by multiplying it by a tap coefficient and adding the result (see FIG. 9 (force)) was not a normal value.

The present invention has been made in view of these problems, and provides a timing generation method for a digital filter that can output accurate filter values even when the internal clock and sample clock are not synchronized. The purpose is to provide circuits.

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention. In the figure,
1 is a first differentiating circuit that receives an internal clock (A>) and a sample clock (B); 2 is an internal clock (A>) and a sample clock (C) having twice the frequency of the sample clock (B); 3 is a counter that receives the internal clock (A) as a counter clock and the output of the second differentiator 2 as a clear (E) signal; 4 is a counter that receives the internal clock (A) as a clear (E) signal; 4 is a counter that receives the internal clock (A) as a counter clock; A 2-1 selector receives the output and outputs one of the outputs as a shift clock (G) for the delay circuit of the digital filter, and 5 indicates the third and fourth outputs Qc of the counter.

A 2-1 selector receives Qo and supplies one of them to the enable input of the counter 3, and 6 outputs an AND signal between the output of the 2-1 selector 5 and the internal clock (A>) as a delay data capture clock. This is the output gate.

[Operation] When internal clock 1 (A) and sample clock 2 (C) are asynchronous, or when internal clock 1 (△) width x 4 < sample clock 2 (C)
), the output of counter 3 becomes "0100",
Of these, Qo and Qc are given to the enable (ENABLE) terminal of the counter 3 via the 2-1 selector 5,
The counting operation of counter 3 is held until the next clear (E) signal is input. Therefore, the ROM storing the tap coefficients is given a normal address and an accurate filter value is output.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. Components that are the same as those in FIGS. 1 and 17 are designated by the same reference numerals. The acquisition clock (Q) is outputted via a buffer gate G30. G31 is a flip 70 tube which receives the output of the second differentiating circuit 2 at its clock input CK and receives the sample clock 1 (B) at its D input. The output of this flip 70 tube G31 is part of the select signal (H) in the 4 sample mode. The operation of the circuit configured as described above will be explained as follows.

First, the timing generation circuit shown in FIG. 2 generates various timing signals to be applied to the digital filter circuit shown in FIG. 6. FIG. 3 is a timing chart showing the operation of each part according to the present invention. In the figure, (a) is the internal clock (A), and (b) is the sample clock 1.
(B) and (C) are the sample clock 2 (C), (D) is the internal clock (D), (E) is the CLR (E) signal that clears the counter 3, and the shift register (flip-flop Shift clock 5CLK (G), (to) that shifts F1 to F26) is the counter address (F), (to) as a ROM address output from counter 3.
G) is the input data from ■ to @, (H) is the output (L) of the 8-1 selector N3, (S) is the output (M) of the 8-1 selector N4, and (N) is the input data of 2 to the adder. Outputs (0) and (l) are the data capture clock (Q) in which the tap coefficients are stored,
(e) shows the data of tap coefficient multiplication, (w) shows the output of the 2-1 selector M7, and (power) shows the output (filter value) of the adder multiplied by the tap coefficient. Second
In the inventive circuit shown in the figure, in the 4-sample mode, the sample clock 2 (C) is differentiated and the clear (CL) shown in (E) is
Generate R) (E) signal and shift pulse (SCLK) (G).

At this time, the internal clock (A) is (
As shown in (d) and (e), if there are 5 or more clocks, the count value of counter 3 becomes "0100", and counter 3
QO 01'' is input to the enable input E, and the counting operation of the counter 3 is stopped until the next CLR signal (E) is input.As a result, the counter 3 retains the count value up to that point.

In addition, select signals (H) of 8-1 selectors N1 to N4
is the inversion of the signal latched by hitting the lower two bits of the counter 3 and the sample clock 1 with 5CLK (G). As a result, the output of counter 3 (address (F
)) becomes as shown in (to), and 8-1 selector N3
．． The output data (L) and (M) of N4 and the output (0) of adder 2 are as shown in (H), (S), and (N), respectively. Then, when capturing the data multiplied by the tap coefficient, by capturing with the capture clock (Q),
By removing the extra data, normal filter values can be obtained as shown in (force). Note that the last time point is read at LCLK when all data addition is completed.

In the above description, the case where the number of pigs is 1 to 26 has been described, but the present description is not limited to this and any number may be used.

[Effects of the Invention] As described above in detail, according to the present invention, when the sample clock and the internal clock are asynchronous or when there are 5 or more internal clocks between shift clocks, the counting operation of the counter is stopped. By stopping, it is possible to provide a timing generation circuit for a digital filter that can always obtain accurate digital values.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of a configuration showing an embodiment of the invention, Fig. 3 is a timing chart showing the operation of each part according to the invention, and Fig. 4 is a configuration of a digital filter. Conceptual diagram, Figure 5 is an explanatory diagram of sampling, Figure 6 is a diagram showing a detailed configuration example of a digital filter, Figure 7 is a diagram showing a conventional configuration example of a timing generation circuit, Figures 8 and 9 are conventional diagrams. 3 is a timing chart showing the operation of each part of FIG. In FIG. 1, 1.2 is a differential circuit, 3 is a counter, 4.5 is a 2-1 selector, and 6 is a gate.

Claims (1)

[Claims] A first differentiating circuit (1) receiving an internal clock (A) and a sample clock (B); and two of the internal clock (A) and the sample clock (B).
The second differentiating circuit (2) receives the sample clock (C) with twice the frequency, uses the internal clock (A) as a counter clock, and clears the output of the second differentiating circuit (2) (E)
A counter (3) receives the output as a signal, and receives the output of the first and second differentiating circuits (1) and (2) and outputs one of them as a shift clock (G) for the delay circuit of the digital filter. 2-1 selector (
4); a 2-1 selector (5) that receives the third and fourth outputs Q_C and Q_D of the counter and supplies one of them to the enable input of the counter (3);
), and a gate (6) that outputs an AND signal of the internal clock (A) and the internal clock (A) as a delayed data capture clock.