JPH0322885Y2 - - Google Patents

Description

[Detailed explanation of the idea]

[Technical Field of the Invention] The present invention relates to a chip varistor with improved electrodes and exterior structure. [Technical background of the invention and its problems] In recent years, with the expansion of applications for varistors, they have become leadless, and the electrodes formed on the varistor body can be placed directly on a printed circuit board, making them compact and lightweight, which can contribute to high-density packaging. Demand for chip baristas is increasing. As shown in Fig. 6, the conventional chip varistor has a structure in which a square plate-shaped varistor body 21 is connected to a portion of the opposite side through both side surfaces, and is made of Ag or Ag-Pd. electrodes 22, 23 are provided, and the opposing electrodes 22, 23 are provided.
The distance t ₃ between the electrodes 12 and 13 on the opposing surfaces is made larger than the thickness t ₄ of the varistor body 21, and the portions of the electrodes 22 and 23 excluding the external connection electrode portions 24 and 25 are made of glass or An insulating layer 26 is formed by coating resin or the like, and the opposing electrodes 22 and 23 are
There is one in which the varistor properties are exhibited in the opposing portions W on both the front and back surfaces of the varistor body 21. However, the chip varistor with the above configuration is
As shown in FIG. 7, external connection electrode portions 24, 2
5 is used by attaching the solder 28 to the printed circuit board 27, but since the expansion coefficient of the printed circuit board 27 is larger than the expansion coefficient of the varistor element body 21, there is a risk that the soldered part 28 will peel off at high temperatures. Ag constituting the connection electrode portions 24 and 25;
Electrode materials made of Ag-Pd etc. tend to be eaten away by silver and have poor solder heat resistance. Furthermore, insulating layer 2
6 can only be formed as extremely thin as 5 to 40 μm,
This method has the disadvantage that a sufficient dielectric strength voltage of the insulating layer 26 cannot be ensured due to the occurrence of pinholes or cracks due to thermal shock during processing of the insulating layer 26. Therefore, it is conceivable to make the insulating layer 26 thicker, but in that case, as shown in FIG. Not only did this cause a new problem of making the state of attachment to the board unstable, but it still could not prevent peeling of the soldered portion and the phenomenon of silver eating of the electrode material, so it could not be said to be an effective countermeasure. [Purpose of the invention] The present invention has been developed in view of the above points, and by improving the electrode and exterior structure, it has improved solder heat resistance and dielectric strength characteristics, allowing stable attachment to printed circuit boards. The purpose of the present invention is to provide a chip varistor with improved characteristics. [Summary of the invention] The chip varistor of the present invention has a varistor element molded and sintered into a rectangular plate shape, and opposing electrodes are provided on both the front and back surfaces of the element body and connected to a part of the opposite side through both sides of the element, respectively. Electrode flanges are fitted to both ends of the varistor body through the electrodes and solder, and a molded insulating layer is formed in a plane between the electrode flanges and the surface of the electrode flanges, so that the electrodes are connected to the varistor body. The feature is that the varistor characteristics are exhibited in the opposing parts on both the front and back sides. [Embodiment of the invention] An embodiment of the invention will be described below with reference to the drawings. In other words, as shown in Figs. 1 and 2, ceramic powder containing zinc oxide, strontium titanate, barium titanate, iron oxide, silicon carbide, etc. as main components, and a mixture of several other metal oxides is used. A varistor element body 1 is formed by molding and sintering into a square plate shape, and Ag or Opposing electrodes 4 and 5 made of Ag-Pd are provided at both ends of the varistor body 1.
the third to connect via solder 6 with each
As shown in the figure, an electrode flange 7 made of soft copper, iron, or an alloy thereof, which has been subjected to solder plating, silver plating, or nickel plating, etc., is fitted, and then the front and back sides of the varistor element body 1 are placed between the electrode flange 7. Epoxy on both sides and front and back parts,
The electrode flange 7 is formed by transfer molding using a thermosetting resin made of phenol, unsaturated polyester, etc., or by in-die extension molding using a thermoplastic resin made of vinyl chloride, polyamide, polyimide, polycarbonate, etc.
A mold insulating layer 8 is formed planar to the surface, so that the electrodes 4 and 5 exhibit varistor characteristics at the portions H facing each other on both the front and back surfaces of the varistor element body 1. The chip varistor configured as above is
Solder 1 to the printed circuit board 9 as shown in FIG.
Since the 0 attachment point is electrode flange 7, electrodes 4 and 5 can be connected directly.
Without being exposed to soldering conditions (240°C, 30-60 seconds), there is no silver eating phenomenon and electrode damage is eliminated. Also, the electrode collar 7 is used as an external mounting part.
By using this, a sufficient thickness of the insulating layer can be ensured and an excellent dielectric strength voltage can be obtained. Further, since the electrode flange 7 surface and the mold insulating layer 8 surface are arranged in a plane and there is no difference in level, there is an advantage that all the drawbacks of the conventional example, such as stabilizing the mounting state to the printed circuit board 9, can be eliminated. In the above embodiment, the structure in which the mold insulating layer directly contacts the varistor element body was explained as an example, but as shown in FIG. By forming the layer 11 and forming the mold insulating layer 8 through the glass layer 11, it is possible to prevent oxygen depletion due to carbonization of the resin in the mold insulating layer 8 surrounding the electrodes 4 and 5. It is extremely effective in preventing property deterioration. In FIG. 5, parts that are not clear in the above explanation are given the same numbers as above, and the explanation is omitted. Next, we will discuss a comparison of the dielectric strength characteristics after thermal shock between the present invention and a conventional reference example. That is, the second
The present invention A shown in the figure, the present invention B shown in Fig. 5, and the sixth invention shown in Fig.
100℃ boiling water of conventional reference example C shown in the figure ←→0℃
After repeating 10 cycles of immersion in cold water for 5 minutes each, and then air drying at room temperature for 2 hours, the dielectric strength voltage between the external electrode and the insulating layer was measured, as shown in the table below, demonstrating the remarkable effects of the present invention.

[Effect of idea]

According to the present invention, it is possible to obtain a chip varistor of high practical value that greatly improves dielectric strength characteristics, eliminates electrode breakdown, and allows stable attachment to a printed circuit board.

[Brief explanation of drawings]

Figures 1 to 4 relate to one embodiment of the present invention.
The figure is a perspective view of the chip varistor, Figure 2 is a front sectional view of the chip varistor, Figure 3 is a perspective view showing the electrode collar, Figure 4 is a front sectional view showing how it is attached to a printed circuit board, and Figure 5 is a front sectional view of the chip varistor. A front cross-sectional view showing a chip varistor according to another embodiment of the present invention, FIGS. 6 and 7 are a front cross-sectional view showing a chip varistor according to a conventional example, and FIG. 7 is a front cross-sectional view showing a chip varistor according to a conventional example. FIG. 8 is a front sectional view showing a chip varistor according to another conventional reference example. 1... Ballista body, 2, 3... Side, 4, 5
...Electrode, 6...Solder, 7...Electrode collar, 8...
Mold insulating layer, 11... glass layer.

Claims (1)

[Claims for Utility Model Registration] (1) A varistor element formed into a rectangular plate shape and sintered, opposing electrodes formed by connecting each side of the element to a part of the opposing side, and the varistor. Electrode flanges are fitted onto both ends of the element body and connected to the electrodes via solder, and a molded insulating layer is formed at a portion located between the electrode flanges to be planar with the electrode flanges. Chip barista features. (2) The chip varistor according to claim (1) of the utility model registration, characterized in that a glass layer is formed between the varistor body and the mold insulating layer on at least both the front and back surfaces.