JPH03228355A - Substrate of hybrid ic - Google Patents
Substrate of hybrid icInfo
- Publication number
- JPH03228355A JPH03228355A JP2225890A JP2225890A JPH03228355A JP H03228355 A JPH03228355 A JP H03228355A JP 2225890 A JP2225890 A JP 2225890A JP 2225890 A JP2225890 A JP 2225890A JP H03228355 A JPH03228355 A JP H03228355A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- layer
- circuit board
- wires
- main body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title abstract 2
- 229920005989 resin Polymers 0.000 claims abstract description 37
- 239000011347 resin Substances 0.000 claims abstract description 37
- 230000001681 protective effect Effects 0.000 claims abstract description 28
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims description 4
- 239000011253 protective coating Substances 0.000 claims description 4
- 229910000679 solder Inorganic materials 0.000 abstract description 6
- 239000011810 insulating material Substances 0.000 abstract 1
- 239000007788 liquid Substances 0.000 description 12
- 239000003822 epoxy resin Substances 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 229920002050 silicone resin Polymers 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は半導体チップを実装した混成集積回路基板に関
する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a hybrid integrated circuit board on which a semiconductor chip is mounted.
（従来の技術）
近年、回路パターンを有する回路基板本体にＩＣやＬＳ
Ｉなどの半導体チップを実装した混成集積回路基板が各
種の分野に多用されている。(Prior art) In recent years, ICs and LS have been installed on circuit boards with circuit patterns.
Hybrid integrated circuit boards mounted with semiconductor chips such as I are widely used in various fields.
従来の混成集積回路基板としては第３図及び第４図に示
す構成のものが知られている。第３図は混成集積回路基
板を示す断面図であり、第４図は第３図の混成集積回路
基板の保護樹脂層を省略した平面図である。回路基板本
体１１は、絶縁基材１２上に回路パターン１３を形成し
た構造になっている。As a conventional hybrid integrated circuit board, those having the configurations shown in FIGS. 3 and 4 are known. FIG. 3 is a sectional view showing the hybrid integrated circuit board, and FIG. 4 is a plan view of the hybrid integrated circuit board of FIG. 3 with the protective resin layer omitted. The circuit board main body 11 has a structure in which a circuit pattern 13 is formed on an insulating base material 12.
半導体チップ１５は、前記本体１１の所望の回路パター
ン（グイパッド）にダイボンディングされている。ワイ
ヤ１Ｂは、前記本体１１の回路パターン１３と前記チッ
プ１５上面の電極パッドとを結線している。The semiconductor chip 15 is die-bonded to a desired circuit pattern (guid pad) of the main body 11. The wire 1B connects the circuit pattern 13 of the main body 11 and the electrode pad on the top surface of the chip 15.
ダム層１８は、前記チップ１５及びワイヤ１６周辺の前
記本体ｌｌ上に枠状に形成されている。前記ダム層１８
は、エポキシ系樹脂やシリコーン系樹脂などの液状樹脂
をデイスペンサーなどの装置を用いて描画しながら塗布
した後硬化することにより形成される。保護樹脂層１９
は、前記ダム層１８で囲まれた前記本体１１上に前記チ
ップ１５及びワイヤ［６を封止するように設けられてい
る。前記保護樹脂層１９は、エポキシ系樹脂などの液状
樹脂を前記ダム層１８の枠内にコーティングすることに
より形成される。The dam layer 18 is formed in a frame shape on the main body 11 around the chip 15 and the wire 16. The dam layer 18
is formed by applying a liquid resin such as an epoxy resin or a silicone resin in a drawing manner using a device such as a dispenser, and then curing the resin. Protective resin layer 19
is provided on the main body 11 surrounded by the dam layer 18 so as to seal the chip 15 and the wire [6]. The protective resin layer 19 is formed by coating the dam layer 18 with a liquid resin such as an epoxy resin.
ところで、前述した混成集積回路基板では十分な厚さの
保護樹脂層［９を設けて前記半導体チップ１５及びワイ
ヤ１６を良好に封止する必要がある。そのために、前記
ダム層１８を所定の高さて全体的に一定な高さにして前
記保護樹脂層１９を形成する際の液状樹脂の流れを堰き
止め、十分な厚さの保護樹脂層１９を設ける必要がある
。By the way, in the above-mentioned hybrid integrated circuit board, it is necessary to provide a protective resin layer [9 of sufficient thickness to seal the semiconductor chip 15 and the wires 16 well. For this purpose, the dam layer 18 is set to a predetermined height and has a uniform height overall to dam the flow of liquid resin when forming the protective resin layer 19, and to provide the protective resin layer 19 with a sufficient thickness. There is a need.
しかしながら、従来の混成集積回路基板では、ダム層１
８を形成する際に液状樹脂が流動変形して回路基板本体
１１上に広がって低くなったり、高さがバラついたりす
ることがある。このため、保護樹脂層■９の厚さを十分
に厚くできず、半導体チップ１５及びワイヤ１６の封止
が不完全になって、信頼性を低下させるという問題があ
った。なお、十分かつ一定な高さのダム層を設けるため
に流動性の低い液状樹脂を用いることが考えられるが、
かかる液状樹脂を用いるとその低流動性により塗布作業
の能率か著しく低下し、実際に採用するのは困難である
。However, in conventional hybrid integrated circuit boards, the dam layer 1
When forming the circuit board 8, the liquid resin flows and deforms and spreads over the circuit board body 11, resulting in the height becoming lower or being uneven. For this reason, the thickness of the protective resin layer (1) 9 cannot be made sufficiently thick, resulting in incomplete sealing of the semiconductor chip 15 and the wires 16, resulting in a decrease in reliability. In addition, it is possible to use a liquid resin with low fluidity in order to provide a dam layer with a sufficient and constant height.
When such a liquid resin is used, the efficiency of the coating operation is significantly reduced due to its low fluidity, and it is difficult to use it in practice.
（発明が解決しようとする課題）
本発明は、上記従来の課題を解決するためになされたも
ので、十分かつ一定な高さのダム層を有し、半導体チッ
プ及びワイヤを十分な厚さの保護樹脂層で良好に封止し
た高信頼性の混成集積回路基板を提供しようとするもの
である。(Problems to be Solved by the Invention) The present invention has been made in order to solve the above-mentioned conventional problems. The present invention aims to provide a highly reliable hybrid integrated circuit board that is well sealed with a protective resin layer.
［発明の構成コ
（課題を解決するための手段）
本発明は、絶縁基材上に回路パターンを有すると共に該
回路パターンの外部接続領域を除く表面に保護被膜を有
する回路基板本体と、前記本体の所望の回路パターンに
ダイボンディングされた半導体チップと、前記本体の回
路パターンと前記チップ上面の電極パッドとを結線する
ワイヤと、前記チップ及びワイヤ周辺の前記保護被膜に
形成された枠状の開口部と、この開口部内に底部が充填
された枠状のダム層と、このダム層で囲まれた前記本体
上に前記チップ及びワイヤを封止するように設けられた
保護樹脂層とを具備したことを特徴とする混成集積回路
基板である。[Structure of the Invention (Means for Solving the Problems) The present invention provides a circuit board main body having a circuit pattern on an insulating base material and having a protective coating on the surface of the circuit pattern except for an external connection area, and the main body. a semiconductor chip die-bonded to a desired circuit pattern, a wire connecting the circuit pattern of the main body and an electrode pad on the top surface of the chip, and a frame-shaped opening formed in the protective coating around the chip and the wire. a frame-shaped dam layer with a bottom filled in the opening, and a protective resin layer provided on the main body surrounded by the dam layer so as to seal the chip and the wire. This is a hybrid integrated circuit board characterized by the following.
（作用）
本発明によれば、ワイヤが結線され、ダイボンディング
された半導体チップ周囲の回路基板本体上に被覆された
保護被膜に枠状の開口部を設け、この開口部内に底部が
充填された枠状のダム層を設けることによって、該ダム
層を液状樹脂で形成する際にこの液状樹脂が前記開口部
の段差により横方向に広がるのを抑制できる。その結果
、十分かつ一定な高さのダム層を前記開口部の位置に設
けることができるため、該ダム層で囲まれ、前記半導体
チップ及びワイヤが位置する前記本体上に十分な厚さの
保護樹脂層を設けることができる。(Function) According to the present invention, a frame-shaped opening is provided in the protective film coated on the circuit board body around the semiconductor chip to which wires are connected and die-bonded, and the bottom portion is filled in the opening. By providing the frame-shaped dam layer, when the dam layer is formed of liquid resin, it is possible to suppress the liquid resin from spreading in the lateral direction due to the step difference in the opening. As a result, a dam layer of sufficient and constant height can be provided at the location of the opening, so that a sufficient thickness of protection can be provided on the body surrounded by the dam layer and on which the semiconductor chip and wires are located. A resin layer can be provided.
従って、前記保護樹脂層により半導体チップ及びワイヤ
が良好に封止された高信頼性の混成集積回路基板を得る
ことができる。Therefore, it is possible to obtain a highly reliable hybrid integrated circuit board in which the semiconductor chip and wires are well sealed by the protective resin layer.
（実施例）
以下、本発明の実施例を図面を参照して詳細に説明する
。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図は本発明の混成集積回路基板を示す断面図であり
、第２図は第１図の混成集積回路基板の保護樹脂層及び
ダム層を省略した平面図である。FIG. 1 is a sectional view showing a hybrid integrated circuit board of the present invention, and FIG. 2 is a plan view of the hybrid integrated circuit board of FIG. 1 with the protective resin layer and dam layer omitted.
回路基板本体ｌは、絶縁基材２上に回路パターン３が形
成されていると共に該回路パターン３の外部接続領域を
除く表面に保護被膜であるソルダーレジスト層４を形成
した構造になっている。半導体チップ５は、前記本体ｌ
の所望の回路パターン（ダイパッド）にダイボンディン
グされている。The circuit board body 1 has a structure in which a circuit pattern 3 is formed on an insulating base material 2, and a solder resist layer 4, which is a protective film, is formed on the surface of the circuit pattern 3 except for the external connection area. The semiconductor chip 5 is connected to the main body l.
is die-bonded to the desired circuit pattern (die pad).
ワイヤ６は、前記本体１の回路パターン３と前記チップ
５上面の電極パッドとを結線している。枠状の開口部７
は、前記チップ５及びワイヤ６周辺の前記ソルダーレジ
スト層４に形成されている。A wire 6 connects the circuit pattern 3 of the main body 1 and the electrode pad on the upper surface of the chip 5. Frame-shaped opening 7
are formed in the solder resist layer 4 around the chip 5 and the wire 6.
枠状のダム層８は、前記開口部７内にその底部が充填さ
れて設けられている。前記ダム層８は、エポキシ系樹脂
やシリコーン系樹脂などの液状樹脂をデイスペンサーな
どの装置を用いて前記開口部７内の本体１上に描画しな
がら塗布した後硬化することにより形成される。保護樹
脂層８は、前記ダム層７で囲まれた前記本体１上に前記
チップ５及びワイヤ６を封止するように設けらでいる。The frame-shaped dam layer 8 is provided so that its bottom portion is filled in the opening 7. The dam layer 8 is formed by applying a liquid resin such as an epoxy resin or a silicone resin onto the main body 1 inside the opening 7 using a device such as a dispenser, and then curing the resin. A protective resin layer 8 is provided on the main body 1 surrounded by the dam layer 7 so as to seal the chip 5 and the wires 6.
前記保護樹脂層９は、エポキシ系樹脂などの液状樹脂を
コーティングすることにより形成される。The protective resin layer 9 is formed by coating a liquid resin such as an epoxy resin.
このような構成によれば、回路基板本体１上のソルダー
レジスト層４に枠状の開口部７を設け、この開口部７内
にダム層８をその底部が充填されるように設けることに
よって、該ダム層８を液状樹脂により形成する際に横方
向の広がりを前記開口部７の段差で抑制できる。その結
果、十分かつ一定な高さのダム層８を設けることができ
るため、該ダム層８で囲まれ、前記半導体チップ５及び
ワイヤ６が位置する前記本体１上に十分な厚さの保護樹
脂層９を設けることができる。このため、前記保護樹脂
層９により半導体チップ５及びワイヤ６が良好に封止で
きる。更に、回路基板本体ｌの表面から半導体チップ５
までの間にダム層８、ソルダーレジスト層４の一部及び
保護樹脂層９の３層の樹脂をコートした構成であるため
、回路基板本体１の表面から半導体チップ５への水分な
どの浸透を十分に防１卜することができる。従って、信
頼性の高い混成集積回路基板を得ることができる。According to such a configuration, the frame-shaped opening 7 is provided in the solder resist layer 4 on the circuit board body 1, and the dam layer 8 is provided in the opening 7 so that the bottom thereof is filled. When the dam layer 8 is formed of liquid resin, lateral expansion can be suppressed by the step of the opening 7. As a result, since the dam layer 8 can be provided with a sufficient and constant height, a protective resin of sufficient thickness can be formed on the main body 1 surrounded by the dam layer 8 and on which the semiconductor chip 5 and the wires 6 are located. A layer 9 can be provided. Therefore, the semiconductor chip 5 and the wires 6 can be sealed well by the protective resin layer 9. Furthermore, the semiconductor chip 5 is removed from the surface of the circuit board main body l.
Since the structure is coated with three layers of resin, the dam layer 8, a part of the solder resist layer 4, and the protective resin layer 9, the penetration of moisture from the surface of the circuit board body 1 into the semiconductor chip 5 is prevented. It can be sufficiently defended. Therefore, a highly reliable hybrid integrated circuit board can be obtained.
また、ダム層８を形成するための液状樹脂として比較的
流動性の高いものを用いることもできるため、塗布性な
どが阻害されず、ダム層を効率よく形成することが可能
となる。Furthermore, since a liquid resin with relatively high fluidity can be used to form the dam layer 8, the applicability is not hindered and the dam layer can be formed efficiently.
［発明の効果コ
以上詳述した如く、本発明によれば十分かつ一定な高さ
のダム層を有し、半導体チップ及びワイヤを十分な厚さ
の保護樹脂層で良好に封止した高信頼性の混成集積回路
基板を提供することができる。[Effects of the Invention] As detailed above, the present invention has a dam layer with a sufficient and constant height, and is highly reliable in that the semiconductor chip and wires are well sealed with a protective resin layer of sufficient thickness. A hybrid integrated circuit board can be provided.
第１図は本発明の混成集積回路基板を示す断面図、第２
図は第１図の混成集積回路基板の一部を省略した平面図
、第３図は従来の混成集積回路基板を示す断面図、第４
図は第３図の混成集積回路基板の一部を省略した平面図
である。
ｌ・・・回路基板本体、２・・・絶縁基板、３・・・回
路パターン、４・・・ソルダーレジスト層（保護被膜）
、５・・・半導体チップ、６・・・ワイヤ、７・・・開
口部、訃・・ダム層、９・・・保護樹脂層。FIG. 1 is a sectional view showing a hybrid integrated circuit board of the present invention, and FIG.
The figure is a partially omitted plan view of the hybrid integrated circuit board in Figure 1, Figure 3 is a sectional view showing a conventional hybrid integrated circuit board, and Figure 4 is a cross-sectional view showing a conventional hybrid integrated circuit board.
The figure is a partially omitted plan view of the hybrid integrated circuit board of FIG. 3. l... Circuit board body, 2... Insulating board, 3... Circuit pattern, 4... Solder resist layer (protective film)
, 5... Semiconductor chip, 6... Wire, 7... Opening, end... Dam layer, 9... Protective resin layer.
Claims (1)
ンの外部接続領域を除く表面に保護被膜を有する回路基
板本体と、前記本体の所望の回路パターンにダイボンデ
ィングされた半導体チップと、前記本体の回路パターン
と前記チップ上面の電極パッドとを結線するワイヤと、
前記チップ及びワイヤ周辺の前記保護被膜に形成された
枠状の開口部と、この開口部内に底部が充填された枠状
のダム層と、このダム層で囲まれた前記本体上に前記チ
ップ及びワイヤを封止するように設けられた保護樹脂層
とを具備したことを特徴とする混成集積回路基板。A circuit board main body having a circuit pattern on an insulating base material and having a protective coating on the surface except for an external connection area of the circuit pattern, a semiconductor chip die-bonded to a desired circuit pattern of the main body, and a circuit of the main body. a wire connecting the pattern and the electrode pad on the top surface of the chip;
A frame-shaped opening formed in the protective coating around the chip and the wire, a frame-shaped dam layer whose bottom is filled in the opening, and the chip and the wire on the main body surrounded by the dam layer. 1. A hybrid integrated circuit board comprising a protective resin layer provided to seal wires.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2225890A JP2797598B2 (en) | 1990-02-02 | 1990-02-02 | Hybrid integrated circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2225890A JP2797598B2 (en) | 1990-02-02 | 1990-02-02 | Hybrid integrated circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03228355A true JPH03228355A (en) | 1991-10-09 |
| JP2797598B2 JP2797598B2 (en) | 1998-09-17 |
Family
ID=12077749
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2225890A Expired - Lifetime JP2797598B2 (en) | 1990-02-02 | 1990-02-02 | Hybrid integrated circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2797598B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0568635U (en) * | 1992-02-25 | 1993-09-17 | スタンレー電気株式会社 | Mask for solder paste printing |
| KR100292033B1 (en) * | 1998-05-13 | 2001-07-12 | 윤종용 | Semiconductor chip package and method for manufacturing same |
| US6365979B1 (en) * | 1998-03-06 | 2002-04-02 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
| US6984286B2 (en) | 2001-01-17 | 2006-01-10 | International Business Machines Corporation | Adjusting fillet geometry to couple a heat spreader to a chip carrier |
| JP2008277248A (en) * | 2006-11-22 | 2008-11-13 | Alps Electric Co Ltd | Manufacturing method of light guide member, and light guide member and light guide plate |
| JP2017005175A (en) * | 2015-06-12 | 2017-01-05 | 凸版印刷株式会社 | Semiconductor package substrate, semiconductor package and manufacturing method of the same |
-
1990
- 1990-02-02 JP JP2225890A patent/JP2797598B2/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0568635U (en) * | 1992-02-25 | 1993-09-17 | スタンレー電気株式会社 | Mask for solder paste printing |
| US6365979B1 (en) * | 1998-03-06 | 2002-04-02 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
| KR100292033B1 (en) * | 1998-05-13 | 2001-07-12 | 윤종용 | Semiconductor chip package and method for manufacturing same |
| US6984286B2 (en) | 2001-01-17 | 2006-01-10 | International Business Machines Corporation | Adjusting fillet geometry to couple a heat spreader to a chip carrier |
| JP2008277248A (en) * | 2006-11-22 | 2008-11-13 | Alps Electric Co Ltd | Manufacturing method of light guide member, and light guide member and light guide plate |
| JP2012256085A (en) * | 2006-11-22 | 2012-12-27 | Mitsubishi Chemicals Corp | Light-emitting device, and manufacturing method of light-emitting device |
| JP2017005175A (en) * | 2015-06-12 | 2017-01-05 | 凸版印刷株式会社 | Semiconductor package substrate, semiconductor package and manufacturing method of the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2797598B2 (en) | 1998-09-17 |
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