JP2017005175A - Semiconductor package substrate, semiconductor package and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor package substrate and a semiconductor package which reduce warpage of the semiconductor package in which a plurality of semiconductor chips are arranged and further prevent detachment of the semiconductor package substrate and disconnection in a refrigerated/heating atmosphere.SOLUTION: A manufacturing method of a semiconductor package including a semiconductor package substrate and a plurality of semiconductor chips arranged on the semiconductor package substrate comprises: a process of forming between at least one pair of semiconductor chips adjacent to each other, a protruded region which protrudes from the package substrate; and a process of inserting an underfill into a gap between the semiconductor package substrate and the semiconductor chips so as to be isolated by the protruded region.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor package substrate, a semiconductor package, and a manufacturing method thereof.

  A semiconductor package substrate is used for electrical connection between the semiconductor chip and the motherboard. The semiconductor package substrate also serves to bridge the difference in thermal expansion coefficient between the semiconductor chip and the printed wiring board on which the semiconductor package is mounted, thereby increasing the bonding reliability of the system mounting. Because of this role, the semiconductor package substrate is called an interposer substrate.

  In addition, the semiconductor package substrate is converted into a line width and pitch between the semiconductor chip and the mother board by changing the wiring width and pitch in the substrate in each layer to obtain electrical connection.

  On the other hand, there are various connection / mounting methods between the semiconductor package substrate and the semiconductor chip depending on the use situation, but flip chip connection / mounting is often used in which the semiconductor chip and the semiconductor package substrate are connected by metal bonding such as solder or gold. . Flip chip connection is often used in high performance semiconductor packages because many terminals can be connected to the semiconductor package substrate by arranging the terminal surface of the semiconductor chip on the terminal surface on the substrate side.

  However, after flip-chip mounting, the semiconductor chip and the semiconductor package substrate are held only by a minute metal such as solder, and the difference in linear expansion coefficient between the semiconductor chip and the package substrate is high and low temperature. As a result, stress concentrates on the solder bumps, and cracks and interfacial peeling of the substrate occur in the solder, which may lead to failure of the semiconductor package.

  Therefore, conventionally, a resin called underfill is poured into the gap between the semiconductor chip and the substrate by utilizing the capillary phenomenon to relieve the stress of the solder bumps and ensure the connection reliability.

  In recent years, not only the conventional SoC (System on a Chip) but also SiP (System in Package) for building a large-scale system on one package is used to develop a high-performance system in a short period of time. ing. For example, there are cases where a plurality of semiconductor chips such as a CPU / GPU and a large-capacity memory are arranged next to each other on a single package substrate, or chips are stacked and arranged three-dimensionally.

  Furthermore, in a form in which a plurality of semiconductor chips are arranged in two or three dimensions, in order to reduce the overall size of the package, in recent years, by reducing the power consumption of the semiconductor chip and increasing the bandwidth of signal transmission, the signal attenuation between the chips is suppressed. Therefore, it is required to reduce the distance between the semiconductor chips to be arranged.

  FIG. 4 is a cross-sectional view showing a configuration of a semiconductor package according to the prior art. This is an example of a structure in which two semiconductor chips 1 are arranged on a semiconductor package substrate 2 using a flip chip mounting method. The semiconductor chip 1 and the semiconductor package substrate 2 are joined via solder bumps 3. An underfill 4 is inserted between the semiconductor chip 1 and the semiconductor package substrate 2.

  FIG. 5 is a sectional view showing the structure of a semiconductor package substrate according to the prior art. A core base material 5 using glass epoxy resin, glass, or silicon plate is formed at the center of the semiconductor package substrate. Further, the wiring pattern 6 and the insulating resin layer 7 are laminated in this order on the top and bottom of the core substrate 5. Further, through-hole electrodes 8 or vias 9 are provided in the core base material 5 and the buildup layer for the conduction of each wiring pattern 6.

  Further, a solder resist layer 10 is formed on the uppermost or lowermost insulating resin layer 7, and an electrode pad 11 is formed in a portion where the solder resist layer 10 is not present.

  FIG. 6 is a cross-sectional view of an underfill insertion process according to the prior art when two semiconductor chips are arranged on a semiconductor package substrate. The semiconductor chip 1 and the semiconductor package substrate 2 are mounted with their surfaces having connection terminals facing each other (see FIG. 6A), and then heated to join the solder bumps 3 (see FIG. 6B). . Thereafter, the underfill 4 is inserted between the semiconductor chip and the semiconductor package substrate (see FIG. 6C).

  At that time, when the gap between the semiconductor chips becomes equal to or smaller than the fillet width generated at the end of the underfill, the mutual fillets are integrated (see FIG. 6C). Thereafter, the underfill is heated and cured. At this time, the package substrate is warped in a concave shape with the chip mounting surface facing upward due to curing shrinkage of the underfill existing between the chips (see FIG. 4B). The shape and size of the warp greatly affects the mountability in the secondary mounting process and the like and the decrease in connection reliability. For this reason, it is necessary to reduce warpage and ensure connection reliability.

  As a solution to these problems, it has been proposed to form a non-adhesion site that repels underfill between semiconductor chips on a semiconductor package substrate (Patent Document 1). In this method, the durability of mounting can be improved by preventing the underfill from being integrated. However, if the semiconductor chip is separated to some extent, the underfill is repelled by the non-adhered part, but if the distance between the semiconductor chips is narrowed and the width of the non-adhered part is reduced, or if the amount of underfill is large, non-adhesive It is difficult to secure the durability of the mounting because the underfill adjacent to each other is integrated.

  In addition, stress is generated at the interface between the fillet and the package substrate after curing due to the difference in the coefficient of linear expansion (CTE) and elastic modulus between the underfill and the semiconductor package substrate. May change, and the solder resist layer may be peeled off or the wiring just under the solder resist layer may be disconnected.

JP 2011-176022 A

  The present invention has been made under the circumstances described above, and in a semiconductor package in which a plurality of semiconductor chips are arranged two- or three-dimensionally, the warpage of the semiconductor package is reduced, and the underfill fillet portion of the semiconductor package in a high-temperature environment. It is an object of the present invention to provide a semiconductor package substrate and a semiconductor package that prevent the substrate from peeling and disconnection.

  One embodiment of the present invention is a method of manufacturing a semiconductor package including a semiconductor package substrate and a plurality of semiconductor chips arranged on the semiconductor package substrate, and includes at least one set of adjacent semiconductor chips from the package substrate. Forming a projecting projecting portion, and inserting an underfill between the semiconductor package substrate and the semiconductor chip so as to be separated by the projecting portion.

  Another embodiment of the present invention is a wiring pattern formed between a core base material, at least two or more insulating resin layers laminated on the core base material, or between the insulating resin layers or on the surface of the insulating resin layer. And an electrode pad connected to at least a part of the wiring pattern, and a solder resist layer that is laminated on the insulating resin layer farthest from the core substrate among the insulating resin layers and has an opening at least exposing the electrode pad And a protruding portion laminated on the solder resist layer.

  According to the present invention, by forming a protruding portion on the mounting surface of the semiconductor package substrate immediately below the portion where the semiconductor chips are adjacent to each other, the amount of cure shrinkage during underfill heating between the semiconductor chips is reduced, thereby warping the semiconductor package. In addition, it is possible to relieve stress generated at the interface between the semiconductor package substrate and the fillet in a high and low temperature environment by forming the protruding portion, and it is possible to prevent the peeling of the solder resist layer and the disconnection of the wiring. A conductor package substrate and a semiconductor package can be provided.

The top view of the semiconductor package which concerns on one Embodiment of this invention Sectional drawing which shows the manufacturing process of the semiconductor package which concerns on one Embodiment of this invention. Sectional drawing which shows the semiconductor package which concerns on the modification of this invention Sectional drawing which shows the structure of the semiconductor package which concerns on a prior art Sectional drawing which shows the structure of the semiconductor package board | substrate which concerns on a prior art Sectional drawing which shows the manufacturing process of the semiconductor package which concerns on a prior art

  A semiconductor package according to an embodiment of the present invention will be described below, but the present invention is not limited to this.

  FIG. 1 is a top view of a semiconductor package 100 according to each example of the present embodiment. In the semiconductor package 100, two or more semiconductor chips 1 are two-dimensionally arranged on a semiconductor package substrate 2. For example, semiconductor chips 1 having the same dimensions may be arranged as shown in FIGS. 1A and 1B, or semiconductor chips 1 having different dimensions may be arranged as shown in FIG. Further, two or more semiconductor chips 1 previously arranged in three dimensions may be arranged in two dimensions. The thickness of the semiconductor chip 1 may be the same or different. The interval between the semiconductor chips 1 is preferably 0.1 mm or more and 5 mm or less. Between at least one pair of adjacent semiconductor chips 1, protruding portions 12 that protrude from the semiconductor package substrate 2 are formed.

  FIG. 2 is a cross-sectional view showing the manufacturing process of the semiconductor package 100.

  First, the semiconductor package substrate 2 and the semiconductor chip 1 as shown in FIG.

  The semiconductor package substrate 2 has a core base material, vias and lands formed on both surfaces of the core base material, and wiring patterns on both surfaces (not shown). The core substrate has through-hole electrodes in the thickness direction for connecting each wiring pattern. The wiring pattern has a build-up layer in which an insulating resin is laminated (not shown).

  The buildup layer is formed by a buildup method and has an insulating resin layer and a wiring pattern. For example, an epoxy resin or a polyimide resin is used for the insulating resin layer, and a material obtained by adding a filler to the resin can also be used. Further, for example, copper is used as the wiring pattern material. Note that the wiring patterns of each layer are electrically connected to each other by vias.

  Further, electrode pads are formed on the uppermost and lowermost wiring patterns to connect electrical signals to the outside. A solder resist layer 10 is formed on the outermost surface so as to open on the electrode pad. In addition, the material which added the filler to the photosensitive epoxy resin and resin can also be used for the material of the soldering resist layer 10, for example. Solder bumps 3 are formed on the electrode pads using a printing method, a solder ball transfer method, or the like. The above configuration can be configured similarly to the conventional semiconductor package substrate shown in FIG. 5, for example.

  A protruding portion 12 is formed on the semiconductor package substrate 2. A protruding portion 12 is formed on the solder resist layer 10 of the semiconductor package substrate 2 immediately below the region where the semiconductor chips 1 are adjacent to each other when the semiconductor chip 1 is disposed. The length of the protruding portion 12 is preferably equal to or longer than the adjacent distance of the semiconductor chip 1 in order to prevent the integration of the fillet from the end of the semiconductor chip 1 of the underfill 4. Further, the cross-sectional shape of the protruding portion 12 can be a rectangular shape. Note that the adjacent distance of the semiconductor chip 1 refers to the length of the adjacent range along the side adjacent to another semiconductor chip.

  Further, the width of the protruding portion 12 is preferably close to the extent that the semiconductor chip 1 and the protruding portion 12 do not contact each other, and is preferably 0.1 mm or more and 5 mm or less.

  Moreover, the linear expansion coefficient of the projection part 12 is made smaller than the underfill described later. For example, epoxy resin, polyimide resin, copper, stainless steel, aluminum or the like is used as the material.

  Further, the thickness of the projecting portion 12 (the amount of protrusion from the semiconductor package substrate 2) is determined as appropriate between the thickness of the semiconductor chip 1, the interval between adjacent semiconductor chips 1, and the amount of underfill described later as appropriate. The thickness is preferably such that the underfill 4 is not integrated, for example, 0.01 mm to 5 mm.

  As a method of forming the protruding portion 12, a form material or a metal piece is cut in advance to the size of the protruding portion 12 and bonded to the semiconductor package substrate 2. As another method, the projection portion 12 may be formed on the solder resist layer 10 by using a screen printing method or a photographic method. The formation of the protruding portion 12 is not limited to after the solder bump 3 is formed, and the order of the steps may be changed as long as the protruding portion 12 can be formed on the solder resist layer 10.

  Next, as shown in FIG. 2B, a flux is applied on the semiconductor package substrate 2 and then flip chip mounting is performed to electrically connect the semiconductor package substrate 2 and the semiconductor chip 1.

  Next, as shown in FIG. 2C, the underfill 4 is inserted into a gap that is a space where the solder bumps 3 do not exist between the semiconductor package substrate 2 and the semiconductor chip 1. First, the underfill resin is arranged on one side or two sides near the mounting region. Thereafter, an underfill is inserted into the gap by capillary action. At this time, it is preferable to set the arrangement position of the underfill resin on the opposite side or the diagonal side of the protruding portion 12 so that the underfill 4 is finally inserted into the solder bump 3 on the protruding portion 12 side.

  By providing the projecting portion 12, the underfill 4 between the semiconductor chips 1 is formed with the projecting portion 12 as a boundary. Thereafter, the underfill 4 is cured by heating. The semiconductor package 100 can be manufactured as described above.

  When the underfill 4 is cured, the underfill 4 is cured and contracted. However, the amount of the underfill 4 between the semiconductor chips 1 is reduced in the volume of the protruding portion 12 and the contraction amount is decreased. Therefore, the stress generated at the interface between the underfill 4 and the semiconductor package substrate 2 is suppressed, and the amount of warpage is smaller than that in the case where there is no protruding portion 12.

  Here, in a high and low temperature environment, stress is generated at the interface due to a difference in coefficient of linear expansion between the fillet and the solder resist layer 10 on the semiconductor package substrate 2, and peeling of the solder resist layer 10 and wiring immediately below the solder resist layer 10 are performed. May break.

  In the semiconductor package 100, since the linear expansion coefficient of the projecting portion 12 is smaller than that of the underfill 4, the composite linear expansion coefficient in the region between the semiconductor chips 1 decreases. By doing so, the difference in linear expansion coefficient with the semiconductor package substrate 2 in the region between the semiconductor chips 1 is reduced, and the stress generated at the interface between the semiconductor chip 1 and the semiconductor package substrate 2 can be suppressed in a high and low temperature environment. In this way, peeling of the solder resist layer 10 and disconnection of the wiring can be prevented.

  FIG. 3 is a sectional view showing the structure of a semiconductor package 101 according to another embodiment of the present invention. The semiconductor package 101 is different from the semiconductor package 100 in that the protruding portion 12 is formed in the wiring layer under the solder resist layer 10. In the semiconductor package 101, when the semiconductor package substrate 2 is manufactured, the solder resist layer 10 at the position where the protruding portion 12 is formed is removed to expose the wiring layer. Thereafter, a metal protrusion 12 is formed on the wiring layer by electroplating or the like. In this way, even if it is difficult to form the protruding portion 12 on the solder resist layer 10, the protruding portion 12 can be formed.

  An embodiment of the present invention will be described below, but the present invention is not limited to this.

  As a semiconductor package substrate 2, a multilayer build-up print in which an epoxy resin in which a filler is added to an insulating resin layer 7 is used on a core substrate 5, copper is used as the material of the wiring pattern 6, and three wiring patterns 6 are formed. A wiring board was used. Also, solder bumps 3 having a pitch of 0.150 mm are formed on the semiconductor element joint portion by a solder ball mounting method. In addition, four semiconductor chip 1 mounting regions are provided, and the arrangement interval is 0.5 mm (see FIG. 1A). The printed wiring board has a size of 50 mm square and a thickness of 0.35 mm. Also, four semiconductor chips 1 having an outer shape of 20 mm square having solder bumps 3 with a thickness of 0.725 mm and a pitch of 0.150 mm were prepared.

  Next, a protrusion portion 12 having a width of 0.3 mm and a thickness of 0.4 mm obtained by curing an epoxy resin was laminated on the solder resist layer 10 (four places) where the semiconductor chips 1 of the semiconductor package substrate 2 are adjacent to each other. The laminating method was formed by applying an adhesive on the solder resist layer 10 of the semiconductor package substrate 2 (see FIG. 1A).

  Next, the semiconductor package substrate 2 was spray-applied to the semiconductor chip 1 connection range using a dispenser. Thereafter, the terminal surface of the semiconductor chip 1 was arranged in the mounting region of the semiconductor package substrate 2 using a mounter.

  Thereafter, the semiconductor package substrate 2 and the semiconductor chip 1 were joined using a reflow furnace in which the maximum temperature was 260 ° C.

  Thereafter, the flux was cleaned using a flux cleaner. The flux cleaning liquid used was an alkaline solvent.

  After pre-baking, the surface of the solder joint was modified using a plasma generator. Thereafter, an underfill 4 in which a filler was added to an epoxy resin manufactured by Namics Co., Ltd. was inserted between the semiconductor chip 1 and the semiconductor package substrate 2 bonded using a dispenser, and was cured by heating. In addition, the insertion method was inserted several times from the two sides of the projecting portion diagonally into the underfill 4 arrangement position at regular time intervals, and the heat curing conditions were 165 ° C. and 2 hours.

  Thereafter, the semiconductor chip 1 was bonded, and the semiconductor package substrate 2 was placed on the lower side with the underfill 4 inserted, and the warpage was measured. Using a shadow moire measuring device, the height from the flat surface to the highest point of the semiconductor package substrate 2 was measured as the amount of warpage. As a result of the measurement, the amount of warpage was 105 μm.

  Further, the semiconductor package 100 was subjected to 1000 cycles by alternately changing the temperature in the range of −55 ° C. to 125 ° C. using a thermal cold shock tester, and then the presence or absence of peeling between the semiconductor chips 1 was observed. As a result of the inspection, no peeling at each layer and no disconnection of the wiring were observed.

<Comparative example>
Further, as a comparative example, a semiconductor package was manufactured by a semiconductor package manufacturing method according to the related art shown in FIG.

  The produced semiconductor package was placed on the lower side and the warpage was measured. Using a shadow moire measuring device, the height from the flat surface to the highest point of the semiconductor package substrate was measured as the amount of warpage. As a result of the measurement, the amount of warpage was 230 μm.

  Moreover, the temperature of the manufactured semiconductor package was alternately changed in a range of −55 ° C. to 125 ° C. using a thermal cold shock tester, and after 1000 cycles, the presence or absence of peeling between the semiconductor chips was observed. As a result of the inspection, cracks and wire breakage were observed in the solder resist layer below the semiconductor chip.

  In comparison with the comparative example, in the example, it was confirmed that the warp of the semiconductor package can be reduced by using the structure of the present invention, and further, the peeling of the semiconductor package substrate between the semiconductor chips and the disconnection of the wiring can be prevented in a high and low temperature environment. did.

  The present invention is useful for semiconductor packages and the like.

DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Semiconductor package board | substrate 3 Solder bump 4 Underfill 5 Core base material 6 Wiring pattern 7 Insulating resin layer 8 Through-hole electrode 9 Via 10 Solder resist layer 11 Electrode pad 12 Protruding part 100, 101 Semiconductor package

Claims (10)

A semiconductor package manufacturing method comprising a semiconductor package substrate and a plurality of semiconductor chips disposed on the semiconductor package substrate,
Forming a projecting portion protruding from the package substrate between at least one set of the adjacent semiconductor chips;
A method of manufacturing a semiconductor package, comprising a step of inserting an underfill between the semiconductor package substrate and the semiconductor chip after the step of forming the protruding portion.   The method of manufacturing a semiconductor package according to claim 1, wherein the protruding portion has a width of 0.1 mm to 5 mm.   3. The method of manufacturing a semiconductor package according to claim 1, wherein in the step of inserting the underfill, the underfill is separated by a predetermined thickness of the protruding portion and is not integrated.   The method of manufacturing a semiconductor package according to claim 1, wherein a linear expansion coefficient of the protruding portion is smaller than a linear expansion coefficient of the underfill.   The method of manufacturing a semiconductor package according to claim 1, wherein a length of the protruding portion is equal to or longer than an adjacent distance between the semiconductor chips.   The method of manufacturing a semiconductor package according to claim 1, wherein a material of the protruding portion includes a resin or a metal.   The manufacturing method of the semiconductor package in any one of Claims 1-6 whose cross section of the said protrusion part is a rectangular shape.   The semiconductor package manufacturing method according to claim 1, wherein an interval between the semiconductor chips is 0.1 mm or more and 5 mm or less. A core substrate;
At least two or more insulating resin layers laminated on the core substrate;
A wiring pattern formed between the insulating resin layers or on the surface of the insulating resin layer;
An electrode pad connected to at least a part of the wiring pattern;
Of the insulating resin layer, a solder resist layer laminated on the insulating resin layer farthest from the core base material and having an opening through which at least an electrode pad is exposed, and a protruding portion laminated on the solder resist layer And a semiconductor package substrate. A semiconductor package substrate according to claim 9;
A semiconductor chip connected to the semiconductor package substrate via the electrode pad;
A semiconductor package including an underfill inserted between the semiconductor package substrate and the semiconductor chip.