JPH03227122A - First-order digital pll - Google Patents

Abstract

PURPOSE:To optionally select an oscillator generating an internal high speed clock by adding a multiplier outputting a fixed number of control pulses and an arithmetic circuit outputting a 1 pulse addition signal or a 1 pulse elimination signal. CONSTITUTION:A 1 pulse addition signal I2 from a rate multiplier 8 at free-run state is a 1 pulse addition signal I0 of an arithmetic circuit 9 as it is and one pulse is added to a pulse train of an internal high speed clock Rf0 in a 1 pulse addition or elimination circuit 6 by using the 1 pulse addition signal I0. In this case, the free run frequency is a frequency higher than the frequency f0. the number of position decision clocks CI, CD and the generated position are decided by the number of the 1 pulse addition signal I2 outputted from the rate multiplier 8. Thus, the free run frequency is finely adjusted.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital PLL (phase-locked loop), and particularly to a primary digital PLL used in the stuff synchronization method.

Conventional technology The conventional primary system digital PLL is as shown in Fig. 2.
An N frequency divider 1 that divides the input signal fin by N (N: a positive integer), an N frequency divider 2 that divides the output signal fout by N, and an internal high-speed clock Rfo (R: a positive integer, Fo: a multi-level quantization phase comparator 4 that quantizes the phase difference between the input signal fin and the output signal fout using an internal high-speed clock Rfo, and outputs the amount of phase advance or phase delay. , it counts up as the phase advances, and when it reaches 2N, it outputs a 1-pulse removal signal D1 and resets it to N1, it counts down as the phase lags, and when it reaches 0, it outputs a 1-pulse addition signal 11.
The N1 counter 5 outputs and resets to N1, and when the 1-pulse addition code 11 is input, the internal high-speed clock Rf
a 1-pulse addition or removal circuit 6 that adds 1 pulse to the pulse train of o, and removes 1 pulse from the pulse train of the internal high-speed clock Rfo when the 1-pulse removal signal D1 is input; It has an R frequency divider 7 that divides the pulse train outputted from the R frequency by R. Such a conventional technique is described, for example, in "All-Digital Line System PLL Using Multi-Level Quantization Phase Comparator", Journal of the Institute of Electronics and Communication Engineers, Vol. 82/3, J65-B.

Here, when a phase difference occurs between the input signal ftn and the output signal fout, the multi-level quantization phase comparator 4 determines the amount of phase difference and whether the phase is advanced or delayed, and converts the determination result into N
The N1 counter 5 operates as a digital filter and controls the 1 pulse addition or removal circuit 6 using the 1 pulse addition signal 1 or the 1 pulse removal signal DI from the Nl counter 5. Feedback control is performed so that the output signal fout is locked to the input signal fin.

Problems to be Solved by the Invention However, the above-mentioned conventional primary system digital PLL
In order to obtain the free-run frequency, the frequency of the oscillator that generates the internal high-speed clock is determined, so the frequency of the oscillator that generates the internal high-speed clock is uniquely determined, and the frequency of the oscillator that generates the internal high-speed clock is uniquely determined. Even if there is an oscillator with a frequency similar to that of the oscillator used, there is a problem that this oscillator cannot be used as an oscillator for generating an internal high-speed clock.

The present invention has been made in view of the above-mentioned conventional situation,
Therefore, an object of the present invention is to solve the above-mentioned problems inherent in the conventional technology, and to provide a novel primary system digital PL that makes it possible to arbitrarily select an oscillator that generates an internal high-speed clock.
The aim is to provide L.

Means for Solving the Problems In order to achieve the above object, the primary system digital PLL according to the present invention includes an N frequency divider that divides the input signal by N, and an N frequency divider that divides the output signal by N. and a multi-value quantization phase comparator that detects and quantizes the phase difference of each output of each of these frequency dividers,
An N1 counter that counts up and counts down based on the phase lead and lag information output from the multilevel quantization phase comparator, an oscillator that generates an internal high-speed clock, a fixed number of control pulses, and a
a rate multiplayer that generates a positioning clock for incorporating the pulse addition signal and the l-pulse removal signal into specific positional relationships with respect to the control pulse; The 1-pulse addition signal and 1-pulse removal signal from the Nl counter are inserted into the positions where the 1-pulse addition signal and 1-pulse removal signal are added and subtracted from the fixed number of control pulses output from the rate multiplayer. an arithmetic circuit that generates a pulse removal signal; and a 1-pulse addition signal and a 1-pulse removal signal output from the arithmetic circuit to add 1 pulse or remove 1 pulse from the pulse train of the internal high-speed clock output from the oscillator. The 1-pulse addition or removal circuit includes a 1-pulse addition or removal circuit, and an R frequency divider that smoothes the pulse train output from the 1-pulse addition or removal circuit.

Operation In the present invention, even during free run, that is, when the N counter does not output a 1-pulse addition signal or a 1-pulse removal signal, the control pulse from the rate multiplier passes through the arithmetic circuit to add or remove 1 pulse. It acts as a one-pulse addition signal or one-pulse removal signal for the removal circuit.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a primary digital PLL according to the present invention.

Referring to FIG. 1, one embodiment of the present invention provides an input signal f
N frequency divider 1 that divides in by N, and output signal fout by N
The N frequency divider 2 divides the frequency, and the internal high-speed clock Rfo (
R: a positive integer, an oscillator 3 that generates foζfin), and a multi-level quantizer that quantizes the phase difference between the input signal fin and the output signal fout using an internal high-speed clock Rfo, and outputs the amount of phase advance or phase delay. The phase comparator 4 counts up as the phase advances, and when the count value reaches 2N, outputs a 1-pulse removal signal D1 and resets it to N1, and counts down as the phase lags until the count value reaches 0. When it reaches 1 pulse addition number 1
An N1 counter 5 that outputs 1 and resets it to N1, and a fixed number of control pulses (in this embodiment, 1 pulse addition signal I2).
), a position determination clock CI for preventing the 1-pulse addition signal I□ from the Nl counter 5 from being generated simultaneously with the 1-pulse addition signal I2, and the 1-pulse removal signal from the N1 counter 5, Positioning clock CD for generating 1 pulse addition signal ■2 so as to cancel each other
a rate multiplier 8 that outputs
1 pulse addition signal 11 and rate multiplier 8 from
The final 1-pulse addition signal ■ is added with the 1-pulse addition signal I2 from . , subtracts the 1-pulse removal signal D1 from the N1 counter 5 and the 1-pulse addition signal I2 from the rate multiplier 8, and outputs the final 1-pulse removal signal Do. No. 1. When is inputted, one pulse is added to the pulse train of the internal high speed clock RfO, and when the one pulse removal signal Do is inputted, one pulse is removed from the pulse train of the internal high speed clock RfO. and an R frequency divider 7 that divides the pulse train output from the l pulse addition or removal circuit 6 by R frequency and smoothes it.

The rate multiplier 8 has a function of outputting an arbitrary number of clocks in the pulse train of the output signal fout of the R frequency divider 7 inputted to the clock input terminal as a control signal (1 pulse addition signal h) at as equal intervals as possible. It is a circuit that has a gate circuit, and is configured by a combination of gate circuits, etc. The number of output pulses of the one-pulse addition signal I2 is determined by the free run frequency.

Further, the arithmetic circuit 6 can be configured by a combination of a plurality of memories, a subtracter, etc. - such an arithmetic circuit is
For example, a patent application filed in 1983 by the same applicant as the present application.
3-215237 and the drawings.

In the free run operation in this embodiment, the 1-pulse addition signal I2 from the rate multiplier 8 is directly converted to the 1-pulse addition signal I of the arithmetic circuit 9. According to this 1-pulse addition code 1o, 1 pulse is added to the pulse train of the internal high-speed clock Rf in the 1-pulse addition or removal circuit 6, and in this case, the free run frequency becomes higher than fo. .

The number of position determination clocks CI and CD and their generation positions are determined by the number of one-pulse addition codes 2 outputted from the rate multiplier 8.

The above configuration and functions according to the present invention make it possible to finely adjust the free run frequency output by the PLL circuit according to the present invention when the input signal is disconnected.

The present embodiment described above is for the case where the 1-pulse addition signal I2 is used as the control pulse output from the rate multiplier 8, but the 1-pulse removal signal D2 is used instead of the 1-pulse addition signal I2. (not shown) can also be used to operate the arithmetic circuit 9 in the opposite manner to that of this embodiment. In that case, the positioning clock C1,
Of course, the relationship between the CD and the 1-pulse addition signal 11.1-pulse removal signal is reversed.

As described in detail, according to the present invention, the rate multiplier always outputs a fixed number of control pulses, and even during free run, the arithmetic circuit outputs one pulse additional signal or one pulse.
Since a pulse removal signal is output, it is possible to change the free run frequency by selecting the number of control pulses, which has the effect that the selection of the oscillator that generates the internal high-speed clock is not unique. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is a block diagram of a conventional example of a primary digital PLL.

Claims (3)

[Claims] (1) An N frequency divider that divides the input signal by N, an N frequency divider that divides the output signal by N, and a multivalued system that detects and quantizes the phase difference between the outputs of these N frequency dividers. A quantization phase comparator, an N_1 counter that counts up and counts down based on the phase lead and lag information output from the multi-level quantization phase comparator, an oscillator that generates an internal high-speed clock, and a a 1-pulse addition or removal circuit that adds 1 pulse or removes 1 pulse from the pulse train of the internal high-speed clock output by the oscillator according to the 1-pulse addition signal and the 1-pulse removal signal; In a primary digital PLL having an R frequency divider that smoothes an output pulse train, a fixed number of control pulses and the N_
A rate multiplier that generates a positioning clock for incorporating the 1-pulse addition signal and 1-pulse removal signal from the 1-counter into a specific positional relationship with respect to each control pulse, and each positioning clock from this rate multiplier. inserting a 1-pulse addition signal and a 1-pulse removal signal from the N_1 counter at positions determined by;
An arithmetic circuit that performs an addition/subtraction operation on a fixed number of control pulses output from the rate multiplier to generate a final 1-pulse addition signal and 1-pulse removal signal for the 1-pulse addition or removal circuit. A first-order digital PLL. (2) The number of control pulses output from the rate multiplier is determined by the free run frequency output by the primary digital PLL when the input signal is disconnected. The first-order digital PLL described in 1). (3) The fixed number of control pulses output from the rate multiplier is a one-pulse addition signal or a one-pulse removal signal.
The primary digital PLL described in 2).