CN114826257A

CN114826257A - fractional-N frequency division phase-locked loop and system

Info

Publication number: CN114826257A
Application number: CN202210629897.9A
Authority: CN
Inventors: 拉贾·普拉布·J; 桑迪普·萨西; 哈什瓦尔丹·雷迪
Original assignee: Shaoxing Yuanfang Semiconductor Co Ltd
Current assignee: Shaoxing Yuanfang Semiconductor Co Ltd
Priority date: 2021-07-05
Filing date: 2022-06-06
Publication date: 2022-07-29
Anticipated expiration: 2042-06-06
Also published as: CN114826257B; CN115208393A

Abstract

The invention relates to a fractional-N frequency division phase-locked loop and a system. The compensation module generates a compensation factor and is implemented based on the correction module and the filter. The correction module generates a correction signal comprising a first frequency correction factor and a second frequency correction factor. The first and second frequency correction factors are for the first and second periods. The first period and the second period constitute each pair of successive periods. The correction signal also contains a dc noise component. The filter removes a direct current noise component from the correction signal to generate a compensation factor including a first frequency correction factor and a second frequency correction factor. The resulting compensation factor may provide an input to a division factor generator that serves as a divider module of a fractional-N pll, such that zero-error frequency synthesis may be achieved.

Description

fractional-N frequency division phase-locked loop and system

Priority declaration

The present patent application claims priority to the Indian provisional patent application entitled "Minimizing Circuit Noise and Frequency synthesis error In Reference Clock Duty Cycle Compensation Loop of Phase Locked Loop System" filed with application No. 202141030146, filed 2021, 7/5. This indian provisional patent application is incorporated in its entirety into the present application without conflicting with the description herein.

This patent application claims priority to U.S. patent application entitled "Noise in Output Clock Due to Unequal consecutive time periods of a Reference Clock in Fractional-N Phase Locked Loop" entitled "Reduction of Noise in Output Clock Dual to unknown temporal periods of a Reference Clock in a Fractional-N Phase Locked Loop", entitled "priority of U.S. patent application No. 17/663,216, entitled" 2022, 5/13/d ". This U.S. patent application is incorporated herein in its entirety without conflicting with the description herein.

The present patent application claims priority to U.S. patent application entitled "cancellation of Noise Contribution in continuous time period compensation of Reference Clock inequality in Fractional-N Phase Locked Loop" (reduction Noise suppression in compensation for unknown Clock in a Fractional-N Phase Locked Loop) having a Reference Clock in a Fractional-N Phase Locked Loop with application number 17/663,217, filing date 2022, 5, 13. This U.S. patent application is incorporated herein in its entirety without conflicting with the description herein.

Technical Field

Embodiments of the present invention relate generally to Phase Locked Loops (PLLs), and more particularly, to a fractional-N PLL and system.

Background

fractional-N frequency-division phase-locked loops (PLLs) are often used to generate an output clock having a frequency that is a fractional multiple of the frequency of a reference clock that can be received as an input. Fractional multiples refer to multiples of the general form M.N, where M and N are positive integers, and "-" denotes the decimal point.

Since the reference clock itself may be derived by techniques such as frequency multiplication of an asymmetric source clock, the reference clock may have a continuous period, with the continuous period of the reference clock having unequal duration. If the duty cycle (i.e., the ratio of on-time to period) is not 50%, the source clock is said to be asymmetric. In addition, the reference clock generator may use other techniques to generate reference clocks having non-equal consecutive time periods.

Successive time periods in the reference clock having unequal durations typically cause noise in the output clock. This noise can appear as a Reference Spur (Reference Spur) on both sides of the frequency of the output clock (output frequency). Such noise in the output clock is highly desirable to reduce.

As is well known in the art, compensation modules are used to compensate for the noise effects of such reference clock signals in PLLs. However, the compensation module itself may be a source of noise generation, at least to some extent.

Aspects of the present invention aim to reduce such noise generation by the compensation module.

Disclosure of Invention

The embodiment of the invention aims to provide a decimal-N frequency division phase-locked loop and a system, which can improve the precision of compensating errors caused by reference signals with unequal continuous periods in the decimal-N frequency division phase-locked loop.

To solve the above technical problem, an embodiment of the present invention provides a fractional-N pll, including: a phase detector for generating an error signal representative of a phase difference between a reference clock and a feedback clock, wherein successive cycles of the reference clock have unequal durations; a low pass filter for receiving the error signal and filtering the error signal to generate a filtered error signal; a controlled oscillator for receiving the filtered error signal and generating an output clock having an output frequency proportional to the strength of the filtered error signal; a fractional-N divider module to receive the output clock, the fractional-N divider module to divide a frequency of the output clock by a desired division factor to generate a feedback clock, wherein the desired division factor has a first integer portion and a first fractional portion, wherein the frequency of the output clock divided by the desired division factor is designed to make the output frequency equal to a product of the reference frequency and the desired division factor; and a compensation module for generating a compensation factor to compensate for the effect of successive cycles of unequal duration of the reference clock, wherein the compensation factor has a second integer part and a second fractional part, wherein the fractional-N divider module is designed to generate a modified division factor by combining a desired division factor and the compensation factor, wherein the compensation module comprises: a correction module for generating a correction signal, the correction signal including a first frequency correction factor constituting a first period and a second frequency correction factor constituting a second period of each pair of successive periods, the correction signal further including a dc noise component; and a filter for removing the noise component from the correction signal to generate a compensation factor including the first frequency correction factor and the second frequency correction factor.

Additionally, wherein the fractional-N divider module comprises: a frequency dividing circuit for dividing the output clock by a sequence of divisor values to generate a feedback clock, wherein each divisor value is an integer; and a division factor generator for generating a sequence of divisor values, wherein an output of the filter is provided as an input to the division factor generator.

Further wherein the division factor generator is a Delta-Sigma modulator.

In addition, a phase error signal generator for generating a phase error signal between the reference clock and the feedback clock, the phase error signal being due to successive periods of unequal duration; a differentiator for generating a frequency error value based on the phase error signal; and a correlation sequence generator for generating a correlation sequence, wherein one value of the correlation sequence indicates the beginning of a smaller time segment in the successive periods, and wherein another value of the correlation sequence indicates the beginning of a larger time segment in the successive periods, wherein quantization noise caused by the Delta Sigma modulator causes at least part of the noise, the phase error signal generator, the differentiator, and the correlation sequence generator cause circuit noise, wherein the frequency error value is multiplied by the correlation sequence to generate a correction signal.

In addition, wherein the compensation module further comprises: a second filter coupled to receive the output of the differentiator and designed to reduce errors introduced by the phase error signal generator, the differentiator and the quantization noise; a gain module; and an accumulator, wherein the gain module and the accumulator are located between the filter and the second filter to provide the correction signals together in amplified form to the filter.

In addition, wherein the division factor generator includes: a splitter for generating a corresponding integer portion and a corresponding fractional portion, a sum of the corresponding integer portion and the corresponding fractional portion being equal to a sum of the compensation factor and the desired division factor, wherein the corresponding integer portion contains at least a portion of an integer value generated by summing the compensation factor and the first fractional portion, a modulator core designed to generate an integer logic stream corresponding to each corresponding fractional portion, wherein the integer logic stream represents a size of the corresponding fractional portion in the density domain, wherein each integer of the logic stream is added to the corresponding integer portion to generate a corresponding divisor value of the sequence of divisor values.

Additionally, wherein the corresponding integer portion contains all integer values generated by the summing.

Further, wherein the modulator is a Delta Sigma modulator having a signal transfer function, wherein the signal transfer function is configured to: if the value of the input signal transfer function is an integer, the output value of the signal transfer function is also an integer.

In addition, the division factor generator further includes a delay unit for acquiring the delay value so that the corresponding integer part is delayed by the delay value.

In addition, the filter is a two-tap comb filter.

Correspondingly, the embodiment of the invention also provides a system, which comprises: a timing card for generating a reference clock; a line card for receiving data packets and retiming the data packets with reference to an output clock and transmitting the retimed data packets, wherein the line card comprises a fractional-N pll for receiving the reference clock, the fractional-N pll providing the output clock based on the reference clock, wherein successive cycles of the reference clock have unequal durations, wherein the fractional-N pll is any one of the fractional-N plls described above.

Drawings

Example embodiments of the invention are described below with reference to the accompanying drawings, which are briefly described below.

Fig. 1 is a block diagram of a first phase-locked loop in a fractional-N pll according to an embodiment of the present invention.

Fig. 2 shows a timing diagram of frequency multiplication to generate a reference clock.

Fig. 3A depicts a timing diagram of a phase error caused by an asymmetric source clock.

Fig. 3B depicts a graph of a histogram of phase error at the input of a phase detector for one type of asymmetry of the reference clock according to an embodiment of the present invention.

Fig. 3C depicts a graph of a histogram of phase error at the input of a phase detector for another asymmetric value of the reference clock according to an embodiment of the present invention.

FIG. 3D depicts a graph of a histogram of phase error correspondences at the phase detector input for yet another asymmetric value of the reference clock in accordance with an embodiment of the present invention.

Fig. 4 is a block diagram of a Phase Locked Loop (PLL) including a compensation module according to an embodiment of the present invention.

Fig. 5 is a block diagram of a division factor generator provided according to an embodiment of the present invention.

Fig. 6A is a block diagram of a first order Delta Sigma Modulator (DSM) in a fractional-N pll according to an embodiment of the present invention.

Fig. 6B is a block diagram of a fractional-N pll according to an embodiment of the present invention.

FIG. 7A is a block diagram of a compensation module according to an embodiment of the invention.

FIG. 7B is a timing diagram of signals at some nodes of the compensation module of an embodiment of the present invention.

FIG. 8 is a block diagram of a simplified view of a compensation module of an embodiment of the present invention.

Fig. 9 is a graph of the response of a Direct Current (DC) return-to-zero filter in the compensation module according to an embodiment of the invention.

Fig. 10 is a graph of phase noise versus frequency for the output clock of various combinations of compensation loop filter configurations in accordance with an embodiment of the present invention.

Fig. 11 is a block diagram of an exemplary system that employs a PLL in one embodiment of the invention.

In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.

Detailed Description

One aspect of the present invention improves the accuracy of compensating for errors caused by a reference signal having consecutive periods of unequal duration in a fractional-N Phase Locked Loop (PLL). In an embodiment, the compensation module generates a compensation factor based on the correction module and the filter. The correction module is configured to generate a correction signal comprising a first frequency correction factor and a second frequency correction factor. The first and second frequency correction factors are for the first and second periods. The first period and the second period constitute each pair of successive periods, and the correction signal contains a direct current noise component.

The filter is used for removing the direct current noise component from the correction signal to generate a compensation factor containing a first frequency correction factor and a second frequency correction factor. The generated compensation factor can be used for being input into a frequency division factor generator of a frequency divider module in the fractional-N frequency division phase-locked loop, so that the signal output by the fractional-N frequency division phase-locked loop has no frequency error or small frequency error.

Several aspects of the invention are described below with reference to examples. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown in detail to avoid obscuring aspects of the invention. Furthermore, although only some of the various combinations are described herein for brevity, the described features/aspects may be practiced in various combinations.

Fig. 1 is a block diagram of a first phase-locked loop in a fractional-N pll according to an embodiment of the present invention. The first Phase-locked loop 100 includes a Crystal Oscillator (XO) 105, a buffer 110, a Delay Element (Td) 115, an XNOR 120, a Phase Detector (PD) 125, a Charge Pump (CP) 130, a Low-Pass Filter (LPF) 135, a Voltage-Controlled Oscillator (VCO) 140, a first Frequency Divider (DIV) 150, a second Frequency divider 155, and a fractional-N divider module 170. fractional-N divider module 170, in turn, comprises a first frequency dividing circuit 160 and a first Dela-Sigma modulator (Frac DSM) 165. The components and modules of fig. 1 are shown by way of illustration only. In other embodiments, the first phase-locked loop 100 may contain more modules, fewer modules, or modules implemented in a different manner. For example, the first phase-locked loop 100 may be implemented as an all-Digital PLL, wherein the phase detector 125 is implemented as a Time-to-Digital Converter (TDC), the charge pump 130 is omitted, and the Digital filter is implemented as a Digitally-Controlled Oscillator (DCO) instead of the low-pass filter 135 and the voltage-Controlled Oscillator 140. The first phase-locked loop 100 may also be implemented using a combination of analog and digital blocks, as will be apparent to those skilled in the relevant art.

The crystal oscillator 105 is a crystal oscillator (source clock source) that generates a periodic signal (source clock) having a desired frequency. The periodic signal is buffered by buffer 110 and forwarded by buffer 110 on path 112 as the source clock (CLK-XO-MAIN). The source clock is delayed by delay unit 115 and a delayed clock is generated on path 113. The Exclusive-OR gate 120 performs an Exclusive-OR (Exclusive-NOR) logic operation of the source clock and the delayed clock to generate a reference clock 122 (CLK-REF-N). The exclusive-nor operation of the source clock and the delayed clock results in the reference clock 122 being twice as frequent as the source clock. Other methods may be used to generate a reference clock of similar characteristics.

Phase detector 125 generates an error signal that represents the phase difference between reference clock 122 and first feedback clock 162. In one embodiment, the phase difference is obtained based on the time of occurrence of the falling edges of the reference clock 122 and the first feedback clock 162. The error signal drives a current source and sink in the charge pump 130, and the charge pump 130 generates a current proportional to the strength of the error signal (including the amplitude and signal). The low pass filter 135 converts the current to a voltage and low pass filters the voltage to generate a filtered error signal as an output. The voltage controlled oscillator 140 receives the filtered error signal and generates a first output clock 141, the frequency of the first output clock 141 being determined by the strength of the filtered error signal. Among them, a voltage controlled oscillator may be taken as an example of the controlled oscillator.

The fractional-N divider module 170 divides the frequency of the first output clock 141 by a desired division factor (fractional or integer) to generate the first feedback clock 162. The desired division factor has a first integer portion and a first fractional portion, and the value of the desired division factor employed by the fractional-N divider module 170 determines the steady-state frequency of the first output clock 141. If the desired division factor is represented by a fraction M.N, the frequency of the first output clock 141 is equal to the product of M.N and the frequency of the reference clock 122 (the reference frequency). M is a first integer portion, N is a first fractional portion, and ". quadrature" denotes a fractional point, M.N denotes a desired division factor for obtaining the first output clock 141 at a desired frequency. The fractional-N divider block 170 includes a first Division circuit (DIVN) 160 and a first Dela-Sigma modulator 165. The first Dela-Sigma modulator 165 receives a division factor M.N on path 161 (e.g., from a user input or from an external device). Based on the value M.N, the first Dela-Sigma modulator 165 generates a sequence of divisor values (all integers) on path 166, where the sequence of divisor values may be generated by a division factor generator. Each cycle of the reference clock 122 uses a divisor value of the sequence of divisor values as the value by which the first frequency divider circuit 160 should divide the frequency of the first output clock 141. The moment at which the first Dela-Sigma modulator 165 forwards the next divisor value of the sequence of divisor values is indicated by a valid edge of the first feedback clock 162, the first feedback clock 162 also being applied to the clock input of the first Dela-Sigma modulator 165. The first Dela-Sigma modulator 165 may be operated in a known manner.

In order to minimize jitter in the output clock 141 and minimize quantization noise generation of the first Dela-Sigma modulator 165 and noise generation of the voltage controlled oscillator 140 caused by jitter in the first clock (CLK 1) 151 and the second clock (CLK 2) 156, a reference clock having a high frequency is required, wherein the first clock 151 and the second clock 156 are obtained from the first output clock 141 by frequency division in the first frequency divider 150 and the second frequency divider 155, respectively. Based on this, a clock multiplier (here implemented by a combination of delay element 115 and exclusive-or gate 120) is typically used in high performance (i.e., low jitter) fractional-N frequency synthesis applications to generate a reference clock that is twice the source clock frequency.

Fig. 2 shows a timing diagram of frequency multiplication to generate a reference clock. At time T21 and time T22, a pair of edges of the source clock 10 and the delayed clock 20 are shown. The exclusive nor operation of the exclusive nor gate 120 results in the generation of a reference clock 122 having a frequency twice the source clock frequency. Signal 210 represents the result of an exclusive or (XOR) operation on the source clock and delayed clock 20. Such techniques are well known.

A non-50% duty cycle (i.e., asymmetry) of the source clock (generated by the crystal oscillator) prior to the frequency multiplier will result in large phase error perturbations of the opposite signal alternating between successive reference clock (reference clock 122) edges. This is because reference clock 122 will have successive periods that alternate between shorter and longer periods, as shown below with reference to fig. 3A. Even in a steady state (i.e., when the first phase-locked loop 100 is locked to the reference clock 122 and is generating the first output clock 141 having the desired frequency), the phase error disturbance causes subsequent modules (PD, CP, LPF, VCO) to cause a non-linear fold-back of the quantization noise of the first Dela-Sigma modulator 165 in-band (i.e., within the bandwidth of the first phase-locked loop 100), thereby increasing the overall jitter in the first output clock 141.

In addition, even without using a source clock and a frequency multiplication to generate the reference clock, the reference clock generator may use other techniques for generating the reference clock with non-equal consecutive time periods. Again, this may result in phase error perturbations, noise foldback, and an increase in overall jitter in first output clock 141.

Fig. 3A to 3D show such a fold-back. Specifically, fig. 3A depicts a timing diagram of phase errors caused by an asymmetric source clock, and fig. 3B-3D depict graphs of histograms corresponding to phase errors at the phase detector inputs for three different asymmetric values of a reference clock, in accordance with an embodiment of the present invention. Wherein, the three different asymmetry values of the reference clock are respectively 50%, 49% and 45% of the duty ratio of the reference clock.

In fig. 3A, the source clock 10 has a duty cycle (i.e., asymmetry) that is not 50%. The doubling operation results in the reference clock 122 having unequal consecutive periods (T32-T33 and T33-T35). However, since the first output clock 141 always has a 50% duty cycle, the first feedback clock 162 will also always have nominally the same continuous time period except for the fractional-N Delta Sigma modulator-related phase shift. In steady state, the falling edge of the reference clock 122 and the falling edge of the first feedback clock 162 are not aligned. For example, the reference clock falling edge is earlier than the falling edge of the first feedback clock 162 in intervals T31-T32, and later than the falling edge of the first feedback clock 162 in intervals T33-T34. As described above, this alternating pattern repeats, resulting in a non-zero output of the phase detector 125, and subsequent effects in other parts of the feedback loop of the first phase locked loop 100. Fig. 3B, 3C, and 3D show the phase error distribution (approximately zero) at the input of phase detector 125 for reference clock duty cycles of 50%, 49%, and 45%, respectively. In each of fig. 3B to 3D, the y-axis represents the magnitude of the phase error, and the x-axis represents the frequency at which the phase error occurs.

Deviation from the ideal 50% duty cycle of the source clock 10 results in an increase in the amount of quantization noise (due to the inherent operation of the first Dela-Sigma modulator 165) folding back (into the bandwidth of the first phase locked loop 100). Based on this, jitter in the first output clock 141 increases. Wherein the greater the deviation from the 50% duty cycle (i.e., the duty cycle is greater or less than 50%), the greater the foldback and jitter. Therefore, it is generally necessary to compensate for the duty error of the source clock. Although the following description is provided with a non-50% duty cycle and frequency multiplication of the source clock, the description and techniques are equally applicable to the case where the reference clock generator itself generates the reference clock with non-equal consecutive time periods.

Compensation for non-50% (asymmetric) duty cycles of the source clock (when a multiple of the frequency of the source clock is used to generate the reference clock) and the resulting effect of increased phase noise (jitter) in first output clock 141 may be performed in one of a number of ways. For example, one approach corrects the source clock itself by using delay cells with corresponding delays to eliminate the asymmetry in the source clock. However, this approach can be very difficult in practice and can result in additional noise loss. A better approach is to sense a non-50% duty cycle (duty cycle error) in the source clock by extracting the signal sequence of the phase detector 125 and use this information to modulate the first Dela-Sigma modulator 165 to compensate for the source clock duty cycle error. This method is used in the embodiments of the present invention and is explained with reference to fig. 4 and 5.

Fig. 4 is a block diagram of a phase locked loop including a compensation module according to an embodiment of the present invention. The implementation of the second phase locked loop 400 is the same as the implementation of the first phase locked loop 100 of fig. 1, except that a duty cycle compensation module is added and a modification to the first Dela-Sigma modulator of the first phase locked loop 100 is added. Therefore, for simplicity, only the duty cycle compensation module and the modified second Dela-Sigma modulator are described next. CLK-OUT441 represents an output clock that is substantially free of noise due to asymmetric source clock 10.

The duty cycle compensation module (or simply compensation module 410) operates to sense a non-50% duty cycle (duty cycle error) in the source clock and generate a compensation factor to compensate for the non-50% duty cycle. The compensation module 410 receives the reference clock 122 and the second feedback clock 462. Based on processing of both inputs, the reference clock 122 and the second feedback clock 462, the compensation module 410 generates and provides compensation factors to the second Dela-Sigma modulator 465 on path 416. The compensation factor is of the form a.b, where a and B are the second integer part and the second fractional part, respectively, and a.b can be a positive or negative decimal number. A may be equal to 0. An example implementation of the compensation module 410 that processes the reference clock 122 and the second feedback clock 462 is used in an embodiment of the present invention and is described in the following sections. However, in other embodiments, in general, the compensation module 410 may be implemented using other techniques, such as by processing other signals in the second phase locked loop 400, such as the output of the source clock 10 or the phase detector 125, as will be apparent to those skilled in the relevant art.

In the fractional-N divider block 470, the second frequency divider circuit 460 and the path 461, the second feedback clock 462 and the path 466 are similar or identical to the first frequency divider circuit 160 and the path 161, the first feedback clock 162 and the path 166 of the first phase locked loop 100 in fig. 1, and their description will not be repeated here for the sake of brevity. The second Dela-Sigma modulator 465 (Delta-Sigma modulator or in general a division factor generator) is a modified Dela-Sigma modulator (which has been enhanced or modified when compared to the first Dela-Sigma modulator 165 of fig. 1). The second Dela-Sigma modulator 465 combines M.N (on path 461) with the compensation factor a.b on path 416 to enable some internal modules (specifically, modulator core 520, described below) in terms of hardware to generate a modified division factor on path 466 in a simpler and more efficient manner, as will be apparent from the description below. Specifically, second Dela-Sigma modulator 465 adds M.N to a.b to generate a modified division factor. M.N is typically a fixed value, but may vary. On the other hand, a.b may be a fixed value or may be a value that varies with time during operation of the second phase locked loop 400, and the second integer portion "a" may be zero or non-zero, as will be described below.

As is well known in the relevant art, the Delta Sigma modulator generates a string of numbers representing an integer logic flow representing the order of the input fraction (the sum of path 161 in fig. 1, M.N and a.b in fig. 4) in the "density domain". That is, the output stream is such that the density of the logical stream is greater for larger input values and smaller for smaller input values. Likewise, when the Delta-Sigma modulator output is represented by a logical stream of Multi-bit outputs (relative to a single-bit output), higher values in the logical stream are also denser when there are more higher input values than lower input values in the logical stream. Thus, the division factor generator may be used to generate and output a logic stream, which is used for input into the "density domain".

Next, a specific structural implementation of the second Dela-Sigma modulator 465 and the manner in which the second Dela-Sigma modulator 456 of the present disclosure modifies the desired division factor M.N by adding a compensation factor a.b is described.

Fig. 5 is a block diagram representation of a division factor generator provided in accordance with an embodiment of the present invention. A second Dela-Sigma modulator 465 includes a splitter 510, an integer transform module 530, a modulator core 520, and an adder 540.

Splitter 510 receives desired division factor M.N on path 461 and compensation factor a.b on path 416, each of which may be represented by multiple bits according to known conventions. Splitter 510 combines the division factor and the compensation factor by:

1) adding the numbers N and B to obtain decimal C.D

2) The numbers C, M and a are added to give a third integer part W.

3) The third integer part W is forwarded on path 513 (INT).

4) The third fractional portion D is forwarded on path 512 (DEC).

The above-described bonding process is now illustrated by way of example. Assume M.N is 5.6 and a.b is 4.7. Adding N and B (i.e., 6 and 7) yields a c.d equal to 1.3. D (i.e., 3) is forwarded on path 512. C, M and A (i.e., 1, 4, and 5) are added to obtain 10, which is forwarded on path 513 as 10.

In the above combining process, only the summed fractional part of M.N and A.B is forwarded to modulator core 520 on path 512, while all the resulting integer part is forwarded on path 513.

The combined M.N and a.b process described above provides the benefits of: if no compensation factor is applied or needed (i.e., as shown in FIG. 1), then the design of the modulator core 520 need not be changed or enhancements to the modulator core 520 are minimal, as described below with reference to FIGS. 6A, 6B.

Fig. 6A is a block diagram of a first order Delta Sigma modulator in a fractional-N pll according to an embodiment of the present invention, as is well known in the relevant art. A first order Dela-Sigma modulator 600 receives the signal (in digitized form) and generates as output a logic stream of numbers y n. W [ n ] is the output of the integration operation. The first order DSM comprises: adder 610, subtractor 620, single-sample delay unit 630, and quantizer 640. Fig. 6B is a block diagram of a third order multi-stage noise shaping Delta Sigma modulator in a fractional-N pll according to an embodiment of the invention, consisting of three DSMs, each DSM similar to or identical to the first order Dela-Sigma modulator 600 of fig. 6A, with additional components as shown in fig. 6B. Each of the blocks 665 is a single sample delay unit. Further comprising: a digital differentiator 680, and an adder 670. x [ n ] and y [ n ] are the input signal and output logic streams, respectively.

With continued reference to fig. 5, modulator core 520 performs a Delta Sigma operation to generate a logic flow on path 524 that corresponds to the input signal to modulator core 520. In an embodiment of the invention, the modulator core 520 may act as a third order multi-stage noise shaping Delta-Sigma modulator. However, in other embodiments, other types of modulator cores may be used if the Signal Transfer Function (STF) output based on the modulator core is also an integer for integer inputs.

An integer transform module 530 receives the input on path 513 and transforms the input in a manner specified by the Signal Transfer Function (STF) of the modulator core 520. As described above, the STF must have the properties of: for integer inputs, the output is always only 1 or more integers. When the modulator core 520 is implemented as a third order multi-stage noise shaping Delta Sigma modulator, the STF is a dual sample delay unit, i.e., STF = Z ^-2 . The delay unit is used for obtaining a delay value, so that the corresponding integer part is delayed by the delay value. In general, the value of the delay, or "n", is typically determined by the order of the modulator core 520, n =1 for the second order, n =2 for the third order, and so on.

The integer transform module 530 forwards the transformed input values on path 534. It is noted here that the first integer part M of the desired division factor may also be converted by the integer transform module 530.

Adder 540 adds the pair of values received on respective paths 534 and 524 (at respective times) and forwards the resulting sum on path 466. The summation is a sequence of divisor values provided to the second frequency-dividing circuit 460 for frequency division of the VCO output (i.e., the CLKOUT signal).

To achieve the highest value of duty cycle correction, an additional 4-bit width would need to be input on path 512 for a third order multi-stage noise shaping Delta Sigma modulator. As such, a 2-bit quantizer implemented in each of the three first order DSMs (the first order Dela-Sigma modulator 600 of fig. 6B) would need to become 5 bits. Accordingly, one or more internal digital paths and the modules of FIG. 6B need to be added accordingly.

Therefore, the modulator core 520 must be redesigned or upgraded to support these changes. However, by combining M.N and a.b as described above, the input range of modulator core 520 remains the same as when no compensation factor is applied or used, and no modification to modulator core 520 is required, i.e., the input range of modulator core 520 designed such that when no compensation factor is needed or used can be reused without any modification. Thus, the combining technique is very efficient.

The implementation of the compensation module in the embodiment of the present invention is described next.

FIG. 7A is a block diagram of a compensation module according to an embodiment of the invention. Compensation module 410 includes D flip-flop 801, D flip-flop 805, D flip-flop 810, differentiator 815, multiplier 825, filter 830, accumulator 835, multiplier 840, dc return to zero filter 845, D flip-flop 850, third Dela-Sigma modulator 860, divide-by-two module 865, and D flip-flop 870 and D flip-flop 875. A dc return-to-zero filter is exemplified as the second filter, among others, which is coupled to receive the output of the differentiator and is designed to reduce errors introduced by the phase error signal generator, the differentiator and the quantization noise. Figure 7B is a timing diagram of the signals at some nodes of the compensation module of one embodiment of the present invention, specifically illustrating exemplary waveforms of the source clock 10, the CLK-XO signal 851, the reference clock 122, the first feedback clock 162, the CLK-XO/2 signal 866, the SIGN [ N ] signal 811, and the correlation sequence signal. The operation of the compensation module 410 will now be briefly described with reference to fig. 7A and 7B. The specific details of the compensation module 410 are set forth by way of illustration only, and various modifications or alternatives to the design and module will be apparent to those skilled in the relevant arts upon reading the disclosure herein.

Referring to fig. 7A, the D flip-flop 801 generates a signal of a duty error (i.e., positive or negative) as an output signal 802 at each cycle of the reference clock 122, the output signal 802 being obtained by sampling the reference clock at a falling edge of the first feedback clock 162. Similar to what is pointed out with reference to fig. 3A, the duty cycle error (especially during steady state operation of the second phase locked loop 400) causes the phase difference to alternate between positive and negative in successive cycles of the reference clock. The reference clock 122 is inverted before being provided as an input to the D flip-flop 801. CLK-XO signal 851, which is an inverted value of reference clock 122, is used as the clock input for D flip-flop 870, D flip-flop 875, D flip-flop 805, D flip-flop 810, and D flip-flop 850. Output signal 802 is passed through D flip-flop 805 and D flip-flop 810 (for clock domain cross synchronization) and forwarded as SIGN [ N ] signal 811. SIGN [ N ] signal 811 is passed through differentiator 815. The SIGN [ N ] signal is forwarded by differentiator 815 and provided as an input to multiplier 825.

It can be observed from FIG. 7B that the phase error is negative when the reference clock 122 lags the first feedback clock 162 (e.g., during time interval t81-t 82) and positive when the reference clock 122 leads the first feedback clock 162 (e.g., during time interval t83-t 84). It is to be noted here that the positive phase error and the negative phase error may be replaced with each other, that is, a positive phase error when the reference clock 122 lags the first feedback clock 162, and a negative phase error when the reference clock 122 leads the first feedback clock 162.

Divide-by-two module 865 divides CLK-XO signal 851 by 2 to generate CLK-XO/2 signal 866, CLK-XO/2 signal 866 is passed through D flip-flop 870 and D flip-flop 875 (D flip-flop 870 and D flip-flop 875 together provide the function of a synchronizer) to generate CORR-SEQ N signal 876 (the correlation sequence signal), and CORR-SEQ N signal 876 is forwarded as input to multiplier 825 and multiplier 840. The CORR-SEQ N signal 876 represents one half of the "current" clock period of the source clock 10 (i.e., at the current running time of the compensation module 410 and the second phase locked loop 400), or equivalently, the correlation sequence signal represents one of the two current unequal clock periods of the reference clock 122.

Referring to one half cycle of the source clock 10 as an odd cycle (e.g., interval t82-t 83) and the other half cycle (e.g., interval t83-t 85) as an even cycle, a logic value of 1 of the correlation sequence signal indicates that the current half cycle is an odd cycle, and a value of 0 indicates that the current cycle is an even cycle. As will be appreciated from the following description, the correlation sequence signal is required to accurately identify the start of each pair of unequal consecutive periods of the reference clock 122, and the generation or available time of the corresponding correction factors generated at the various nodes in the compensation module 410 may not be aligned with the start of each pair of unequal consecutive periods of the reference clock 122 based on the delay/noise in one or more blocks in the correction path from the D flip-flop 801 to the input of the third Delta Sigma modulator 860. The delta-f generated by the correlation sequence signal at the input of each of multiplier 825 and multiplier 840 is also required to be multiplied by either +1 or-1 to properly generate the final + delta-f and-delta-f values.

Example waveforms of the source clock 10 (also referred to as CLK-XO-MAIN), CLK-XO signal 851, reference clock 122 (also referred to as CLK-REF-N), and first feedback clock 162 (also referred to as CLK-DIV-N) are shown in fig. 7B. Their example values may be determined by referring to the graph of fig. 7A.

As can be seen from the above description and fig. 3A, for each shorter time period of the reference clock 122, it is necessary to correct it by shortening the time period of the feedback clock. Similarly, for each longer time period of the reference clock 122, the time period of the feedback clock needs to be extended for correction. Accordingly, all cycles of the reference clock 122 are aligned with all cycles of the first feedback clock 162, thereby eliminating noise generation. The compensation module 410 performs the above correction by generating a correction factor + Delta-f/-Delta-f on path 852 (input to the third Delta Sigma modulator 860) to decrease/increase the divide value of the second divide circuit 460. As can be appreciated from the above description, the two correction factors have equal magnitude but opposite signals.

In operation, the output signal 802 is first converted to a frequency error value by a differentiator 815 and then correlated with the correlation sequence signal (by multiplication in multiplier 825) to sense the duty cycle error. The product value generated by multiplier 825 is first filtered by filter 830 (to eliminate noise increase due to DSM quantization noise and noise introduced by earlier elements in the circuit (e.g., D flip-flop 801, D flip-flop 805, etc.)). The filtered product value is then accumulated in accumulator 835 to generate an accumulated steady-state value on path 836. The values on path 836 are again correlated with the correlation sequence signal by multiplier 840 to generate correction factors of the same magnitude but alternating signals for similar reasons as described above.

The output of multiplier 840 is represented as a compensation factor generated by the compensation module and contains the correction values + delta-f and-delta-f at the respective time instants. In an embodiment, the output of multiplier 840 is passed directly to path 852, and thus to third Delta Sigma modulator 860. The input on path 856 in the third Delta Sigma modulator 860 represents the desired division factor M.N described above, and path 856 corresponds to path 461 of fig. 4. Thus, in this embodiment, the dc return to zero filter 845 (and D flip-flop 850) are not provided.

Adding a compensation factor to the desired division factor (in the third Delta Sigma modulator 860) nulls (equals zero) the alternating positive/negative phase error between the reference clock and the feedback clock by effectively increasing or decreasing the duration of the first feedback clock 162 in the corresponding cycle. This effect can also be equivalently viewed as decreasing and increasing the frequency of the feedback clock in corresponding successive cycles by changing (decreasing or increasing) the division factor applied by the second division circuit 460 accordingly. Thus, any additional noise caused by non-50% duty cycles of source clock 10 (or unequal durations of successive clock cycles of reference clock 122) to output clock 441 (FIG. 4) of second phase locked loop 400 is reduced or completely eliminated.

FIG. 8 is a block diagram of a simplified view of a compensation module of an embodiment of the present invention. Phase error signal generator 910 is operable to generate a phase error signal (on path 912) between the reference clock and the feedback clock received on path 901. Differentiator 920 converts the phase error to a frequency error, wherein the frequency error value is multiplied by the correlation sequence to generate a correction signal, specifically the frequency error is multiplied by +1 (on path 923) or-1 by multiplier 940 to generate positive and negative correction values at the input of multiplexer 930. The multiplexer 930 forwards either positive correction values (when the value of the correlation sequence 931 is 0) or negative correction values (when the value of the correlation sequence 931 is 1). The respective values of the correction values are passed through gain module 950 and accumulator 960. Based on the current value of correlation sequence 931, the output of accumulator 960 is multiplied by either +1 (on path 968) or-1 (multiplier 970) to provide positive and negative correction values (+ delta-f and-delta-f) at the corresponding correct times on path 981.

Referring again to FIG. 7A, in other embodiments, a DC return-to-zero filter 845 is introduced between the output of the multiplier 840 and the third Delta-Sigma modulator 860, according to another aspect of the present invention. D flip-flop 850 acts as a pipeline element to turn off the digital timing of high speed operation. The beneficial effects of introducing the dc return-to-zero filter 845 are as follows: noise induced by the signal at and/or near zero hertz, which may be due to duty cycle error caused by the mixing operation of multiplier 840 and/or any residual noise caused by one or more components in the correction path, is reduced or eliminated at path 852. The duty cycle error on path 852 will result in a fixed frequency error (offset) in the frequency of output clock 441. Dc return-to-zero filter 845 effectively completely eliminates this error frequency offset. Thus, the introduction of the dc return-to-zero filter 845 causes the second phase locked loop 400 to synthesize a frequency to have zero (or minimal) frequency error and minimal near carrier phase noise at the final clock output (i.e., output clock 441). In fig. 8, the second dc return-to-zero filter 990 corresponds to the dc return-to-zero filter 845 of fig. 7A. Although an equivalent device of the filter 830 is not shown in fig. 8, an equivalent device of the filter 830 may be added.

In an embodiment, the dc return to zero filter 845 may be a two-tap comb filter. FIG. 9 is a graph of the response of the DC return to zero filter in the compensation module according to one embodiment of the present invention. In fig. 9, the y-axis represents the amplitude of the transfer function and the x-axis represents the frequency. Curve 1010 shows a portion of an example transfer function of the two-tap comb filter described above. It can be observed that the amplitude response of the transfer function at zero hertz is null (zero).

Fig. 10 is a graph of phase noise versus frequency for the output clock of various combinations of compensation loop filter configurations in accordance with an embodiment of the present invention. Curve 1110 shows the phase noise when filter 830 and dc return to zero filter 845 are not used in compensation module 410. Curve 1120 shows phase noise when only filter 830 is used, where filter 830 is a two tap filter. Curve 1130 shows the phase noise when filter 830 and dc-null filter 845 are used. It can be observed that the phase noise performance is best when filter 830 and dc return to zero filter 845 are used in combination.

The second phase locked loop 400 implemented as described above may be incorporated into a larger device or system as briefly described below.

Fig. 11 is a block diagram of an exemplary system employing a PLL in an embodiment of the invention that incorporates a TDC having a counter and counting logic implemented in accordance with various aspects of the invention, as described in detail above. The embodiment of the invention discloses a system, which comprises: a timing card for generating a reference clock; a line card for receiving data packets and retiming the data packets with reference to an output clock and transmitting the retimed data packets, wherein the line card comprises a fractional-N pll for receiving the reference clock, the fractional-N pll providing the output clock based on the reference clock, wherein successive cycles of the reference clock have unequal durations, wherein the fractional-N pll is the fractional-N pll provided by the above embodiments. The system 1200 includes 2 SyncE (synchronous ethernet) timing cards, where the two timing cards are denoted as timing card 1210 and timing card 1220, respectively. Further comprising: line card 1 through line card N, of which only two, line card 1230 and line card 1250, are shown for simplicity. In particular, linecard 1230 includes a first jitter attenuator phase-locked loop 1240 and a first synchronous ethernet physical layer transmitter (SyncEPHY TX) 1245. Line card 1250 includes a second jitter attenuator phase-locked loop 1260 and a second synchronous ethernet physical layer transmitter 1265. The components of fig. 11 may operate in accordance with the synchronous ethernet network standard. As is well known in the related art, SyncE is a physical layer-based technology for implementing synchronization in a data packet-based ethernet network. The synchronized clock signal transmitted over the physical layer should be traceable to an external master clock (e.g., from a timing card such as timing card 1210 or timing card 1220), which in some embodiments may be a reference clock. Thus, the ethernet data packets are retimed by the master clock and then transmitted in the physical layer. Thus, data packets (e.g., on path 1231 and path 1251) are retimed and transmitted without any time information being recorded in the data packets. These data packets may be generated by corresponding applications, such as IPTV (Internet Protocol Television), VoIP (Voice over Internet Protocol), and the like.

Thus, line card 1230 receives data packets on path 1231 and forwards the data packets on output path 1246 after the data packets have been retimed (synchronized) to the master clock. Similarly, line card 1250 receives data packets on path 1251 and forwards the data packets on output path 1266 after the data packets have been retimed (synchronized) to the master clock.

A master clock 1211 (clock-1) is generated by the timing card 1210. Timing card 1220 generates a redundant clock 1221 (clock-2) that line card 1230 and line card 1250 will use when primary clock 1211 fails. Master clock 1211 and redundant clock 1221 are provided to each of line card 1230 and line card 1250 through backplane 1270.

In line card 1230, the first jitter attenuator phase-locked loop 1240 is implemented as a second phase-locked loop as described in detail above. The first jitter attenuator phase-locked loop 1240 generates an output clock 1241, the output clock 1241 being used to synchronize (retime) data packets, where the data packets are first received via path 1231, retimed by the output clock 1241, and forwarded on output path 1246.

Similarly, in line card 1250, the second jitter attenuator phase-locked loop 1260 is implemented as the second phase-locked loop 400 described in detail above. The second jitter attenuator phase lock loop 1260 generates an output clock 1261, the output clock 1261 being used to synchronize (retime) data packets, where the data packets are first received via path 1251, retimed by the output clock 1261, and forwarded on an output path 1266.

Reference throughout this specification to "one embodiment," "an embodiment," or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases "in one embodiment," "in an embodiment," and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

In the illustrations of fig. 1, 4, 5, 6A, 6B, 7A, 8, and 11, although the terminals/nodes are shown as being directly connected to (i.e., "connected to") various other terminals, it should be recognized that additional components (as appropriate for the particular environment) may also be present in the path, and thus, the connections may be considered to be "electrically coupled" to the same connected terminals.

In this application, the power supply and the ground are referred to as constant reference potentials.

While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present invention should not be limited by any of the above-described embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A fractional-N pll comprising: a phase detector for generating an error signal representative of a phase difference between a reference clock and a feedback clock, wherein successive cycles of the reference clock have unequal durations; a low pass filter to receive the error signal and filter the error signal to generate a filtered error signal; a controlled oscillator for receiving the filtered error signal and generating an output clock having an output frequency proportional to the strength of the filtered error signal; it is characterized by also comprising:

a fractional-N divider module to receive the output clock, the fractional-N divider module to divide a frequency of the output clock by a desired division factor to generate the feedback clock, wherein the desired division factor has a first integer portion and a first fractional portion,

wherein the frequency of the output clock divided by the desired division factor is designed to make the output frequency equal to the product of the reference frequency and the desired division factor; and

a compensation module to generate a compensation factor to compensate for an effect of successive periods of unequal duration of the reference clock, wherein the compensation factor has a second integer portion and a second fractional portion,

wherein the fractional-N divider module is designed to generate a modified division factor by combining the desired division factor and the compensation factor,

wherein the compensation module comprises:

a correction module for generating a correction signal comprising a first frequency correction factor constituting a first period and a second frequency correction factor constituting a second period of each pair of said successive periods, said correction signal further comprising a dc noise component; and

a filter to remove the noise component from the correction signal to generate the compensation factor including the first frequency correction factor and the second frequency correction factor.

2. The fractional-N pll of claim 1, wherein the fractional-N divider module comprises:

a frequency dividing circuit for dividing the output clock by a sequence of divisor values to generate the feedback clock, wherein each divisor value is an integer; and

a division factor generator for generating the sequence of divisor values,

wherein an output of the filter is provided as an input to the division factor generator.

3. The fractional-N pll of claim 2, wherein the division factor generator is a Delta Sigma modulator.

4. The fractional-N pll of claim 3, wherein the compensation module comprises:

a phase error signal generator for generating a phase error signal between the reference clock and the feedback clock, the phase error signal being due to successive periods of the unequal duration;

a differentiator for generating a frequency error value based on the phase error signal; and

a correlation sequence generator for generating a correlation sequence, wherein one value of the correlation sequence indicates the start of a smaller time period in the successive cycles, and wherein another value of the correlation sequence indicates the start of a larger time period in the successive cycles,

wherein quantization noise caused by the Delta-Sigma modulator causes at least part of the noise, the phase error signal generator, the differentiator and the correlation sequence generator cause circuit noise,

wherein the frequency error value is multiplied by the correlation sequence to generate the correction signal.

5. The fractional-N pll of claim 4, wherein the compensation module further comprises:

a second filter coupled to receive the output of the differentiator and designed to reduce errors introduced by the phase error signal generator, the differentiator and the quantization noise;

a gain module; and

the number of the accumulators is increased by the number of the accumulators,

wherein the gain module and accumulator are located between the filter and the second filter to provide the correction signals together in amplified form to the filter.

6. The fractional-N pll of claim 5, wherein the division factor generator comprises:

a splitter for generating a corresponding integer portion and a corresponding fractional portion, the sum of the corresponding integer portion and the corresponding fractional portion being equal to the sum of the compensation factor and the desired division factor,

wherein the corresponding integer portion comprises at least a portion of an integer value generated by summing the compensation factor and the first fractional portion,

a modulator core designed to generate an integer logic flow corresponding to each corresponding fractional portion, wherein the integer logic flow represents a size of the corresponding fractional portion in a density domain,

wherein each integer of the logic flow is added to the corresponding integer portion to generate a corresponding divisor value of the sequence of divisor values.

7. The fractional-N pll of claim 6, wherein the corresponding integer portion contains all integer values generated by the summing.

8. The fractional-N pll of claim 7, wherein the modulator is a Delta Sigma modulator having a signal transfer function, wherein the signal transfer function is configured to: if the value of the input signal transfer function is an integer, the output value of the signal transfer function is also an integer.

9. The fractional-N pll of claim 8, wherein the division factor generator further comprises a delay unit configured to obtain a delay value such that the corresponding integer portion is delayed by the delay value.

10. A fractional-N pll as claimed in claim 2, wherein the filter is a two-tap comb filter.

11. A fractional-N pll system comprising:

a timing card for generating a reference clock;

a line card to receive and retime a data packet with reference to an output clock and transmit the retimed data packet,

wherein the line card comprises a fractional-N phase locked loop for receiving the reference clock, the fractional-N phase locked loop providing the output clock based on the reference clock, wherein successive cycles of the reference clock have unequal durations, wherein the fractional-N phase locked loop is a fractional-N phase locked loop as claimed in any one of claims 1 to 10.