JPH0653829A - Oversampling a/d converter - Google Patents

Abstract

PURPOSE:To suppress a jitter noise and to attain a high SN ratio. CONSTITUTION:This oversampling A/D converter has the 1st forward pass circuit 3, the 2nd forward pass circuit 4, a judging circuit 5, a digital PLL 6, a selector 7, and a feedback loop and constituted so as to measure a change in the quantized output of a sigma-delta type noise shaper in both cases executing and not executing phase shift in each execution of phase shift in the PLL 6. Since the probability of a sharp inclination in an analog input signal is high when a change is generated in the measurement, a phase shifting position is changed, and since the probability of a moderate inclination in the input signal is high when there is no change on the contrary, the phase shift is effectively controlled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to oversampling A.
A / D converter, especially used in the field of communication,
Moreover, the SN in the application where the quantizing jitter generated by the digital PLL is superimposed on the sampling clock.
Oversampling A suitable for improving ratio deterioration
/ D converter.

[0002]

2. Description of the Related Art Conventionally, an Σ-Δ type oversampling A / D converter has a feedback loop formed by an integrator, a quantizer (voltage comparator), a feedback D / A conversion circuit, etc. The difference between the output of the D / A converter for feeding back the quantized signal and the input signal is integrated by the quantizer, and the integrated value is quantized by the quantizer. I try to suppress it. On the contrary, it is possible to obtain a high S / N ratio by combining with a digital filter in the latter stage by taking advantage of the feature that the noise component of high frequency increases. Therefore, such an A / D converter is suitable as a front end for a digital signal processing LSI.

On the other hand, a digital type phase locked oscillator (DPL)
L) is a circuit in which all the constituent elements of the PLL are digitalized, and it is possible to realize non-adjustment and downsizing, and it is an important circuit for realizing an LSI. However, since it necessarily includes quantized jitter caused by digitally performing phase control, when used for synchronization control of a communication LSI, jitter is superimposed on the synchronization clock inside the LSI. Therefore, in the signal processing LSI of the data modem system, the above-mentioned Σ-Δ type oversampling A / D
It is necessary to synchronize the sampling clock of the converter with an external signal by this digital PLL.

FIGS. 6A and 6B are a block diagram of an oversampling A / D converter and a DPLL used therein, respectively, showing a conventional example. As shown in FIG. 6A, the conventional oversampling A / D converter includes a D / A conversion unit 2 for feeding back a quantized signal, an output of the D / A conversion unit 2 and an analog signal input. Terminal AIN
Analog differencer 1 for taking the difference from the input signal from
And a digital integrator 9 in the feedback loop. This integrator 9 is used only for a prediction type noise shaper. Further, the conventional A / D converter includes an integrator having an input capacitance Ci and an integration capacitance Cs, an operational amplifier 23 of the integrator, and a voltage comparator (quantum quantum comparator) that compares an output voltage of the operational amplifier 23 with a reference voltage. 24),
A latch 25 triggered by the negative edge of the clock φ1,
The digital delay unit 8 has a switch SWφ2 that is turned on when the clock φ2 is at H level, and a switch SWφ1 that is turned on when the clock φ1 is at H level.
The output of the latch 25 is the digital bit stream output D
It is output to OUT.

Further, as shown in FIG. 6B, the DPLL
Is a digital phase comparator 14a connected to an external reference clock input terminal RCLK, which quantizes phase lead / lag and outputs a pulse respectively, and this comparator 14a.
A phase shift control circuit 15a that controls the phase shift based on the amount of phase lead / lag input from, a stabilized master clock oscillator 20, a variable frequency division ratio phase shifter 18a, (1 / N ) A frequency divider 22 and a two-phase clock generation circuit 28. In the above-described DPLL, the digital phase comparator 14a performs a phase comparison between the external asynchronous clock input signal RCLK and the clock obtained by dividing the output of the master frequency oscillator 20 by the variable frequency division ratio phase shifter 18a and the frequency divider 22. . Thereafter, the output quantized into a binary value or a multivalued value is received from the comparator 14a, and the phase shift control circuit 15a adjusts the timing to carry out advance or delay control of the master clock phase with respect to the control signal. However, the digital VCO is a system in which the output of the fixed frequency oscillator is received by the phase shifter 18a having a variable frequency division ratio and the pulse is inserted or removed, and the frequency of the oscillator is sufficiently large in order to reduce the quantized value of the phase control. Set to frequency. The output clock of the phase shifter 18a is a two-phase clock generation circuit 28 as a gate circuit.
The two-phase cocks φ1 and φ2 that do not overlap with each other are created by and are output as the sampling clock.

Oversampling A / D supplied with sampling clocks φ1 and φ2 from the above-mentioned DPLL
The converter includes a switch capacitor (SC) integrator that inputs a φ1 clock to the switch SWφ1 and a φ2 clock to the switch SWφ2, and a voltage comparator (quantizer) 2
4, the digital integrator 9 and the feedback D / A converter 2 form a feedback loop. Therefore, the difference between the output of the D / A converter 2 for feeding back the integrated value of the quantized signal and the input signal AIN is taken by the analog differentiator 1 and integrated again by the SC integrator. Further, the quantizer has a structure for quantizing the integrated value. Therefore, the bitstream output DOU
At T, sufficiently low frequency components of the quantization noise are suppressed, and conversely, high frequency noise components increase. By utilizing this feature and combining it with a digital filter (not shown) in the subsequent stage, a high S / N ratio can be obtained.

[0007]

In the conventional oversampling A / D converter described above, when jitter is superimposed on the sampling clock, the noise generated by the jitter is determined by the slew rate of the analog input signal. Therefore, when the input signal is a sine wave, the phase is 90
Quantization noise of the cosine wave with a shift is generated.

Generally, the analog input signal is V (t) = A
If Sin (2πft) and the average jitter amount are Δt, the product of the root mean square value of the slope of the input signal and Δt is the effective value of the voltage error due to the jitter. Therefore, such a relationship is

[0009]

It is expressed as

That is, there is a clear positive correlation between the slope of the analog input signal voltage and the noise voltage due to jitter. In the above-mentioned conventional example, the timing of the phase shift of the digital PLL is performed at the sampling clock after the phase comparison or at an arbitrary timing similar thereto, regardless of the analog input signal. Therefore, the generated jitter noise has a strong correlation with the input signal, and cannot be suppressed by the noise shaping in the case of the Σ-Δ type A / D converter. Therefore, the SN ratio characteristic reaches a ceiling due to this jitter noise.

Further, when the external asynchronous input clock has a frequency offset in the digital PLL, a stationary phase error occurs, so that the jitter noise is constantly generated. On the other hand, there is an A / D converter that does not generate a steady phase error by configuring the loop filter of the digital PLL with a digital filter having a second-order or higher pole, but the hardware below the phase comparator is multi-valued. Therefore, it leads to a large increase in hardware scale.

Therefore, in the modem analog front end using the oversampling A / D converter including the conventional digital PLL circuit, there is a drawback that a high SN ratio characteristic cannot be realized with an appropriate circuit scale.

It is an object of the present invention to provide an oversampling A / D converter which can realize such a high SN ratio characteristic with an appropriate circuit scale.

[0015]

SUMMARY OF THE INVENTION An oversampling A / D converter of the present invention is an oversampling A / D converter that uses a clock whose phase is synchronized with an external asynchronous clock by a digital PLL as a sampling clock. A digital PLL circuit that outputs a first clock that has been phase-corrected at a predetermined phase-correction timing and a second clock that has not been phase-shifted with respect to a phase deviation in a subsequent steady operation state, and an analog integration circuit for each of them. And a quantizer, and a latch circuit, and one of the first and second forward path circuits that operate according to the first and second clocks respectively, and the output of the first and second forward path circuits Selecting circuit for selecting and outputting the quantized output, and the digital PL
When the quantized output results of the first and second forward path circuits differ due to the phase correction operation of the L circuit, it is determined that the phase correction timing of the digital PLL circuit is inappropriate, and the first forward path circuit The integration result is modified so as to be equal to the integration result of the second forward path circuit, and the second result is used as the output of the selection circuit.
Selecting the quantized output of the forward path circuit of the digital PLL circuit and correcting the phase of the first clock in the digital PLL circuit so as to be equal to the second clock, while the first and second forward circuits are When the quantized output result of the pass circuit is the same, it is determined that the phase correction timing of the digital PLL circuit is appropriate, and the integration result of the second forward path circuit is set to the integration result of the first forward path circuit. So that the output of the first forward path circuit is selected as the output of the selection circuit and the phase of the second clock in the digital PLL circuit is made equal to the first clock. And a control circuit that performs an operation of correcting the phase.

Further, the oversampling A /
The D converter is an oversampling A / D converter that uses a clock synchronized in phase with an external asynchronous clock by a digital PLL as a sampling clock, and adds a phase shift operation following a phase error in a steady operation state after lock-in. A digital PLL circuit that controls the phase of the first sampling clock and the second sampling clock that has not been subjected to a phase shift for tracking, and an analog integrator, a quantizer, and a latch circuit, respectively. It operates independently by the first and second sampling clocks, and at the timing when the phase shift operation is not added, the first and second sampling clocks are operated.
Sampling clocks completely overlap to obtain the same output and operate as one sigma-delta modulator, and at the timing when the phase shift operation is added, the first and second sampling clocks are added.
Of the sampling clocks and a second forward path circuit that operates by the second sampling clock so as to output an integration result and a quantization result at the time of settling of each sampling clock. And when the quantization results output from the first and second forward path circuits are different due to the operation of the phase shift, it is determined to be unsuitable as the execution timing of the phase shift, and the first phase shift operation is performed. No. 1 forward path circuit is modified so as to match the integration result of the second forward path circuit, and the quantized value of the second forward path circuit is selected and output. If the quantization results output from the second forward path circuit are the same, the phase shift Are judged to be valid as the timing for implementing the bets, the correction to the first to match the integration result of the second forward path circuit was not performed a phase shift to the integration result of the first forward path circuit
Selection circuit for selecting and outputting the quantized value of the forward path circuit of the above, and when the selection circuit determines that the phase shift is not appropriate for the execution timing, the digital PLL circuit causes the first sampling clock When a lag or lead shift is performed, a correction shift of lead or lag is performed on the first sampling glock within one sampling period, and conversely, when it is determined that the phase shift is effective,
After the digital PLL circuit performs the delay or advance shift with respect to the first sampling clock, performs the delay or advance follow-up shift with respect to the second sampling clock within one sampling period, and then the next phase. And a control circuit that performs control for synchronizing the first and second forward path circuits until the shift timing.

[0017]

In general, in the oversampling A / D converter, the output amplitude of the integrator as a noise shaper becomes small in a portion where the analog input signal has a steep slope, and the input hysteresis of the quantizer is approached. The converted output has a high probability of being inverted every sampling. On the contrary, in the portion where the analog input signal has a gentle slope, the integrator output amplitude becomes large, and the probability that the quantized output is not inverted over several samples tends to increase.

The present invention takes advantage of this property to make a digital PL.
Every time the phase shift of L is executed, the change in the quantized output of the Σ-Δ type noise shaper is observed with and without the phase shift, and if there is a change, the input signal Since the probability that the slope is steep is high, control is performed to change the phase shift position to another, and if there is no change, the probability that the slope of the input signal is gentle is high, so the phase shift is enabled. By controlling in this way, the digital P at the timing when the slope of the analog input signal voltage is steep
By reducing the probability of occurrence of sampling jitter due to the phase shift generated by LL and increasing the phase shift at the timing when the slope of the analog input signal voltage is gentle, the voltage amplitude caused by the jitter can be suppressed at the same time. Since the suppression effect due to noise shaping can be expected by reducing the correlation with the analog input signal, the SN ratio due to jitter is improved.

[0019]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a circuit diagram of an oversampling A / D converter showing an embodiment of the present invention. As shown in FIG. 1, in this embodiment, a digital PLL (DPLL) 6 using clocks φ and φA that are phase-synchronized with an external reference clock RCLK as a sampling clock and an analog signal AIN are input to obtain a difference from a feedback signal. A differentiator 1, first and second forward path circuits 3 and 4 to which an output of the differentiator 1 is input and which includes an analog integrator 11, a quantizer 12 and a latch circuit 13, and the first and second forward path circuits 3 and 4. A determination circuit 5 that determines and controls the outputs of the second forward path circuits 3 and 4, a selector 7 that selects the outputs of the first and second forward path circuits 3 and 4 as a digital output DOUT, and this selector 7 Of the digital delay 8 and the integrator 9 that integrates the output of the digital delay 8, the digital delay 8 and the integrator 9
The differencer 10 that takes the difference of
/ A conversion and the difference device 1 as the above-mentioned feedback signal
And a D / A converter 2 for supplying The forward path circuits 3 and 4 as sigma-delta modulators in the oversampling A / D converter having such a configuration each include an analog integrator 11, a quantizer 12, and a latch circuit 13.
It operates independently by two clocks φ and φA. These forward path circuits 3 and 4 operate as one sigma-delta modulator by obtaining the same output because the clocks φ and φA completely overlap each other at the timing when no phase shift operation is applied. Conversely, at the timing when the phase shift is applied, the integration result and the quantization result at the time of settling of the clocks φ and φA are output.
In short, the first forward path circuit 3 operates by the clock φ, and the second forward path circuit 4 operates by the clock φA.

Next, the decision circuit 5 as the control means is modified by the operation of the phase shift so as to match the integration result of the first and second forward path circuits 3 and 4, and the second forward path circuit 4 is further modified. It controls to select and output the quantized value of. On the contrary, when the quantization results output from the first forward path circuit 3 and the second forward path circuit 4 are the same, the determination circuit 5 determines that the timing for executing the phase shift is effective and determines the phase shift. The integration result of the second forward path circuit 4 which has not been implemented is corrected so as to match the integration result of the first forward path circuit 3, and the quantized value of the first forward path circuit 3 is selected and output. To control.

FIG. 2 is a circuit diagram of the digital PLL shown in FIG. As shown in FIG. 2, the digital PLL 6 compares the phases of the reference clock RCLK and the feedback data via the frequency divider 22 to output the delay / advance signal S2 of the digital PLL phase shift. Have 14. Phase shift control circuit 1 for inputting the output S2 of the digital phase comparator 14
5 is a phase shift that follows a phase error when in a steady operation state in which the output clocks φ and φA are phase-followed by giving a time-discrete phase shift to the occurrence of a phase error within the lock range. Phase control is performed on two clock outputs of a sampling clock φ to which an operation is applied and a sampling clock φA to which a phase shift for tracking is not added. Further, this DPLL 6 receives the judgment result output S1 of the judgment circuit 5 and controls the phase by a phase shift control circuit 16
And OR of these two phase shift control circuits 15 and 16
OR gates 17 and 19 that take logic and their OR
Phase shifters 18 and 21 for phase-shifting the output of the master clock oscillator 20 based on the outputs of the gates 17 and 19 to output the clocks φ and φA, and the output clock φ of the phase shifter 18 are divided into 1 / N, and the above-mentioned operations are performed. And a frequency divider 22 for providing the feedback data.

In the DPLL 6, when the determination circuit 5 determines that the timing for executing the phase shift is not appropriate, the phase shift control circuit 15 delays or advances the clock φ within one sampling period. The phase shift control circuit 16 performs a correction shift, which leads or lags the clock φ. On the contrary, when the determination circuit 5 determines that the phase shift execution timing is valid, the phase shift control circuit 15 performs the delay or advance shift with respect to the clock φ within one sampling period. Performs a follow-up shift that is delayed or advanced with respect to the clock φA, and then performs control for synchronizing the first and second forward pass circuits 3 and 4 until the next phase shift dimming. In short, this DPLL inputs the same master clock to the phase shifters 18 and 21 of two systems,
The clocks φ and φA are independently output, and at the timing of phase correction, the phase shifter 18 that outputs the clock φ is phase-shift controlled only by the phase shift control circuit 15. At the timing of determining whether the phase correction is valid or invalid, the phase shift control circuit 16 shift-controls the phase shifter 18 that outputs the clock φ or the phase shifter 21 that outputs the clock φA based on the determination result.

FIG. 3 is a specific circuit diagram of the oversampling A / D converter in FIG. As shown in FIG. 3, such an A / D converter has an analog signal input terminal AIN.
And an analog differentiator 1 connected to a D / A converter 2 for feeding back a quantized signal and taking a difference between an input signal and a D / A converted output, a digital delay device 8, and a prediction type noise shaper. With a digital integrator 9 in the feedback loop used, these being identical to FIG. In FIG. 3, the first and second forward path circuits 3 and 4 are input capacitances Ci of the SC integrator on the φ clock side.
1 and φ clock side SC integrator integration capacitance Cs
1 and the input capacitance Ci of the SC integrator on the φA clock side
2 and φA Clock side SC integrator integration capacitance C
s2, an operational amplifier 23 for an integrator, a voltage comparator 24 as a quantizer, a latch 25 triggered by the negative edge of the clock φ1 and a latch 26 triggered by the negative edge of the clock φ1A. . These latches 2
The outputs of 5 and 26 are supplied to the multiplexer 7 as a selector directly and via the EX-OR gate 27.
That is, the multiplexer uses the lag / lead signal and EX-O
The output of the R gate 27 is used as a control input, and the latched 2
Select two quantized outputs.

SWφ1 is a switch that is turned on when the clock φ1 is at the H level, and SWφ2 is the clock φ.
The switch that turns on when 2 is at the H level, SWP turns on only for one cycle in synchronization with clock φ2 after the completion of integration and quantization, only when the phase shift of digital PLL 6 is executed with respect to clock φ. Is a switch. Further, the SWφ2Cs2 is normally turned on when the clock φ2 is enabled, but when it is determined that the charge of the capacitor Cs2 needs to be corrected when the phase shift is executed, the control timing generation circuit masks the switch enable of the clock φ2 to turn it off. Switch to maintain, SWφ2
Cs1 is normally turned on when the clock φ2 is enabled, but when it is determined that the charge of the capacitor Cs1 needs to be corrected when the phase shift is performed, the control timing generation circuit masks the switch enable of the clock φ2 and maintains the off state. It is a switch. Moreover, the SWCs2 is normally in the ON state, but only when it is determined that the charge amount of Cs2 needs to be corrected during the phase shift, the switch SWφ
It is a switch that is turned off in synchronization with 2Cs2.
The WCs1 is normally on, but is turned off in synchronization with the switch SWφ2Cs1 only when it is determined that the charge amount of the capacitor Cs1 needs to be corrected during the phase shift. The description of the transistor is omitted.

FIG. 4 is a timing diagram for the occurrence of a delayed phase shift to explain the circuit operation in FIG. As shown in FIG. 4, for the occurrence of the delayed phase shift,
In the A / D converter, there is no inversion between the quantization result of the integrator performing the φ-system clock operation and the quantization result of the integrator performing the φA-system clock operation, and thus the phase shift is effective. Therefore, a lag phase shift is performed to follow the φA system clock one cycle later.

Further, in FIG. 4, when the delayed phase shift operation occurs in the φ system clocks φ1 and φ2 according to the result of the phase comparison of the digital PLL 6, first, the integrating operation to the capacitor Cs2 is performed by the rising of φ1A in which the phase shift is not performed. Then, the integrating operation to the capacitor Cs1 is started by the rising of the clock φ1. Next, the settling ends at the fall timing of the clock φ1A and the fall timing of the clock φ1, respectively, and the integration capacitance Cs
2, Cs1 is disconnected from the output of the operational amplifier 23 before and after the switch SWφ1. Therefore, the integrated charge at that timing is held, and at the same time, the quantizer 2
The output of 4 is latched in the latches 25 and 26. These two
The two quantized values are input to the EX-OR gate 27, and when the comparison result is inverted, it is determined that the quantized value is inappropriate as the timing for performing the phase shift. On the contrary, when the comparison result is not inverted, it is determined that the phase shift is effective. This determination is performed during the slit period between the fall timing of the clocks φ1A and φ1 and the rising timing of the clocks φ2A and φ2.

Furthermore, the negative input terminal of the operational amplifier 23 and the input capacitance Ci1, are generated by the rising of the clocks φ2A and φ2.
Since both ends of Ci2 are connected to the analog ground potential by the switch SWφ2, the charges of these input capacitors are reset. Moreover, only when the phase shift is performed, the two held integrated voltages have different values. Therefore, at the rising timing of the clocks φ2A and φ2, one end of the two integration capacitors is connected to the output of the operational amplifier 23 by a switch. At the same time, the integration capacitance to be invalidated, that is, Cs2 in FIG. 4, is connected to the analog ground potential by the switch SWφ2Cs2 and changed to the load capacitance of the operational amplifier 23. At this time, the integration capacitance Cs to be validated
Regarding 1, the other end remains connected to the negative input terminal and maintains virtual ground, so that the integrated voltage becomes the output of the operational amplifier 23. Therefore, the load connected capacity C
By recharging s2, it is possible to have the function of modifying the integrator output.

FIG. 5 is a timing diagram for the generation of the lead phase shift for explaining the circuit operation in FIG. As shown in FIG. 5, for the occurrence of the leading phase shift,
In the A / D converter, inversion occurs between the quantization result of the integrator performing the φ-system clock operation and the quantization result of the integrator performing the φA-system clock operation, so that the phase shift becomes invalid. Therefore, here, the lag phase shift for correcting the φ-system clock after one cycle is performed. That is, when the advanced phase shift operation occurs in the φ system clocks φ1 and φ2 according to the phase comparison result of the digital PLL, the integrating operation to the capacitor Cs1 is first started by the rising of φ1, and the phase shift is not performed next. φ1A
The integration operation to the rising capacitance Cs2 of C. At the fall timing of this clock φ1 and the fall timing of φ1A, settling ends,
The integration capacitors Cs1 and Cs2 are cut off from the output of the operational amplifier 23 one after another by the switch SWφ1. Therefore, the integrated charge at that timing is held, and at the same time, the output of the voltage comparator 24 as a quantizer is latched.

When the comparison result of these two quantized values is inverted, it is determined that the timing for executing the phase shift is inappropriate. This determination is based on the clock φ1A,
This is performed during the slit period between the fall timing of φ1 and the rising timing of the clocks φ2A and φ2. The operational amplifier 2 is generated by the rising of these clocks φ2A and φ2.
Negative input terminal of 3 and input capacitance both ends of switch SWφ
2 is connected to the analog ground potential, and the charge of the input capacitance is reset. Further, in this case, since the two integrated voltages held are different in value, the clocks φ2A and φ2
At one rising timing, one ends of the two integration capacitors are connected to the output of the operational amplifier 23 by the switch SWP. At the same time, with respect to the integration capacitance Cs1 to be invalidated, the other end is connected to the analog ground potential by the switch SWφ2Cs1 and cut off from the negative input terminal of the operational amplifier 23 by the switch SWCs1 to thereby remove the integration capacitance Cs1. Change to the load capacity of. At this time, the other end of the integration capacitance Cs2 to be validated is still connected to the negative input terminal and kept at virtual ground. For this reason, the integrated voltage becomes the output of the operational amplifier 23, and the function of correcting the integrator output can be provided by recharging the load-connected capacitance Cs1.

In summary, the oversampling A / D converter of this embodiment is an integrator and a quantizer (voltage comparator).
A feedback loop is formed by the feedback D / A conversion circuit, and the difference between the output of the D / A conversion circuit for feeding back the quantized signal and the input signal is integrated. In particular, the quantizer has a structure for quantizing the integrated value. The characteristic is that the integrator 11 and the quantizer 12 have two timing edges (φ,
The quantizer 12 compares the integrated voltage held at each timing edge with the voltage comparator 24 and latches it in the latches 25 and 26. The two quantized values latched are input to the EX-OR gate, and it is determined whether the values are inverted. Only the phase shift generated by the digital PLL 6 is selected by the multiplexer 7 based on this result and the lead / lag signal. That is, one of the quantized values is selected by the multiplexer 7.

On the other hand, in the digital PLL 6, phase shift control is performed based on the output of the phase comparator 14, and at the same time, a lead / lag signal indicating the shift direction is generated. Also, it has two phase shift control circuits 15 and 16, one controls the shift operation based on the phase comparison as in the conventional case, and the other one is the value of the lead / lag signal and the output of the EX-OR gate 27. From the above, the clock φA that has been phase-shifted or not corrected
Controls whether to perform the phase shift of. Further, the phase shift circuit is a counter having a variable division ratio, and has a structure that outputs two clocks φ and φA and receives two types of control signals. If the phase error cannot be detected by the phase comparator 14, of course, the phase shift control is not performed, and neither the lead signal nor the lag signal is enabled at this time, and the two output clocks φ and φA are controlled so as to be completely coincident with each other. To be done.

[0032]

As described above, the oversampling A / D converter of the present invention pays attention to the fact that the quantized output is about 1 to 3 bits, and every time the phase shift of the digital PLL is executed. , The change in the quantized output of the noise shaper is observed with and without the phase shift. If there is a change, the probability that the slope of the input signal is steep is high. The other control is performed, and conversely, if there is no change, it is highly likely that the slope of the input signal is gentle. Therefore, control that enables the phase shift is performed to suppress the voltage amplitude caused by jitter to a low level. At the same time, by suppressing the correlation with the analog input signal, it is possible to realize suppression by noise shaping, and thus it is possible to suppress deterioration of the SN ratio to a low level.

[Brief description of drawings]

FIG. 1 is a block diagram of an oversampling A / D converter showing an embodiment of the present invention.

FIG. 2 is a block diagram of the DPLL shown in FIG.

3 is a specific circuit diagram of the oversampling A / D converter in FIG.

4 is a timing diagram for the occurrence of lag phase shift to explain the circuit operation in FIG.

5 is a timing diagram for the occurrence of a lead phase shift to explain the circuit operation in FIG.

FIG. 6 is an oversampling A / D showing a conventional example.
It is a block diagram of a converter and DPLL.

[Explanation of symbols]

 1, 10 Differentiator 2 D / A converter 3 First forward path circuit 4 Second forward path circuit 5 Judgment circuit 6 Digital PLL 7 Selector (MPX) 8 Digital delayer 9 Integrator 11 Analog integrator 12 Quantization Device 13, 25, 26 Latch circuit 14 Digital phase comparator 15, 16 Phase shift control circuit 18, 21 Phase shifter 20 Master clock oscillator 22 Frequency divider 23 Operational amplifier 24 Voltage comparator 27 EX-OR gate

Claims (3)

[Claims] 1. An oversample A / D converter that uses a clock synchronized in phase with an external asynchronous clock by a digital PLL as a sampling clock, and a predetermined phase with respect to a phase deviation in a steady operation state after synchronization is established. A digital PLL circuit that outputs a first clock that has been phase-corrected at a correction timing and a second clock that has not been phase-shifted, and an analog integrator, a quantizer, and a latch circuit, respectively, First and second forward path circuits that are operated by a second clock; and the first and second forward path circuits.
Of the output signals of the forward path circuit, and when the quantized output results of the first and second forward path circuits are different due to the phase correction operation of the digital PLL circuit and the selection circuit that selects the quantized output. It is determined that the phase correction timing of the digital PLL circuit is inappropriate, the integration result of the first forward path circuit is corrected to be equal to the integration result of the second forward path circuit, and the output of the selection circuit is corrected. Is selected as the quantized output of the second forward path circuit, and the phase of the first clock in the digital PLL circuit is corrected so as to be equal to the second clock, while the first and When the quantized output results of the second forward path circuit are the same, the phase correction timing of the digital PLL circuit is Is determined to be appropriate, the integration result of the second forward path circuit is corrected to be equal to the integration result of the first forward path circuit, and the first forward path is output as the output of the selection circuit. And a control circuit for performing an operation of selecting an output of the circuit and correcting the phase of the second clock in the digital PLL circuit so as to be equal to the first clock. Sampling A / D converter. 2. An oversampling A / D converter that uses as a sampling clock a clock whose phase is synchronized with an external asynchronous clock by a digital PLL.
A digital PLL circuit that controls the phase of a first sampling clock to which a phase shift operation is added following a phase error in a steady operation state after lock-in and a second sampling clock to which a phase shift for tracking is not added; Each includes an analog integrator, a quantizer, and a latch circuit, which operate independently by the first and second sampling clocks, and at the timing when the phase shift operation is not applied, the first and second
Sampling clocks completely overlap to obtain the same output and operate as one sigma-delta modulator, and at the timing when the phase shift operation is added, the first and second sampling clocks are added.
Of the sampling clocks and a second forward path circuit that operates by the second sampling clock so as to output an integration result and a quantization result at the time of settling of each sampling clock. And when the quantization results output from the first and second forward path circuits are different due to the operation of the phase shift, it is determined to be unsuitable as the execution timing of the phase shift, and the first phase shift operation is performed. No. 1 forward path circuit is modified so as to match the integration result of the second forward path circuit, and the quantized value of the second forward path circuit is selected and output. If the quantization results output from the second forward path circuit are the same, the phase shift Are judged to be valid as the timing for implementing the bets, the correction to the first to match the integration result of the second forward path circuit was not performed a phase shift to the integration result of the first forward path circuit
Selection circuit for selecting and outputting the quantized value of the forward path circuit of the above, and when the selection circuit determines that the phase shift is not appropriate for the execution timing, the digital PLL circuit causes the first sampling clock When a lag or lead shift is performed, a correction shift of lead or lag is performed on the first sampling glock within one sampling period, and conversely, when it is determined that the phase shift is effective,
After the digital PLL circuit performs the delay or advance shift with respect to the first sampling clock, performs the delay or advance follow-up shift with respect to the second sampling clock within one sampling period, and then the next phase. An oversampling A /, which has a control circuit for controlling the first and second forward path circuits to operate synchronously until a shift timing.
D converter. 3. The SC integrator, wherein the first forward path circuit receives a voltage obtained by subtracting a voltage corresponding to a loop feedback of sigma delta from an input analog signal and operates by two-phase clock outputs φ1 and φ2 of a digital PLL. When the output of the SC integrator is input to the quantizer, the output of the quantizer is latched at the fall timing of the settling edge φ1 of the integrator, and After the slit period in which the switch means is turned off, the integration capacity of the SC integrator is cut off from the output of the operational amplifier by the switch means at the rising timing of the clock φ2, and at the same time, the negative input terminal of the operational amplifier and the both ends of the input capacity of the operational amplifier are disconnected. By connecting to the analog ground potential by switch means, the charge of the input capacitance It has a reset structures, further wherein the second forward path circuit has the same structure as the first forward path circuit, two-phase clock output φ1
A and φ2A, while the first and second
Of the SC integrator share the operational amplifier and the quantizer, and the two-phase clock φ1
And the first latched at the fall timing of φ1A
And which integrated voltage of the first and second forward path circuits is to be validated based on the voltage comparison result of the second forward path circuit and the signal output indicating the phase shift control direction of the delay / advance of the digital PLL. When it is determined by the phase shift control circuit that determines that the integration voltage of the first forward path circuit needs to be corrected, one end of the integration capacitance is output to the output of the operational amplifier by the switch means at the rising timing of the clock φ2. Regarding the integrating capacitance to be invalidated at the same time as the connection, the other end is connected to the analog ground potential by the switch means and is cut off from the negative input terminal of the operational amplifier by the switch means so that the integrated capacitance becomes the load of the operational amplifier. The negative input is the other end of the integration capacitance that should be enabled at this time. The integrated output of the first forward path circuit is converted into the integrated output of the second forward path circuit by having a structure for recharging the load-connected capacitance by keeping the virtual ground while being connected to the child. If the correction is performed and the phase shift control circuit determines that the integrated voltage of the second forward path circuit needs to be corrected, the same control is performed at the timing of the clock φ2A, and the integrated output of the second forward path is obtained. 3. The oversampling A / D converter according to claim 2, wherein is corrected to an integrated output of the first forward path circuit.