JP2531285B2 - Primary system digital PLL - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital PLL (phase locked loop), and more particularly to a primary digital PLL used in a stuff synchronization system.

2. Description of the Related Art A conventional primary digital PLL, as shown in FIG.
N divider 1 that divides the input signal fin by N (N: positive integer)
, An N divider 2 that divides the output signal fout by N, an oscillator 3 that generates an internal high-speed clock Rfo (R: positive integer, Fo: free-run frequency), a position of the input signal fin and the output signal fout. The phase difference is quantized by the internal high-speed clock Rf ₀ , and the multi-value quantization phase comparator 4 that outputs the amount of phase advance or the amount of phase delay, and counts up by 2N ₁
When it reaches to reset outputs one pulse removed signals D ₁ to N _1, counts down by a phase delay, and outputs one pulse additional signal I ₁ reaches 0 and N ₁ counter 5 is reset to N ₁ When the 1-pulse addition signal I ₁ is input, 1 pulse is added to the pulse train of the internal high-speed clock Rf ₀
Internal high-speed clock Rf ₀ when pulse removal signal D ₁ is input
It has a 1-pulse adding or removing circuit 6 for removing 1 pulse from the pulse train, and an R divider 7 for dividing the pulse train output from the 1-pulse adding or removing circuit 6 by R. Such a conventional technique is described, for example, in "All Digital Line PLL Using Multivalued Quantization Phase Comparator", IEICE Transactions 82/3 Vol.J65-B.

Here, when a phase difference occurs between the input signal fin and the output signal fout, the multi-value quantization phase comparator 4 discriminates the amount of phase difference and the phase advance or the phase delay, and the discrimination result is N sent to _first counter 5, N ₁ counter 5 operates as a digital filter, 1 pulse addition signal from N ₁ counter 5 I ₁
Alternatively, by controlling the 1-pulse addition or removal circuit 6 by the 1-pulse removal signal D ₁ , feedback control is performed so that the output signal fout is locked to the input signal fin.

SUMMARY OF THE INVENTION However, the above-described conventional primary digital PLL
Since the frequency of the oscillator that generates the internal high-speed clock is determined in order to obtain the free-run frequency, the frequency of the oscillator that generates the internal high-speed clock is uniquely determined, and this internal high-speed clock is generated in the device. However, even if there is an oscillator having a frequency similar to that of the oscillator, there is a problem that this oscillator cannot be used as an oscillator for generating an internal high-speed clock.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore, an object of the present invention is to solve the above problems inherent in the conventional technology and to arbitrarily select an oscillator for generating an internal high-speed clock. New primary digital system
It is to provide PLL.

Means for Solving the Problems In order to achieve the above object, a primary digital PLL according to the present invention includes an N frequency divider that divides an input signal by N and an N frequency divider that divides an output signal by N. And a multi-valued quantized phase comparator for detecting and quantizing the phase difference of each output of each of these frequency dividers,
The N ₁ counter that counts up and down according to the phase lead and lag information output from this multi-valued quantized phase comparator, an oscillator that generates an internal high-speed clock, a fixed number of control pulses and the N ₁ counter A rate multiplayer for generating a position determination clock for incorporating the 1-pulse addition signal and the 1-pulse removal signal into a specific positional relationship with respect to the control pulse, and the position determination clocks from the rate multi-player. The 1-pulse additional signal and the 1-pulse removal signal from the N ₁ counter are inserted into the position where the fixed number of control pulses output from the rate multiplayer are added and subtracted, and the final 1-pulse additional signal and 1 pulse are added. An arithmetic circuit that generates a removal signal, a 1-pulse addition signal that is output from this arithmetic circuit, and A 1-pulse adding or removing circuit for adding or removing 1 pulse from the pulse train of the internal high-speed clock output from the oscillator according to the pulse removing signal, and the pulse train output by the 1-pulse adding or removing circuit is smoothed. R frequency divider for

Effect In the present invention, the control pulse from the rate multiplier is added or removed through the arithmetic circuit even during free run, that is, when the N ₁ counter does not output the 1 pulse addition signal or the 1 pulse removal signal. It acts as a 1-pulse addition signal or a 1-pulse removal signal for the circuit.

Embodiment Next, the present invention will be described in detail with reference to the drawings for a preferred embodiment thereof.

FIG. 1 is a block diagram showing an embodiment of a primary system digital PLL according to the present invention.

Referring to FIG. 1, one embodiment of the present invention is based on an input signal
N divider 1 that divides fin by N, N divider 2 that divides output signal fout by N, and oscillator 3 that generates internal high-speed clock Rf ₀ (R: positive integer, f ₀ ≈fin) And a multi-value quantization phase comparator 4 which quantizes the phase difference between the input signal fin and the output signal fout by the internal high-speed clock Rf ₀ and outputs the phase advance amount or the phase delay amount, and counts up by the phase advance. Then, when the count value reaches 2N ₁ , it outputs the 1-pulse removal signal D ₁ and resets it to N ₁ , and counts down due to the phase delay, and when the count value reaches 0, it outputs the 1-pulse addition signal I ₁ . and N ₁ counter 5 is reset to N ₁ by the control pulses of a fixed number and (described in 1 pulse addition signal I ₂ in this embodiment), a pulse addition signal I ₁ from N ₁ counter 5 1 pulse positioning clocks CI for additional signal I ₂ and not concurrently generate , The rate multiplier 8 for outputting a positioning clock CD for generating each other so as to offset one pulse removed signal D ₁ and 1 pulse addition signal I ₂ from the N ₁ counter 5, 1 from N ₁ counter 5
The pulse addition signal I ₁ and the 1-pulse addition signal I ₂ from the rate multiplier 8 are added to obtain the final 1-pulse addition signal I ₀
Is output, and the 1-pulse removal signal D ₁ from the N ₁ counter 5 and the 1-pulse addition signal I ₂ from the rate multiplier 8 are subtracted, and the final 1-pulse removal signal D ₀ is output.
When the 1-pulse addition signal I ₀ is input, 1 pulse is added to the pulse train of the internal high-speed clock Rf ₀ , and when the 1-pulse removal signal D ₀ is input, 1 pulse is added from the pulse train of the internal high-speed clock Rf ₀ . It is configured to include a one-pulse adding or removing circuit 6 for removing and an R divider 7 for smoothing by dividing the pulse train output from the one-pulse adding or removing circuit 6 by R.

The rate multiplier 8 has a function of outputting an arbitrary number of clocks in the pulse train of the output signal fout of the R divider 7 input to the clock input terminal as a control signal (1 pulse additional signal I ₂ ) at even intervals. Is a circuit that has
It is composed of a combination of gate circuits. The number of output pulses of the 1-pulse additional signal I ₂ is determined by the free-run frequency. Further, the arithmetic circuit 6 can be configured by a combination of a plurality of memories and a subtractor or the like. Such an arithmetic circuit is described in detail in, for example, the specification of Japanese Patent Application No. 63-215237 and the drawings filed by the same applicant as the present application.

In the free-run operation in this embodiment, the 1-pulse additional signal I ₂ from the rate multiplier 8 becomes the 1-pulse additional signal I _{0 of} the arithmetic circuit 9 as it is, and the 1-pulse additional signal I _{0 is obtained} .
The I ₀ performs the addition of 1 pulse to the pulse train of the internal high-speed clock Rf ₀ in 1 pulse addition or removal circuit 6, the free-run frequency at that time becomes a frequency higher than f _0.

The number of position determination clocks CI, CD, and the generation position are determined by the number of 1-pulse additional signals I ₂ output from the rate multiplier 8.

With the above configuration and function according to the present invention, it becomes possible to finely adjust the free-run frequency output by the PLL circuit according to the present invention when the input signal is disconnected.

The present embodiment described above is for the case where the 1-pulse additional signal I ₂ is used as the control pulse output from the rate multiplier 8. However, instead of the 1-pulse additional signal I ₂ , the 1-pulse removing signal is used. By using D ₂ (not shown), the arithmetic circuit 9 can be operated in the opposite manner to this embodiment. In that case, it goes without saying that the relationship between the position determination clocks CI and CD and the 1-pulse additional signal I ₁ and the 1-pulse removal signal D ₁ is reversed.

EFFECTS OF THE INVENTION As described above, according to the present invention, a fixed number of control pulses are always output from the rate multiplier, and one pulse addition signal or one pulse removal signal is output from the arithmetic circuit even during free run. Therefore, it is possible to change the free-run frequency by selecting the number of control pulses, and it is possible to obtain the effect that the selection of the oscillator that generates the internal high-speed clock is not unique.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG.
The figure is a block diagram of a conventional example of a primary digital PLL. 1, 2 ...... N frequency divider, 3 ...... oscillator, 4 ...... multilevel quantizer phase comparator, 5 ...... N ₁ counter, 6 ...... 1 pulse addition or removal circuit, 7 ...... R divider , 8 ... rate multiplier, 9 ... arithmetic circuit, I ₀ , I ₁ , I ₂ ... 1 pulse addition signal, D ₀ , D ₁ ... 1 pulse removal signal, CI ... 1 pulse addition signal I ₁ Position determination clock, CD ... 1 pulse removal signal
Positioning clock for D ₁

Claims (3)

(57) [Claims] 1. An N divider for dividing an input signal by N, an N divider for dividing an output signal by N, and a multi-value detector for detecting and quantizing a phase difference between respective outputs of these N dividers. A value quantization phase comparator,
An N ₁ counter that counts up and down according to phase lead and lag information output from the multi-valued quantized phase comparator, an oscillator that generates an internal high-speed clock, and a 1-pulse additional signal output from the N ₁ counter. And a 1-pulse adding or removing circuit for adding or removing 1 pulse from the pulse train of the internal high-speed clock output by the oscillator according to the 1-pulse removing signal, and a pulse train output from the 1-pulse adding or removing circuit. In a primary system digital PLL having an R divider for smoothing, a fixed number of control pulses and one pulse addition signal and one pulse removal signal from the N ₁ counter are fetched in a specific positional relationship with respect to each control pulse. And a rate multiplier that generates a position determination clock for 1 to a position determined by the respective position determining clock from Laiya from the N ₁ counter
A pulse addition signal and a 1-pulse removal signal are inserted, a fixed number of control pulses output from the rate multiplier are added and subtracted, and a final 1-pulse addition signal and a 1-pulse removal signal are added to the 1-pulse addition or removal circuit. A first-order digital PLL comprising: 2. The number of control pulses output from the rate multiplier is further determined by the free-run frequency output by the primary digital PLL when the input signal is disconnected. The primary digital PLL described in (1). 3. The primary according to claim 1, wherein the fixed number of control pulses output from the rate multiplier is one pulse addition signal or one pulse removal signal. System digital PLL.