JPH03225859A - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- JPH03225859A JPH03225859A JP2021305A JP2130590A JPH03225859A JP H03225859 A JPH03225859 A JP H03225859A JP 2021305 A JP2021305 A JP 2021305A JP 2130590 A JP2130590 A JP 2130590A JP H03225859 A JPH03225859 A JP H03225859A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- tab
- cap
- semiconductor package
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 238000007789 sealing Methods 0.000 claims description 2
- 239000010931 gold Substances 0.000 description 3
- 229910001080 W alloy Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910000833 kovar Inorganic materials 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- SBYXRAKIOMOBFF-UHFFFAOYSA-N copper tungsten Chemical compound [Cu].[W] SBYXRAKIOMOBFF-UHFFFAOYSA-N 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 1
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体パッケージに関し、特に電子装置等に使
用される配線基板にＴ Ａ Ｂ （Ｔａｐｅ Ａｕｔｏ
ｍａｔｅｄ Ｂｏｎｄｉｎｇ）Ｉ Ｃを実装した半導体
パッケージに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor packages, and in particular to wiring boards used in electronic devices etc.
The present invention relates to a semiconductor package mounted with a mated bonding (IC) IC.
従来、この種の半導体パッケージは、第２図に示すよう
に、配線基板２−１とキャップ２−２とでできる空所２
−３に容量素子２−４を配置したり、あるいは第３図に
示す様にキャップ３−１に凹所３−２を設け容量素子３
−３を配置していた（例えば実開昭５９−１４９６４５
号公報）。Conventionally, this type of semiconductor package has a space 2 formed between a wiring board 2-1 and a cap 2-2, as shown in FIG.
-3, or as shown in FIG.
-3 was placed (for example, Utility Model No. 59-149645
Publication No.).
上述した従来の半導体パッケージは第２図のように、容
量素子２−４を空所２−３に入れるためには容量素子２
−４の大きさだけ空所２−３を大きくする必要かあり、
半導体パッケージの大きさが大きくなる。また第３図の
ように容量素子３−３をキャップ３−１の凹所３−２に
入れるためには、キャップ３−１の厚みを厚くしなけれ
ばならす、そのため半導体パッケージの大きさが大きく
なる。またキャップ３−１側に容量素子３−３があるた
めにＴＡＢＩＣのダイをキャップに接着することができ
ず、ＴＡＢＩＣの発生する熱をキャップ側から放出する
という効率の良い方法が使えないという欠点がある。In the conventional semiconductor package described above, as shown in FIG.
Is it necessary to enlarge space 2-3 by the size of -4?
The size of semiconductor packages increases. Furthermore, in order to insert the capacitive element 3-3 into the recess 3-2 of the cap 3-1 as shown in Fig. 3, the thickness of the cap 3-1 must be increased, which increases the size of the semiconductor package. Become. Also, since the capacitive element 3-3 is located on the cap 3-1 side, the TABIC die cannot be bonded to the cap, and an efficient method of discharging the heat generated by the TABIC from the cap side cannot be used. There is.
本発明の半導体パッケージは、配線基板と、該配線基板
にフェイスダウンで実装されるＴＡＢＩＣと、該ＴＡＢ
Ｉ Ｃのダイと接着されかつ該配線基板とで該ＴＡＢ
ＩＣを密封するキャップとからなる半導体パッケージに
おいて前記配線基板の内部に少なくとも１個の受動素子
を設け該配線基板の端子に接続されたことを備えて構成
される。A semiconductor package of the present invention includes a wiring board, a TABIC mounted face down on the wiring board, and a TABIC mounted face-down on the wiring board.
The TAB is bonded to the IC die and the wiring board.
A semiconductor package comprising a cap for sealing an IC, and at least one passive element provided inside the wiring board and connected to a terminal of the wiring board.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の構造を示す縦断面図である
。配線基板１−１の表面のＴＡＢＩＣＩ−２の実装部の
周囲にはＴＡＢＩＣＩ−２のり−ド１−３に接続される
リード用バット１−４が形成されており、内部配線１−
５によって入出力用パッド１−６と接続されている。ま
た配線基板１１の内部には厚膜印刷法により容量素子１
−７が形成され、一方はＴＡＢＩＣの接地端子に、他方
は電源端子に内部配線１−５を通して接続されている。FIG. 1 is a longitudinal sectional view showing the structure of an embodiment of the present invention. A lead butt 1-4 connected to the TABICI-2 board 1-3 is formed around the TABICI-2 mounting portion on the surface of the wiring board 1-1, and the internal wiring 1-4 is connected to the TABICI-2 board 1-3.
5 is connected to the input/output pads 1-6. In addition, a capacitive element 1 is provided inside the wiring board 11 using a thick film printing method.
-7 is formed, and one is connected to the ground terminal of TABIC, and the other is connected to the power supply terminal through internal wiring 1-5.
ＴＡＢＩＣＩ−２は配線基板１−１にフェイスダウンで
実装され、ＴＡＢＩＣｌ−２のリード１−３はリード用
パッド１−４に接続される。ＴＡＢＩＣＩ−２のダイは
キャップ１−９に接着され、キャップ１−９は配線基板
１−１と接着されＴＡＢＩＣＩ−２を密封する。TABICI-2 is mounted face down on the wiring board 1-1, and leads 1-3 of TABICI-2 are connected to lead pads 1-4. The die of TABICI-2 is bonded to the cap 1-9, and the cap 1-9 is bonded to the wiring board 1-1 to seal TABICI-2.
また容量素子１−７のかわりに、あるいは容量素子１−
７に加えて抵抗素子１−８を内部に形成することもでき
る。本実施例は配線基板内に容量素子と抵抗素子を各々
１個づつ形成した例である。図中の例では、リード用パ
ッド１−４は約１００μｍＸ５００μｍの金のパッドで
ＴＡＢＩＣのリート１−３にボンディングによって接続
される。配線基板１−１は比誘電率ε、が約６のセラミ
ックグリーンシートを約２０層重ね合わせて作られてお
り、内部導体は金（Ａｕ）又は銀−パラジウム＜Ａｇ−
Ｐｄ）のグリーンシート上への印刷によって形成される
。この時のパターンの寸法は線福約１００μｍ厚み約１
０μｍ程度である。容量素子１−７は約ｌＸ１０’ＰＦ
の容量を持ち、抵抗素子１−８は約５０Ωである。Also, instead of capacitive element 1-7, or capacitive element 1-
In addition to 7, resistance elements 1-8 can also be formed inside. This embodiment is an example in which one capacitive element and one resistive element are formed in the wiring board. In the example shown in the figure, the lead pad 1-4 is a gold pad of approximately 100 μm×500 μm and is connected to the TABIC lead 1-3 by bonding. The wiring board 1-1 is made by stacking about 20 layers of ceramic green sheets with a dielectric constant ε of about 6, and the internal conductor is made of gold (Au) or silver-palladium<Ag-
Pd) is formed by printing on a green sheet. The dimensions of the pattern at this time are approximately 100 μm thick and approximately 1
It is about 0 μm. Capacitive element 1-7 is approximately lX10'PF
The resistance element 1-8 has a capacitance of about 50Ω.
キャップ１−９はコバール（Ｋ○ＶＡＲ）又は銅タング
ステン合金（Ｃｕ−Ｗ合金）で作られており、キャップ
１−９と配線基板１−１の接続は金−Ｍ ＜ Ａ ｕ
−Ｓ ｎ ）のろう剤により固着され、もしくはキャッ
プ１−９がコバールの場合はシーム溶接で固着すること
もできる。この時、キャップの大きさは１０〜１５ｍｍ
角で厚が約１關である。配線基板上のリード用のパッド
１−４は直径１００〜２００μｍのスルーホールにより
配線基板内の導体パターンに接続され、さらにスルーホ
ールを介して配線基板裏面の入出力用パッド１６（約５
００μｍ角）に接続されている。The cap 1-9 is made of Kovar (K○VAR) or copper-tungsten alloy (Cu-W alloy), and the connection between the cap 1-9 and the wiring board 1-1 is gold-M < A u
-S n ) or by seam welding if the cap 1-9 is made of Kovar. At this time, the size of the cap is 10 to 15 mm.
It is about 1 inch thick at the corners. Lead pads 1-4 on the wiring board are connected to conductor patterns in the wiring board through through holes with a diameter of 100 to 200 μm, and are further connected to input/output pads 16 (approximately 5
00 μm square).
以上説明した様に本発明は、配線基板の内層に容量素子
または抵抗素子を形成することにより配線基板上に部品
を載せる必要が全く無い。また、ＴＡＢＩＣをフェイス
ダウンで実装し、ＴＡＢ ＩＣのダイをキャップに接着
している。かようなことによりＴＡＢＩＣの発生する熱
をキャップを通して効率良く放出することができるとい
う効果がある。As explained above, the present invention eliminates the need to place any components on the wiring board by forming the capacitive element or the resistive element on the inner layer of the wiring board. Additionally, the TABIC is mounted face-down, and the TAB IC die is glued to the cap. This has the effect that the heat generated by the TABIC can be efficiently released through the cap.
第１図は本発明の一実施例の構造を示す縦断面図、第２
図および第３図は従来の技術による半導体パッケージ構
造の一例を示す縦断面図である。
１−１・・・配線基板、１−２・・・ＴＡＢＩＣｌｌ−
３・・・リード、１−４・・・リード用パッド、１−５
・・・内部配線、１−６・・・入出力用パッド、１−７
・・・容量素子、１−８・・・抵抗素子、１−９・・・
キャップ。Fig. 1 is a longitudinal sectional view showing the structure of one embodiment of the present invention, Fig. 2
3 and 3 are vertical cross-sectional views showing an example of a semiconductor package structure according to the prior art. 1-1... Wiring board, 1-2... TABICll-
3...Lead, 1-4...Lead pad, 1-5
... Internal wiring, 1-6 ... Input/output pad, 1-7
... Capacitive element, 1-8... Resistive element, 1-9...
cap.
Claims (1)
れるＴＡＢＩＣと、該ＴＡＢＩＣのダイと接着されかつ
該配線基板とで該ＴＡＢＩＣを密封するキャップとから
なる半導体パッケージにおいて、前記配線基板の内部に
少なくとも１個の受動素子を設け該配線基板の端子に接
続されたことを特徴とする半導体パッケージ。 ２ 該受動素子が容量素子である特許請求の範囲第１項
記載の半導体パッケージ。 ３ 該受動素子が抵抗素子である特許請求の範囲第１項
記載の半導体パッケージ。 ４ 該受動素子が容量素子および抵抗素子である特許請
求の範囲第１項記載の半導体パッケージ。 ５ 該受動素子が容量素子であってそのうちあらかじめ
定められた該容量素子の一端が該配線基板の接地端子に
接続された特許請求の範囲第１項記載の半導体パッケー
ジ。 ６ 該受動素子が容量素子と抵抗素子であつてそのうち
あらかじめ定められた該容量素子の一端が該配線基板の
接地端子に接続された特許請求の範囲第１項記載の半導
体パッケージ。[Scope of Claims] 1. A semiconductor package comprising a wiring board, a TABIC mounted face down on the wiring board, and a cap bonded to a die of the TABIC and sealing the TABIC with the wiring board, A semiconductor package characterized in that at least one passive element is provided inside the wiring board and connected to a terminal of the wiring board. 2. The semiconductor package according to claim 1, wherein the passive element is a capacitive element. 3. The semiconductor package according to claim 1, wherein the passive element is a resistance element. 4. The semiconductor package according to claim 1, wherein the passive element is a capacitive element and a resistive element. 5. The semiconductor package according to claim 1, wherein the passive element is a capacitive element, and a predetermined one end of the capacitive element is connected to a ground terminal of the wiring board. 6. The semiconductor package according to claim 1, wherein the passive element is a capacitive element and a resistive element, of which a predetermined one end of the capacitive element is connected to a ground terminal of the wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2021305A JPH03225859A (en) | 1990-01-30 | 1990-01-30 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2021305A JPH03225859A (en) | 1990-01-30 | 1990-01-30 | Semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03225859A true JPH03225859A (en) | 1991-10-04 |
Family
ID=12051440
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2021305A Pending JPH03225859A (en) | 1990-01-30 | 1990-01-30 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03225859A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5701033A (en) * | 1995-03-20 | 1997-12-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS557346B2 (en) * | 1975-08-27 | 1980-02-25 | ||
| JPS61285739A (en) * | 1985-06-12 | 1986-12-16 | Sumitomo Electric Ind Ltd | High-density mounting type ceramic ic package |
| JPS6453568A (en) * | 1987-08-25 | 1989-03-01 | Nec Corp | Semiconductor package |
-
1990
- 1990-01-30 JP JP2021305A patent/JPH03225859A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS557346B2 (en) * | 1975-08-27 | 1980-02-25 | ||
| JPS61285739A (en) * | 1985-06-12 | 1986-12-16 | Sumitomo Electric Ind Ltd | High-density mounting type ceramic ic package |
| JPS6453568A (en) * | 1987-08-25 | 1989-03-01 | Nec Corp | Semiconductor package |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5701033A (en) * | 1995-03-20 | 1997-12-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
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