JPH0322489U - - Google Patents
Info
- Publication number
- JPH0322489U JPH0322489U JP8247289U JP8247289U JPH0322489U JP H0322489 U JPH0322489 U JP H0322489U JP 8247289 U JP8247289 U JP 8247289U JP 8247289 U JP8247289 U JP 8247289U JP H0322489 U JPH0322489 U JP H0322489U
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- signal
- circuit
- logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Dc Digital Transmission (AREA)
- Selective Calling Equipment (AREA)
Description
第1図は本考案によるリモートコントロール装
置の1実施例の回路図、第2図は同実施例の使用
状態を示す回路図、第3図は従来のリモートコン
トロール回路を備えたデイレイマシンの使用状態
を示す回路図である。
20a乃至20d……入出力端子、24a乃至
24d……ナンドゲート(論理出力素子)、26
……リモート出力回路、30……両入力否定アン
ドゲート(論理入力素子)、32……リモート入
力回路、{28……コントロール端子、34……
接地端子、36……短絡線、}切換手段。
Fig. 1 is a circuit diagram of one embodiment of the remote control device according to the present invention, Fig. 2 is a circuit diagram showing the usage state of the same embodiment, and Fig. 3 is the usage state of a daytime machine equipped with a conventional remote control circuit. FIG. 20a to 20d...input/output terminals, 24a to 24d...NAND gates (logic output elements), 26
...Remote output circuit, 30...Both input negation AND gate (logic input element), 32...Remote input circuit, {28...Control terminal, 34...
Grounding terminal, 36...short circuit wire, }Switching means.
Claims (1)
上記入出力端子と上記出力回路との間に介在し第
1の状態の制御手段が供給されたとき上記出力回
路から上記入出力端子に出力信号を供給する論理
出力素子と、上記入出力端子と上記入力回路との
間に介在し第2の状態の上記制御信号が供給され
たとき上記入出力端子からの入力信号を上記入力
回路に供給する論理入力素子と、上記制御信号を
第1の状態または第2の状態に切り換える切換手
段とを、具備するリモートコントロール装置。 (2) 上記論理出力素子がオープンコレクタ型で
あることを特徴とする請求項1記載の信号入出力
回路。 (3) 上記論理出力素子がスリーステート型であ
ることを特徴とする請求項1記載の信号入出力回
路。[Scope of claims for utility model registration] (1) Input/output terminals, input circuits, output circuits,
a logic output element that is interposed between the input/output terminal and the output circuit and supplies an output signal from the output circuit to the input/output terminal when the control means in a first state is supplied; a logic input element which is interposed between the input circuit and supplies the input signal from the input/output terminal to the input circuit when the control signal in a second state is supplied; or a switching means for switching to the second state. (2) The signal input/output circuit according to claim 1, wherein the logic output element is of an open collector type. (3) The signal input/output circuit according to claim 1, wherein the logic output element is of a three-state type.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8247289U JPH0322489U (en) | 1989-07-12 | 1989-07-12 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8247289U JPH0322489U (en) | 1989-07-12 | 1989-07-12 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0322489U true JPH0322489U (en) | 1991-03-07 |
Family
ID=31629316
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8247289U Pending JPH0322489U (en) | 1989-07-12 | 1989-07-12 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0322489U (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5310912A (en) * | 1976-07-19 | 1978-01-31 | Hitachi Ltd | Two-way multiplex transmission control system |
JPS5850061A (en) * | 1981-09-21 | 1983-03-24 | Hitachi Ltd | Parallel bus transfer system |
-
1989
- 1989-07-12 JP JP8247289U patent/JPH0322489U/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5310912A (en) * | 1976-07-19 | 1978-01-31 | Hitachi Ltd | Two-way multiplex transmission control system |
JPS5850061A (en) * | 1981-09-21 | 1983-03-24 | Hitachi Ltd | Parallel bus transfer system |
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