JPH03223931A - Data processor - Google Patents

Abstract

PURPOSE:To improve the processing speed of a special arithmetic instruction by saving the internal information on a data processor into a memory when it is decided that the special arithmetic operation can be carried out via an address of a memory storing the special arithmetic instruction. CONSTITUTION:An instruction decoder 107 decides whether the instruction read out of a memory 2 is equal to a normal executing instruction or a special arithmetic instruction via a CPU 1. Based on this deciding result, the CPU 1 reads a non-executing instruction 104 and executes it with a special arithmetic instruction. At the same time, the address of the memory 2 storing the special arithmetic instruction is decided and then this instruction is decoded and executed by the CPU 1 when it is decided that the special arithmetic operation can be executed. Then the internal information of a data processor is saved into the memory 2. Thus the CPU 1 executes the special arithmetic operation concurrently with reading of an instruction. As a result, the special arithmetic operation can be carried out in a short time.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data processing device (sequence calculation processing device) that can process special calculation instructions (sequence calculation instructions) different from normal execution instructions at high speed. It is something.

[Prior Art] FIG. 9 is a system configuration diagram showing an example of a sequence arithmetic processing device, which is a conventional data processing device. In the figure, ] is a central processing unit (CP T, J) which is a microprocessor that can send a pref match signal, 2 is a memory that stores sequence operation instructions that are normal execution instructions or special operation instructions, and 3 is a memory that is read from memory 2. If the instruction is an instruction corresponding to a sequence operation, a decoder for the command (instruction) output by the CPU, 4 is a sequence for executing the sequence operation using the decode signal 5 from the decoder 3 and the address and data from the CPU 1. 6 is a sequence calculation register, 7 is a working RAM for storing the results of sequence calculations, 8 is an address bus, and 9 is a data bus.

FIG. 10 is an operation sequence diagram illustrating the operation of the sequence arithmetic processing device of FIG. 9. In the figure, 201~
220 indicates a cycle in the operation process.

Next, the operation of the conventional sequence arithmetic processing device shown in FIG. 9 will be explained with reference to the operation sequence diagram shown in FIG. 10. The address sent from the CPU 1 through the address bus 8 reads the instruction stored at the corresponding address in the memory 2, and the read, decoded, and executed instructions are read into the CPU I. This read instruction is decoded and executed by CP[J 1, but CPU 1
If the instruction is in a state where the briff match signal is enabled, the CP
U1 is a question that decodes and executes the read instructions.
The next instruction is read from the memory 2 and decoded.

If the instruction decoded by the CPU 1 is an instruction corresponding to a sequence operation, the CPUI issues a predetermined command (instruction) to the sequence operation instruction decoder 3 to request the start of the sequence operation. The decoder 3 sends the target decoded signal 5 to the sequence calculation control section 4 according to the received command. The sequence calculation control unit 4
A sequence operation is executed by decoding the decode signal 5, the address on the address bus 8-L, and the data on the data bus 9, and the result is stored in the working RAM 7.

If we compare the above operation to the operation sequence diagram in Figure 10, cycles 201 to 210 consist of the CPU 1 reading an instruction (1?ETCH: hereinafter referred to as F) and decoding the instruction (DECODE: hereinafter referred to as F). ), instruction execution (E
Cycles 211 to 220 are cycles in which the CPU 1 reads an instruction F and decodes the instruction, and the sequence arithmetic processing unit executes a sequence operation E. It shows.

Now, taking cycles 201 to 210 as an example, CPU1l
The instruction execution cycle will be explained below.

First, an instruction is read by the memory 2 in cycle 201. Cycle 2 of the read instruction
After decoding in cycle 02, the process executes cycle 203. At this time, if the pref match signal of this instruction is possible while decoding and executing the instruction, the instruction is read in cycle 205 and executed,
The instruction is decoded in cycle 204, and when the next execution becomes possible, various operations are executed in cycle 206. After the instruction is executed, when the instruction match signal becomes possible again, the instruction is read from the memory 2 in cycle 208.

This completes one instruction execution cycle for the CPU
do.

Next, cycles 211 to 220 in which sequence calculations are executed by the sequence calculation processing device will be described. If the instruction read by CPU 1 in cycle 211 is decoded as a sequence operation instruction in cycle 212, the sequence operation instruction is executed by CPU 1 using cycle 213 in which the instruction is executed. , commands to the decoder 3 and sequence calculation control unit 4.

By passing the address and data, the sequence calculation is executed. During this instruction execution cycle, CPU 1
Since no instructions can be read, only the instructions corresponding to the number of pipelines inside CPU 1, among the instructions for which a pref match signal has been sent in advance, can be decoded in one cycle when cycle 2131 is executed.
In I, when cycle 216 is executed, cycle 217 becomes possible.

FIG. 11 is a system configuration diagram showing another example of a sequence arithmetic processing device, which is, for example, the data processing device published in Japanese Patent Application Laid-Open No. 62-38902.

In the figure, 11 is a central processing unit (CPU) capable of generating a pref match signal, and 12 is a human data arithmetic theory unit (
13 is a program read-only memory (ROM); 14 is a program read-only memory (ROM); 14 is a non-executable instruction when the instruction written in ROM 13 is for B it A, L U 12; I5 is a control signal line for notifying Bit 8 LU 12 whether the instruction currently being output from ROM 13 is for Bit ALUI 2 or not. The most significant 1 bit of ROM 13 is output.

16 is a first data bus for transferring instructions output from ROM 13; 17 is a data bus for transferring data between CP (J 11 and pseudo-instruction conversion circuit 14.Bit; ALU 12 and RAM 18 for storing operation results); A second data bus for transfer, 19 an interface circuit (1/F) external to the sequence control device, and 20 an address bus.

12 and 13 are an instruction layout diagram and an operation sequence diagram illustrating the operation of the sequence arithmetic processing device of FIG. 11. In the figure, 501 to 50/l are instructions, 501
a-501c, 502a to 502d, 50
3a to 503d and 504a to 5040 indicate cycles in the operating process.

Next, regarding the operation of the conventional sequence arithmetic processing device shown in FIG. 11, the instruction allocation diagram shown in FIG.
This will be explained with reference to the operation sequence diagram shown in FIG. C.P.
UI I reads the program written in the ROM13. The program read by this ROM13 is B
If it does not operate the itALLJ12, that is, if it is a CPU instruction, the lowest E bit of the program read from the ROM 13 is "O", and this is transmitted by the control signal line 15 to 811. 81. II 12, and even though it is output to the instruction conversion circuit I4, +3i1. AI
L112 does not operate, and the pseudo instruction conversion circuit 14 is in ROM1.
The instructions output from 3 are transferred as they are to the CPU III, and the CPU II decodes and executes the read instructions.

Next, if the program read from the ROM 13 by the CPU II is for operating the Bi L ALU 12, that is, if it is a special operation instruction, the most significant bit of the program read from the ROM 13 is "1", and this is the control signal line 15. The signal is output to the Bit ALU 12 and the pseudo-instruction conversion circuit 14. If you receive this, Bi
The tALU 12 performs bit data processing on the data held in the RAM 1B according to instructions (data) output from the ROM 13. At the same time, the pseudo instruction conversion circuit 14 converts the special operation instruction output from the ROM 13 into the CP
It is converted into a UII no-execute instruction (NOP) and output to the CPU II. The CPU 11 then decodes and executes the NOP, but enters the next cycle without external access. That is, while the CPU 11 is executing an instruction match signal cycle, the Bit ALU 12 executes bit data processing.

The above operations are shown in the instruction layout diagram in FIG. 12 and the operation sequence diagram in FIG. 13.
01 + 504 is CPU instruction, instruction 502.503
indicates a special operation instruction. Also, to explain the operation with reference to the operation sequence diagram in FIG. 13, in the cycle of the CI)U instruction 501, the C
PUII reads the instruction in the instruction reading cycle 501a.
The instruction is read from the OM 13, decoded in a decoding cycle 501b, and executed in an execution cycle 501c. In the cycle of the CPU instruction 504, the same cycle as in 1- is repeated to execute the instruction.

In addition, in the cycle when the special operation instruction 502 is executed by the BitALU 12, the CPU II receives the instruction converted into a no-executable instruction (NOP) from the ROM 13 in the cycle 502.
Read in a, decode in cycle 502b, cycle 5
Performs only the operation to be executed at 02C, and at the same time executes the special operation at Bit ALU12.
I'm running 2d. The same applies to the special operation instruction 503.

[Problems to be Solved by the Invention] The sequence arithmetic processing device, which is a conventional data processing device shown in FIG. 9, is configured as described above.
Even if we use U1 to perform sequence operations,
The CPU 1 reads the instruction, decodes the sequence operation instruction, and then the sequence operation control unit 4 executes the instruction from -C. Therefore, while the CPU 1 is reading the instruction, the sequence operation control unit 4 does not execute the instruction. Therefore, while the sequence calculation control unit 4 is executing sequence calculations, the CPU is unable to read instructions.
- There was a problem that the processing time for sequence calculations increased.

By the way, as a means to solve the above-mentioned problem that the processing time of sequence operations becomes long, a method has been disclosed, for example, in Japanese Patent Application Laid-Open No. 62-38902.''-2
A sequence arithmetic processing device shown in FIG. 1t has been proposed. This device executes special operation processing, which is sequence operation processing, only in the CPU II instruction reading cycle.
In executing special operations, there is no need for the CPU II to set data in the arithmetic unit, making it possible to perform high-speed special operations. However, when using a CPU II that is capable of issuing an instruction briff match signal for the purpose of improving data processing performance, the data processing device executes a special operation instruction for which a brief match signal has been given nine times more than the instruction currently being executed by the CPU II. Since special calculation processing is also performed for
When exception processing such as interrupt processing occurs in the CPU II and the CPU returns from this exception processing, the special operation instruction that was not executed by the CPU II as a non-executable instruction will be executed again even though a brief match signal has been sent to the CPU II. Therefore, there is a problem that the calculation result becomes invalid, and therefore it is not possible to recover quickly. Also, C.P.
If there is a special operation instruction within the range where a brief match signal is possible after the U instruction, and the above CPU instruction is an instruction that uses the special operation result, the special operation that is to be used by decoding the CPU instruction The result is the result of a special operation performed by the instruction's briff match signal, which is then transferred to the CPU II
This causes a problem in which the instruction ahead of the instruction that the
Considering the brief match signal of U, 11 instructions, CP
It is necessary to place a special operation instruction after a dummy instruction is placed after the Ll instruction, and as a result, there is a problem in that the total amount of instruction memory increases.

This invention consists of 1. This was done to solve the problems mentioned above, and the CP [,
Even when using J, special operation instructions, which are sequence operation instructions, can be read and executed at the same time, increasing data processing speed, and C
When an exception processing such as an interrupt processing occurs in P tJ, even when returning to special operation processing from the above exception processing, the special operation result can be returned quickly without becoming invalid, and the amount of instruction memory is small. The object of the present invention is to obtain a data processing device that requires less data.

[Steps for Solving the Problems] The data processing device according to the present invention uses a C5 PU that can read, decode and execute instructions from memory according to a machine cycle, and that can generate an instruction brief match signal. C
Allows the PU to continue reading, decoding, and executing instructions,
When a special operation instruction is issued, the CPU reads and executes a non-executable instruction, and also includes an address determination circuit that determines whether or not to execute the special operation by determining the address of the memory where the special operation instruction was stored. When the special operation is determined to be executable based on the judgment result, the special operation instruction is decoded and executed, and the information inside the data processing device is transferred to the memory by the instruction from the CPU. The information in the memory L can be saved or restored into the data processing device.

Further, a data processing device according to another aspect of the present invention is a CP capable of reading, decoding, and executing instructions from a memory according to a machine cycle, and capable of generating an instruction brief match signal.
U determines whether reading from memory, decoding, and execution is a normal execution instruction or special operation instruction, and whether it is a special operation invalidation instruction that is set to be read from memory, decoding, and execution. C from the time it is determined to be a special operation invalidation instruction.
Until a reset command is issued by the PU or the special operation restart instruction is read from the memory by the CP (J), there is a special operation invalidation instruction determination means that holds the special operation invalidation signal, and the address where the special operation instruction is stored is set a predetermined number of times. address match determination means for determining whether or not the address matches the address in which the special operation instruction executed within A central processing unit capable of prefetching the operation invalidation instruction determination means and the address match determination means allows the CPU to continue reading, decoding, and executing instructions read from memory, and also allows the CPU to continue reading, decoding, and executing instructions read from memory, and also allows the CPU to continue reading, decoding, and executing instructions read from memory. When an invalidation instruction or a special operation restart instruction is issued, the CPU reads and executes the non-executable instruction, and if the special operation invalidation signal or address match signal is valid, the special operation is not executed and the special operation instruction is detected. The special operation is executed when the signal is valid and the special operation invalid signal and address match signal are invalid.

[Operation] When the data processing device according to the present invention executes a special operation instruction, the CI) U decodes and executes the instruction and at the same time executes the special operation instruction read into the data processing device. Processing time is reduced.

Furthermore, the address determination circuit and the sequence operation stack control circuit make it possible to easily and rapidly return from exceptional processing such as interrupt processing that has entered the CPU during execution of a special operation.

Further, a data processing device according to another invention of the present invention includes:
When a special operation instruction is executed, a no-execution instruction (N
Since the special operation instruction read into the data processing device is executed at the same time as the OP) is decoded and executed, the execution processing time for the special operation is shortened, and the address match determination means can also prevent exceptions such as interrupt processing. There is no need for any processing when returning from processing, and special operations can be performed at high speed.
and can be executed accurately. In addition, a C
Since the special operation instruction can be placed immediately after the PU instruction, the increase in the amount of instruction memory can be suppressed even when the number of instructions for which the CPU brief match signal is possible is large.

[Embodiment] FIG. 1 is a system configuration diagram showing a data processing apparatus as an embodiment of the present invention. In the figure, 1 is a central processing unit (C
PU), 2 is a memory that stores sequence operation instructions that are normal execution instructions or special operation instructions, and 101 is a CP
A sequence that reads out and decodes from memory 2 according to the address specification of U1, determines whether the execution is a normal execution instruction or a sequence operation instruction, and generates a sequence operation instruction detection signal 102 if the determination result is a sequence operation instruction. An arithmetic instruction detection circuit 103 is a sequence 9-- The arithmetic instruction detection signal 102 causes data to be read into the CPUI to be read from the memory 2 or a non-executable instruction 104.
When reading a sequence operation instruction, the data selector 105 determines whether the address of the memory 2 where the instruction was stored matches the address where the sequence operation instruction executed within a predetermined number of times was stored. Address determination circuit, 106 is address determination circuit 1
The address mismatch signal 107 becomes valid when the address mismatch occurs based on the judgment result of 05, and the address mismatch signal 107 latches the data from the memory 2 when the sequence operation instruction detection signal 102 and the address mismatch signal 106 become valid. An instruction decoder 108 determines the instruction of the decoder 107, the contents of the sequence operation register 6, the contents of the working memory AM7 at the address specified by the sequence operation instruction, and the contents of the address of the memory 2 where the sequence operation instruction was stored. When entering or returning from exception processing such as interrupt processing, the instruction of the instruction decoder 107, the contents of the sequence operation register 6, and the sequence are stored in accordance with the instruction 20- from the CPU 1. The contents of the working RAM 7 at the address specified by the operation instruction.

The contents of the address of memory 2 where the sequence operation instruction was stored can be saved to the sequence operation stack memory 109, or the sequence operation stack memory 1
This is a sequence calculation stack control circuit for returning from 09.

2 and 3 are operation sequence diagrams illustrating the operation of the data processing apparatus shown in FIG. 1. In the figure, 301~
315 and 401 to 420 indicate cycles in the operating process.

Next, the operation of the data processing apparatus according to the embodiment of the present invention shown in FIG. 1 will be explained with reference to the operation sequence diagrams shown in FIGS. 2 and 3.

The memory 2 outputs instructions from the corresponding address according to the address sent from the CPUI. The sequence operation instruction detection circuit 101 determines whether the instruction output from the memory 2 is a normal execution instruction of the CPU 1 or a sequence operation instruction, and if it is determined to be a normal execution instruction based on the determination result, An instruction from memory 2 is selected by data selector 103 and sent to CPU 1.
decodes and executes instructions. If it is determined that it is a sequence operation instruction, select and send the no-execute instruction 104 to C)) [J l using the data selector 103, and CPυ1 decodes and executes the no-execute instruction 104. At this time, the address determination circuit 105 determines whether the address of the memory 2 where the instruction was stored matches the address where the sequence operation instruction executed within a predetermined number of times was stored, and based on the determination result, the address If there is a mismatch, the instruction from the memory 2 is manually decoded by the instruction decoder 107, and then sent to the sequence calculation control unit 4.
Executes sequence operations on the working RA and sends the results to the working RA
Store in M7. At the same time, an instruction decoder 10 held inside the sequence operation stack control circuit 108
7, the contents of the sequence operation register 6, the contents of the address of the memory 2 where the sequence operation instruction was stored, and the information of the working RAM 7 are changed.

Also, by sending a command to the sequence calculation stack control circuit 108, the internal data of the sequence calculation stack control circuit 108 is saved to or restored to the sequence calculation stack memory 109.

When the above operations are shown in the operation sequence diagrams of FIGS. 2 and 3, cycles 301 to 315 are c p [J
1 indicates a cycle in which a normal execution instruction is read, decoded, and executed, and cycles 401 to 420 indicate cycles in which a data processing device executes a sequence operation. In the normal execution instruction cycle of CPU i, CPU
1 reads an instruction from memory 2 in a cycle 301, decodes the instruction in the next cycle 302, and executes the decoded instruction in a cycle 303.

Additionally, the CPUI executes the instruction's brief match signal in cycles 305-311 and waits for decoding and execution. At this time, if an exception process such as an interrupt process occurs as shown by A in FIG.
1-2 When returning from exception handling, the instruction is read and executed again. In a cycle in which a sequence operation instruction is executed, the CPU reads the instruction read from memory 2 as a non-executable instruction 104 in cycle 401, and in cycle 4
The operation is decoded in cycle 03 and executed in cycle 407,
The sequence operation is executed by the data processing device in a cycle 402 between an instruction reading cycle 401.

Furthermore, in cycle 4-04, 409, the CPU executes the instruction blit switch of the non-executable instruction 104, and at the same time executes the sequence operation corresponding to the instruction blifconitch in cycle 406.
, 410. At this time, if exception processing such as interrupt processing occurs as shown in B in Figure 3, C
P tJ 1 sends a brief match signal in cycle 414 and discards unexecuted instructions, and when it returns from the exception handling described above, it reads and executes the instructions again and sends a non-executable instruction 104 to CPU 1, but at that time If the address of the memory 2 is determined to be a match by the address determination circuit 105, no sequence calculation is performed. Furthermore, when performing a sequence operation during exception processing, the state can be easily controlled by issuing a command from the CP TJ 1 and saving and restoring information inside the data processing device.

In addition, in the address match determination means by the address determination circuit 105 corresponding to the sequence operation instruction in the above embodiment, when the initial setting instruction is issued from the CPUI, the address corresponding to the sequence operation instruction always does not match up to a predetermined number of times. It is determined that there is.

Further, FIG. 4 is a system configuration diagram showing a data processing apparatus which is another embodiment of the present invention.

In the figure, IIA is a central processing unit (CPU) capable of sending instruction briff match signals, 13A is an instruction memory that stores normal execution instructions or special operation instructions, and 21 is a CPU
Reads and decodes the instruction from the instruction memory 13A according to the address specification of the IA, and determines whether the execution is a CPU instruction or a special operation instruction,
special operation instruction determining means 23 for outputting a special operation instruction detection signal 22 when the determination result is a special operation instruction;
is the instruction memory 13A according to the address specification of the CPU 11A.
It is read and decoded from the instruction memory 13A to determine whether it is a special operation invalidation instruction set to be executed, and when it is determined that it is a special operation invalidation instruction, a reset command is issued by the CPU IA, or a special operation restart instruction is sent from the instruction memory 13A to the CPU IIA.
Outputs special operation invalid signal 24 until IA reads out,
Further, when the instruction read from the instruction memory 13A is a special operation invalidation instruction or a special operation restart instruction, special operation invalidation instruction determination means 26 outputs a special operation invalidation/resumption instruction detection signal 25; It is determined whether the address corresponding to the operation instruction matches the address where the special operation instruction executed within the set number of times was stored, and if the addresses match, the address match signal 2 is sent.
7, an address match determination means 28 reads out the instruction from the instruction memory 13A, decodes it, and executes it based on the special operation instruction detection signal 22, the special operation invalidation signal 24, the special operation invalidation/restart instruction detection signal 25, and the address match signal 27. When is a normal execution instruction, the CPU 11A reads the normal execution instruction, continues decoding and executing it, and when it is a special operation instruction, the pseudo instruction is used to make the CPU 11A read and execute the NOP instruction. Conversion circuit 14
When the special operation instruction detection signal 22 is valid and the special operation invalidation signal 24 and address match signal 27 are invalid, a special operation start signal 30 is generated to the data processing section 12A. It is a sequence control means for executing data calculations. 31 is an instruction decoder that decodes the instruction read from the instruction memory 13A in response to the special operation start signal 30 and outputs an execution instruction for the data operation control section 32; 33 is located within the data operation control section 32 and holds operation results; operation register, 18
is R in which data used to execute special operation instructions is stored.
AM, 34 is the address when a special operation is executed.
This is an address information update signal output from the sequence control means 28 in order to update the address stored in the match determination means 26. 35 is a RAM I that can read/write data from/to RAM I8 and can be accessed from both the CPU IIA and the data processing unit 12A.
/F.

5 and 6 show the data processing device of FIG. 4,
Instruction placement diagram and operation sequence diagram explaining the operation when exception processing such as interrupt processing occurs in the CPU, Part 7
8 are an instruction layout diagram and an operation sequence diagram illustrating the operation of the special operation invalidation instruction determination means in the data processing device of FIG. 4. In the figure, 601 to 60
7,610-613 and 701-706, 710-71
4 are instructions, 601a to 607a, 610a to 613
a, 60111-607b, 610b-61
31).

601c ~ 607c, 610c ~ 611c, 602
d ~ 607d, 701a ~ 706a, 710a ~ 7
14a, 701b-705b, 701c-705c, 7
10c to 712c and 704d to 705d indicate cycles in the operating process.

Next, 8-- of another invention of this invention shown in FIG. 4 above. The operation of the data processing device according to the embodiment will be explained.

The instruction memory 13A outputs an instruction from the corresponding address according to the address sent from the CPU IIA. The instruction output from the instruction memory 13A is determined by the special operation instruction determining means 21 as to whether it is a CPU instruction or a special operation instruction, and when it is determined that the instruction is a CPU instruction, the special operation instruction detection signal 22 is not output. Since the data selector signal 29 is not outputted from the sequence control means 28, the instruction outputted from the instruction memory 13A is selected by the pseudo-instruction conversion circuit 14 and outputted to the CPU IA. The CPU IIA reads, decodes, and executes the instructions. When it is determined that the instruction is a special operation instruction, the special operation instruction detection signal 22 is output, so that the data selector signal 29 is output from the sequence control means 28, and the NOP instruction is sent to the CPU IIA by the pseudo instruction conversion circuit 1.
4 is selected and output. CPU IIA reads, decodes, and executes NOPs. At this time, the address match determination means 26 determines whether the address where the special operation instruction was stored matches the address where the special operation instruction executed within the set number of times was stored, and determines whether the addresses match. When it is determined that the address match signal 27 is present, an address match signal 27 is output.

When the special operation instruction detection signal 22 is valid and the address match signal 27 and the special operation invalid signal 24 are invalid, the sequence control means 28 outputs the special operation start signal 30 to the data processing section 12A, and starts reading from the instruction memory 13A. After the command is input to the command decoder 31 and decoded, the data processing control unit 32 executes the data processing operation, and if necessary, the result is sent to the RAM through the RAM I/F 35.
18, and outputs the address information update signal 34 to the address match determining means 26 to update the address information in which the special operation instruction executed within the set number of times stored in the address match determining means 26 is stored. do.

In addition, if it is read and decoded from the instruction memory 13A and the execution is a special operation invalidation instruction, special operation invalidation +17
When the open instruction detection 1m- No. 25 is output, the data selector signal 29 is output from the sequence control means 28 to the pseudo instruction conversion circuit 14, so the N○P instruction is output from the pseudo conversion circuit 14 to the CPUIIA and decoded. - Executed. Next, when the special operation instruction is read from the instruction memory 13A, the special operation instruction detection signal 22 is output from the special operation instruction determination means 21, so that the CPU II/l outputs the NOP instruction and decodes and executes it. However, since the special calculation invalidation signal 24 is manually input, the sequence control means 28 does not output the special calculation start signal 30 and the address information update signal 34, so the contents of the calculation register 33 and the address match determination means 26 do not change. No special operations are performed. Next, CPUIIA reads the special operation restart instruction from the instruction memory 13A, or CPUIA directly reads it from instruction memory 13A.
By issuing a command to reset the special operation invalidation signal 24 to the special operation invalidation instruction determination means 23, the special operation invalidation signal 24 is reset, so that when the special operation instruction is read from the instruction memory 13A after that, it will be normal. perform calculations on.

31 The operation described in 1- will be explained with reference to the instruction layout diagrams and operation sequence diagrams shown in FIGS. 5 to 8. 7 In FIG. Shows CPU instructions in processing, 602~
607 indicates a special operation instruction. The above operation will be explained with reference to the operation sequence diagram in FIG.
The UIIA reads an instruction from the instruction memory 13A in an instruction reading cycle 601a, decodes it in a cycle 601b, and executes it in a cycle 601c.
At the same time as decoding the instruction read in step 11], the special operation instruction is read in cycle 602a, and then in cycle 601c.
At the same time as executing the instruction read in, cycle 60
The instruction is read in 3a, decoded in cycle 602b, and data arithmetic processing is executed in the data processing unit 12A in cycle 602d. In this way, CPUIIA
When executing a read instruction, the next instruction is read and decoded in advance, so that the next instruction can be executed immediately after the execution of the instruction is completed. At this time, if an exception process such as an interrupt process occurs as shown by A in FIG. Discards the instruction and decoding information corresponding to , and executes cycle 6 in interrupt processing
Execute steps 10 to 613. Next, when returning from the above interrupt cycle, the CPU IIA reads, decodes, and executes the instruction C; Cycle 60 of reading instructions after interrupt handling
4a and 605a are executed again, the special operation instruction detection signal 22 is output, and a NOP instruction is output to the CPUIIA, but special operation cycles 604d and 605d corresponding to cycles 604a and 605a are executed before interrupt processing. Therefore, the addresses corresponding to the instructions 604 and 605 are stored in the address match determining means 26, and the address match signal 27 is output to the sequence control means 28 during the instruction reading cycle when returning from interrupt processing. Therefore, the special operation start signal 30 and address information update signal 34 are not output, and the same special operation (cycles 604d and 605d) is not executed again.

Next, for the special operation instruction ζ in cycles 605 and 607, the address information is the address match determination means 26.
Since the address matching signal 27 is not stored in the address matching signal 27, the special calculation is performed without outputting the address matching signal 27. From what has been said above, even if exception processing such as interrupt processing occurs during execution of special operations,
1. Since the special operation instructions 602 to 607 are executed only once, the operation results will not be invalid, and no operation is required for returning from exception handling.

Next, a case where a special operation instruction is placed after a CPU instruction that uses a special operation result will be described with reference to FIGS. 7 and 8. In Figure 7, 701.706 is C
CPU instruction for PUIIA, 702 is a special operation invalidation instruction to disable special operations, 703 is a subroutine instruction (SUB instruction) for direct use of special operation results by CI), 704 to 705 are the above Special operation instruction placed following subroutine instruction 703, 7
10 is a CPU instruction in a subroutine, 711 is a special operation restart instruction, and 712 is a return instruction from a subroutine (
RET command). To explain the above-mentioned data processing operation in the operation sequence diagram of FIG. 8, as explained so far, CPU IIA
The instruction is read, decoded by 701b, and executed by 701C. While decoding by 701b, the special operation invalidation instruction 702 is simultaneously read from the instruction memory 13A. At this time, the special operation invalidation command determination means 23 outputs a special operation invalidation/resumption command detection signal 25 and a special operation invalidation signal 24 to the sequence control means 28.

The sequence control means 28 outputs a data selector signal 29 to the pseudo instruction conversion circuit 14, and outputs a NOP signal to the CPU IA.
Output instructions.

Next, when executing cycle 701c, cycle 70
At the same time as the subroutine instruction 703 is read in cycle 3a, the NOP instruction is decoded in cycle 702b. Next, while executing the NOP in cycle 702C, the CPU IIA executes an operation of reading a special operation instruction in cycle 704a. At this time, the special operation instruction determination means 21 outputs the special operation instruction detection signal 22 to the sequence control means 28, so that the
The data selector signal 29 is output to the pseudo instruction conversion circuit 14, and the CPU IA reads the NOP instruction, but since the special operation invalidation signal 24 is output to the sequence control means 28, the special operation start signal 30 and address information are updated. Since the signal 34 is not output, the special calculation result and the contents of the address match determining means 26 do not change. this is,
The same holds true for 705a, which is the instruction reading cycle for the execution of cycle 703c. Then cycle 70
By executing 3C, the CPU enters a cycle in which subroutine processing is executed, and after using the special operation result in the instruction following the CPU instruction 710, the special operation restart instruction 711 is read in the special operation restart instruction 711.
1, the special operation restart command determination means 23 invalidates the special operation invalidation signal 24, makes the special operation invalidation/restart command detection signal 25 valid, and outputs it to the sequence control means 28, thereby controlling the CPU IIA. reads the NOP instruction, and then when the cycle for reading the special operation instruction comes, the special operation is ready to be executed. When the CPU returns from the subroutine processing by the decoding cycle 712b and the execution cycle 712c of the RET instruction 712, the CPU IIA reads out the special operation instruction 704 from the instruction memory 13A again in the cycle 704a. At this time, as explained above, since the special operation instruction detection signal 22 is output to the sequence control means 28 and the special operation invalidation signal 24 is not output, the CPU IIA
A NOP instruction is output to the CPU IIA to read and execute the NOP instruction, and a special operation start signal 30 is output to the data processing unit 12A to execute the special operation. The address information in the address match determining means 26 is updated by being outputted to the match determining means 26. Also,
Regarding the special operation instruction 705, as described above, by executing the special operation, the special operation can be executed at high speed while suppressing the increase in the instruction memory 13A.

[Effects of the Invention] As described above, according to the data processing device of the present invention, instructions are read out from memory, decoded and decoded according to the machine cycle.
A CP that is capable of execution and that can signal an instruction brief match.
U provides a decoder that reads from the memory, decodes it, and determines whether the instruction to be executed is a normal execution instruction or a special operation instruction. Based on the determination result, when the instruction is normally executed, the CPU is caused to continue reading, decoding, and executing the instruction. , when a special operation instruction is issued, an address determination circuit is provided that causes the CPU to read and execute a non-executable instruction, and determines whether or not to execute the special operation by determining the address of the memory where the special operation instruction was stored. When a special operation is determined to be executable based on the judgment result, the special operation instruction is decoded and executed, and the information inside the data processing device is saved in the memory by an instruction from the CPU. Alternatively, the information on the memory is returned to the inside of the data processing device, so the CPU executes special operations at the same time as the instruction is read, reducing the processing time for special operations, and also reducing the time required for interrupt processing, etc. It also has an excellent effect on exception handling, in that if special calculations are not performed within this exception handling, there is no need to issue commands, and special calculations can be executed at high speed. .

Further, according to another invention of the data processing device of this invention,
C that can read, decode, and execute instructions from memory according to the machine cycle, and can signal an instruction briff match.
The PU determines whether it is a special operation invalidation instruction that is read from memory, decoded, and executed, or whether it is a normal execution instruction or a special operation instruction, and whether it is a special operation invalidation instruction that is read from memory, decoded, and executed, and executes this special operation instruction. A reset command is issued by the CPU from the time it is determined to be an operation invalidation instruction, or a special operation restart instruction is sent from memory to the CPU.
A special operation invalidation instruction determining means holds the special operation invalidation signal as read by the controller, and determines whether the address where the special operation instruction is stored matches the address where the special operation instruction executed within the set number of times was stored. A special operation instruction judgment-1 stage and 1, a special operation invalidation instruction judgment means, and a prefetch of the address match judgment means are provided. The central processing unit (CI) that is capable of reading, decoding, and executing the instructions read from the memory (CI) causes the CPU to continue reading, decoding, and executing the instructions read from the memory, and in the case of a special operation instruction, special operation invalidation instruction, or special operation restart instruction, In addition to causing the CPU to read and execute a non-executable instruction, the special operation will not be executed if the special operation invalid signal or address match signal is valid, and if the special operation instruction detection signal is valid and the special operation invalid signal and address match Since the special operation is executed when the signal is invalid, even if an exception process such as an interrupt occurs while the special operation is being executed, the special operation can be executed normally and at high speed, and the instruction memory can be saved. Data equipment that requires a small amount 4
〇- It has the excellent effect of providing a good position.

[Brief explanation of drawings]

FIG. 1 is a system configuration diagram showing a data processing device according to an embodiment of the present invention, FIGS. 2 and 3 are operation sequence diagrams explaining the operation of the data processing device shown in FIG. 1, and FIG. 4 is a system configuration diagram showing a data processing device according to the present invention. FIG. 5 and FIG. 7 are instruction layout diagrams explaining the operation of the data processing device of FIG. 4, and FIGS. 6 and 8 are FIG. 4 is an operation sequence diagram explaining the operation of the data processing device, FIG. 9 is a system configuration diagram showing an example of sequence calculation processing in a conventional data processing device, and FIG. 10 is the sequence calculation processing device of FIG. 9. 11 is a system configuration diagram showing another example of a sequence arithmetic processing device which is a conventional data processing device. FIG. 12 is an operation sequence diagram explaining the operation of the sequence arithmetic processing device of FIG. 11. FIG. 13 is an operation sequence diagram illustrating the operation of the sequence arithmetic processing device of FIG. 11. I In the diagram, 1-... central processing unit (CPU), 2...
・Memo 18 3... Decoder, 4... Sequence calculation control unit, 5... Decode signal, 6... Sequence calculation register, 7... Working RAM, 8... Address bus, 9... ...Data bus, 11. IIA...
Central processing unit (CPU), 12...Bit data arithmetic theory unit (Bit, A1., U), 12A...
・Data processing unit, 13...Program read-only memory (ROM), 13A...Instruction memory, 14...
- Pseudo-instruction conversion circuit, 15...control signal line, 16
---First data bus, 17 ---Second data bus, 18 ---RAM, 19 ---Interface circuit (
I/F), 20...address bus, 21...-special operation instruction determination means, 22...special operation instruction detection signal,
23...Special operation invalidation instruction determination means, 24...Special operation invalidation signal, 25...Special operation invalidation/restart instruction detection signal, 26...Address-match determination means, 27...
-Address match signal, 28...sequence control means,
29...Data selector signal, 30...-Special operation start signal, 31...Instruction decoder, 32...Data operation control section, 33...Arithmetic register A register, 34...Address information update Signal, 35...RA
MI/F, 101 --- Sequence operation instruction detection circuit,
102...Sequence operation instruction detection signal, 103-...
・Data selector, 104...No execution instruction, 105・
-Address judgment circuit, 106...Address mismatch signal, 107...Instruction decoder, 108...Sequence operation stack control circuit, 109...-Stack memory for sequence operation, 201-220, 301-315゜401 -420... Cycle, 501 to 504... Instruction, 501 a to 501 c, 502 a to 5
02d. 503a to 503d, 504a to 504cm cycles, 601 to 607, 610 to 613 and 701 to 7
06,710~714...-Instruction, 601a~607
a, 610a ~ 613a, 601b ~ 607b, 6
10b-613b, 601c-607c. 610C-611c, 602d-607d, 701a
~706a, 710a ~714a, 701b~705
b, 701c-705c, 710c-712c, 704
d ~ 705d--cycle. In the figures, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oishi 44- Figure 7 Data Parallel SUB processing

Claims (1)

[Claims] 1. A central processing unit that is capable of reading, decoding, and executing instructions from memory and prefetching instructions according to a machine cycle determines whether the instructions read from the memory are normally executed instructions or not. A special operation instruction determination means for determining whether the instruction is a special operation instruction, and a special operation instruction determination means that uses the determination result to cause the central processing unit to read, decode, and execute an instruction read from the memory when a normal execution instruction is executed; At the time of an arithmetic instruction, a control means for causing the central processing unit to read and execute a non-executable instruction, and an address in the memory storing the special arithmetic instruction is an address where the special arithmetic instruction executed within a predetermined number of times was stored. an address match determination means that determines whether the addresses match and outputs an address match signal if the addresses match; If the address match signal is invalid, the special operation instruction, the contents of the special operation register, the address of the above memory where the special operation instruction was stored, and the contents of the working RAM at the address specified by the special operation instruction are stored in temporary memory. and a special operation execution control means for holding and executing special operations, and when an instruction is issued from the central processing unit to save internal information such as the special operation instruction, the special operation register, and the address corresponding to the special operation instruction. discharges the internal information onto the special operation stack memory, and when the central processing unit issues an instruction to store the discharged information again, the information on the special operation stack memory is stored internally again. What is claimed is: 1. A data processing device comprising: an information control means for controlling information; 2. A central processing unit that is capable of reading, decoding, and executing instructions from memory and prefetching instructions according to the machine cycle determines whether the instruction read from the memory is a normal execution instruction or a special operation instruction. and a special operation instruction determining means for determining whether the instruction read from the memory is a set special operation invalidation instruction, and from when it is determined that the instruction is the special operation invalidation instruction, the reset command is issued by the central processing unit. special operation invalidation instruction determination means for holding a special operation invalidation signal until the special operation restart instruction is issued or the central processing unit reads the special operation restart instruction from the memory; address match determining means for determining whether or not the address matches an address stored in a special operation instruction executed within the number of times, and outputting an address match signal when the addresses match; the special operation instruction determining means; Based on the determination results of the special operation invalidation instruction determining means and the address matching determining means, when a normal execution instruction is issued, the central processing unit is caused to continue reading, decoding, and executing an instruction read from the memory; When the special operation instruction is the above-mentioned special operation invalidation instruction or the above-mentioned special operation restart instruction, the above-mentioned central processing unit is made to read and execute the no-execution instruction, and the above-mentioned special operation invalidation signal or the above-mentioned address match signal is enabled. and a sequence control means that does not execute the special operation when the special operation instruction detection signal is valid and when the special operation invalidation signal and the address match signal are invalid, the special operation is executed. A data processing device characterized by: