JPH03222457A - Standard cell and automatic arranging and wiring method - Google Patents

Abstract

PURPOSE:To reduce the area of a standard cell by splitting a source contact area into two along the center line of a source contact vertically to a power source line or an earth line. CONSTITUTION:The widths Wp and Wn in contact with the ends of the standard cells in source contact region 4 and 5 are respectively equalized for a P channel transistor and an N channel transistor. Furthermore, the positions of the source contact regions 4 and 5 of the standard cells and the positions and number of source contacts 2, 6, 7, and 8 are accorded with each other, and the source contact regions 4 and 5 are split into two along the center line of the source contacts 2, 6, 7, and 8 vertically to a power source line 1 or an earth line 3. Hereby, it becomes possible to reduce the area and raise the integration degree by adding feed lines onto the source contact regions 4 and 5 communized.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a standard cell used for automatic placement and wiring of LSI etc. and an automatic placement and wiring method.

BACKGROUND OF THE INVENTION In recent years, integrated circuits have become larger and larger, and as a result, the circuit unit has changed from transistors to standard cells, such as NAND gates and flip-flops, reducing the amount of information handled during design and processing. Even though these standard cells are wired using automatic placement and routing to shorten the LSI design period, Figure 9 shows an inverter cell that is an example of a conventional standard cell. Figure 10 shows a NAND cell, which is an example of a conventional standard cell, in which input A 103, input B 105, and output 104 are input and output using two-layer metal wiring. It is something. Figure 11 is the 9th
This shows an example of wiring the standard cells shown in Figure 1 and Figure 10.
By connecting at 16, human power A 113 and human power B1
The logic of the output 115 for 14 can be configured as an AND logic, but by arranging multiple standard cells and wiring them as shown in Figure 11, it is possible to configure a complex logic. Problems to be Solved by the Invention However, in the case of the above-mentioned standard cell (Friend), when each adjacent standard cell has a source contact area, even though the source contact area can be shared as shown in FIG. Source contact region 12 in FIG.
3 and source contact region 127, source contact region 125, and source contact region 126, each has two source contact regions, and as a result, the area increases by the length shown in the figure, which increases the degree of integration. In addition, conventional automatic placement and wiring did not have the function of adding feed lines, and as shown in Figure 13, the wiring ran outside of the placed blocks, resulting in a large area.9The present invention This was done in view of the above issues.6 When there is a source contact region on both sides or one side of a standard cell,
A standard cell and an automatic placement and wiring method that make it possible to reduce the area by sharing the source contact area and by using automatic placement and wiring that adds a feed line on top of the shared source contact area. Means for Solving the Problems of the Invention (Above) Means for Solving the Problems The present invention aims to solve the above problems.When each standard cell has a transistor source contact region at one end, The widths in contact with the edges of the standard cell are made equal for the P-channel transistor and the N-channel transistor, respectively, and the position and number of the source contacts are matched with the position of the source contact region of the standard cell, and the source contact region is connected to the power supply line or the ground line. The present invention also applies to a standard cell that is vertically divided into two along the center line of the source contact. The contact widths are made equal for the P-channel transistor and the N-channel transistor, respectively, and the position and number of source contacts are matched with the position of the source contact region of the standard cell, and the source contact region is connected perpendicularly to the power supply line or the ground line. Furthermore, the present invention (
If each standard cell has source contact regions for P-channel and N-channel transistors at one end and source contacts for either P or N-channel transistors at the other end, then A source contact region of an N-channel transistor is provided, and the width of the source contact region at both ends of the standard cell is equal to L for the P-channel transistor and the N-channel transistor, and the width of the source contact region at both ends of the standard cell is equal to L. A standard cell in which the source contact area is divided into two along the center line of the source contacts perpendicular to the power supply line or the ground line by matching the position and number of the source contacts can also be used according to the present invention 1. Perform automatic placement and wiring using After removing the portion of the source contact area that does not include a transistor by performing automatic placement and routing using the placement and routing method. With the above configuration, the invention makes it possible to share the source contact area when the source contact areas of adjacent standard cells are in contact with each other, and further reduces the area by adding a feed line over the shared source contact area. Embodiment FIG. 1 shows a case where a standard cell has source contact regions of transistors at both ends, and shows the structure of an inverter cell which is an embodiment of the standard cell of the present invention. Diagram 1
In the figure, the width of the source contact region 4.5 in contact with the edge of the standard cell is Wp for a P-channel transistor, Wn for an N-channel transistor, and the position of the source contact regions 4, 5 of the standard cell and the source The position and number of contacts 2.6.7.8 are combined, and the source contact region 4.5 is aligned perpendicularly to the power line 1 or ground line 2 to the center line of the source contact 2.6.7.8. This is an inverter cell divided into two parts along the line. With this configuration, the source contact region 4I can be shared in connection with other standard cells as shown in FIG. 4, and the area can be reduced. Figure 2 shows a case where the standard cell has a source contact region of a transistor at one end, and is a block diagram of a two-man NAND cell which is an embodiment of the standard cell of the present invention. It is. Figure 2 (Source contact area 24.25.2
It is a two-man NAND gate in which 8 is divided into two along the center line of source contacts 23, 27, and 28 perpendicularly to the power supply line 21 or ground line 22, and the P channel source contact region 24.26 is divided into Wp and LN. Even if the source contact region 25 of the channel is made of Wn, the positions of the source contact region 24.26 and the source contact region 25 of the standard cell and the source contact 23.2
7. Even if the position and number of 28 are combined, as shown in Figure 4, in connection with other standard cells,
The source contact region 41 can be made common and the area can be reduced. FIG.
In Figure 3, a standard cell has source contact regions for P-channel and N-channel transistors at one end, and sources for either P or N-channel transistors at the other end. If there is a contact, a source contact region 35 of the other P-channel or N-channel transistor is provided, and the width of the source contact regions 33, 34, 35, 36 at both ends of the source contact region 33, 34, 35, and In addition, the positions of the source contact regions 33, 34, 35, 36 at both ends of the standard cell are matched with the positions and numbers of the source contacts, and the source contact regions 3
3.34.35.36 to power wire 31 or ground wire 32
Figure 4 shows one example of the automatic placement and routing performed using the standard cell shown in Figures 1 and 2. This is an example. For example, if the data of a standard cell is divided into two, add a flag L, and if it is not divided, add a flag O. If the flags are placed in the same way as the standard cell by automatic placement, and 11 combinations of flags are generated, source contact Since the areas are adjacent to each other, it can be recognized that they can be shared, so the automatic placement and wiring algorithm shown in FIG. 8 branches to a sharing routine to carry out the sharing. By making the source contact region 5 in FIG. 1 common, it is possible to reduce the area by the length D shown in FIG. 12 compared to the conventional automatic placement and wiring result shown in FIG. 11. Note that the standard cell of the present invention can be applied to gates other than those of the embodiments. FIG. 5 shows the automatic placement and wiring of the present invention performed on the standard cell shown in FIG. 3. Although it is possible to reduce the area by making the source contact region 51 common, FIG. 6 shows an example of the automatic placement and wiring of the present invention performed using the standard cell shown in FIGS. 1 and 2. This is an example. As shown in FIG. 8, the source contact regions 64 and 85 are shared, and a feed line 66 is passed over the source contact regions 64 and 65. As a result, conventionally, for example, cells A and B in FIG. 13 are connected. In this case, the wiring length is shortened by using the feed line 71 of cells C and D, which have a common source contact area, as shown in Fig. 7, instead of wiring as shown in Fig. 13. As a result, the wiring capacitance is reduced. Effects of the Invention: The standard cell and automatic placement and routing method of the present invention enable LSI
By designing a

[Brief explanation of drawings]

Fig. 1 shows the structure of an inverter cell which is an embodiment of the standard cell of the present invention. Fig. 2 shows the structure of a two-man power NAND cell which is an embodiment of the standard cell of the invention. FIG. 4 shows the configuration of a four-man NAND cell, which is an example of the cell. FIG. 5 shows the configuration of the standard cell shown in FIGS. Figure 6 shows the configuration of an embodiment in which a standard cell is automatically placed and routed according to the present invention. Figure 8 shows the flow of the automatic placement and wiring algorithm of the present invention. Figure 9 shows the configuration of the inverter cell of a conventional standard cell. Figure 11 shows the configuration of a two-man NAND cell using a conventional standard cell. Figure 12 shows the configuration of a conventional standard cell using automatic placement and wiring. FIG. 3 is a diagram showing wiring in an example when automatic placement and wiring is performed.

Claims (5)

[Claims] (1) When each standard cell has a source contact region for a P-channel transistor and an N-channel transistor at one end, the width of the source contact region in contact with the end of the standard cell is equal for the P-channel transistor and the N-channel transistor, respectively. , further characterized in that the position of the source contact region of the standard cell matches the position and number of source contacts, and the source contact region is divided into two along the center line of the source contacts perpendicular to the power supply line or the ground line. standard cell. (2) When each standard cell has source contact regions for P-channel and N-channel transistors at both ends, the width of the source contact region in contact with the end of the standard cell is P.
The channel transistor and the N-channel transistor are made equal, and the position and number of source contacts are matched with the position of the source contact region of the standard cell, and the source contact region is aligned perpendicularly to the power supply line or the ground line at the center of the source contact. A standard cell characterized by being divided into two along a line. (3) If each standard cell has source contact regions for P-channel and N-channel transistors at one end and source contacts for either P or N-channel transistors at the other end, the other A source contact region of a P-channel or N-channel transistor is provided, the width of the source contact region at both ends of the source contact region in contact with the end of the standard cell is made equal for the P-channel transistor and the N-channel transistor, and the source contact region of the standard cell at both ends is equal in width. A standard cell characterized in that the position of the contact region matches the position and number of the source contacts, and the source contact region is divided into two along the center line of the source contacts perpendicular to a power supply line or a ground line. (4) Automatic placement and wiring is performed using the standard cell according to any one of claims 1, 2, and 3, and when the source contact regions of adjacent standard cells touch each other, the divided source contact An automatic placement and routing method characterized by having a function of removing a portion of a region that does not include a transistor. (5) After performing automatic placement and wiring using the automatic placement and wiring method described in claim 4 and removing the portion of the source contact area that does not include a transistor, a feed line is added on top of the common source contact area. 1. An automatic placement and routing method characterized by having a function of: