JPH0322038A - Timing verification processing system - Google Patents

Abstract

PURPOSE:To quickly and efficiently execute the timing of a designed logic circuit by obtaining the timing time difference required for timing verification in accordance with a latched transition time difference, and comparing it with a reference value to detect the abnormality of the timing. CONSTITUTION:When one or plural corresponding event occurrence times are read out from an event memory 15, a subtracting means 19 calculates difference values from the present time to obtain transition time differences and stores them in a latch means 20. A timing discriminating means 21 directly uses transition time differences stored in the latch means 20 or calculates difference values between stored transition time differences to obtain one or plural timing time differences required for verification of the timing of the logic circuit. Obtained timing time differences are compared with corresponding reference values to detect whether the timing is abnormal or not, and the result is outputted as the output of a check primitive. Thus, the timing verification processing is quickly and efficiently performed.

Description

[Detailed Description of the Invention] [Summary] A model incorporating check primitives is provided for the purpose of processing timing checks quickly and efficiently regarding timing verification processing methods in logic simulations. In a processing method that verifies timing by executing logic simulation on a circuit, there is an event memory that manages the occurrence time of the event that occurred closest to the current time for each net of the model circuit, and an input net for each check primitive. A search table manages which input net to search for each time, and when an event occurs in the input net of a check primitive, one or more event occurrence times can be determined by searching the event memory according to the search table. means for determining, means for calculating a transition time difference between the identified occurrence time and the current time, and determining one or more timing time differences from the calculated transition time difference and comparing it with a corresponding reference value. and means for detecting timing abnormalities.

[Industrial application field]

The present invention relates to a timing verification processing method in logic simulation for verifying the timing of a designed logic circuit, and in particular to a timing verification processing method that allows timing checks to be processed quickly and efficiently. This is related to the application processing method.

Logic simulation examines whether the pulse width of the designed logic circuit is sufficient, whether the setup time is sufficient, whether the hold time is sufficient, and whether the delay Timing checks will be performed to check whether the race is over or not, and whether or not it is racing. This timing check process needs to be configured so that it can be executed quickly and efficiently.

[Conventional technology]

Conventionally, timing check processing in logic simulation has been carried out by providing primitives to perform verification processing for each check item, and by performing timing checks according to each primitive. Here, the brimitip corresponds to the basic unit of logic hard logic, and forms the basic unit of simulation calculation by defining the calculation relationship between input and output.

[Problem to be solved by the invention]

However, in such conventional techniques, timing is checked according to individual primitives, so
In terms of software, there was a problem in that the simulation processing time increased, and in terms of hardware, there was a problem in that the amount of material increased. Therefore, there was a problem that the timing check process in logical simulation could not be executed at high speed and could not be executed efficiently. The present invention has been made in view of the above circumstances, and aims to provide a new timing verification processing method that enables high-speed and efficient timing of designed logic circuits. be.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle structure of the present invention.

In the figure, l is a ξ simulation engine, which is configured by hardware and implements the present invention, and lO is a simulation execution means, which executes the ξ simulation of a logic circuit according to the event-driven method. The device that executes the processing, 11, is a model circuit management means that stores circuit description data (circuit connections, delay data, operation types, etc.) for timing check model circuits created by incorporating check primitives into logic circuits. things to manage, l
2 is a time wheel that manages internal events that are scheduled to occur according to the delay operation of the logic circuit; 13 is an input pattern management means that manages external events that are input to the input stage of the logic circuit; 14 is a timing check execution means that manages the time series data, and 14 is a timing check execution means that executes a timing verification process of a logic circuit by executing a simulation operation of a check primitive; 15 is an event memory; l6 is an input event flag memory that manages the occurrence time of the event that occurred closest to the current time for each net of the timing check model circuit; 17 is a search table that manages which input net among the input nets should be searched for each input net of the check primitive; 18 is a previous event occurrence time specifying means, which specifies one or more corresponding event occurrence times by searching the event memory 15 according to the search table 17; l9 is a subtraction means, which specifies the occurrence time of the previous event; 2 for calculating the transition time difference between the event occurrence time specified by the time specifying means l8 and the current time;
o is a latch means that holds the transition time difference obtained by the subtraction means 19, and 21 is a quigging judgment means that calculates the timing required for timing verification from the latched transition time difference. Timing abnormalities are detected by determining the difference in timing and comparing it with a standard check.

[Effect]

In the present invention, the simulation execution means 10 executes the logic simulation 3 on the tying check model circuit while referring to the model circuit management means 11, the time wheel 12, and the input pattern management 13 stages. After determining the occurrence state of the event at the current time in each net of the timing check model circuit, the event memory 15 and the input event flag memory l6 are updated and the timing check execution stage l4 is activated.

When activated in this manner, the previous event occurrence time specifying means 18 of the tie checking execution means 14 first refers to the input event flag memory 16 to determine whether an event has occurred on the input net at the current time. Detect check primitives. Then this check preξ
By searching the search table l7 using the input net where the event occurred as a key, one or more input nets related to the input net where the event occurred are searched, and then this searched one By searching the event memory 15 using one or more person names as keys, one or more corresponding event occurrence times are identified and read out. When one or more corresponding event occurrence times are read out from the event memory l5, the subtraction means l5
9 obtains a transition time difference by calculating a difference value from the current time and stores it in the latch means 20. Then, the tie determination means 21 uses the transition time difference stored in the latch means 20 directly or calculates a difference value between the stored transition time differences to determine the timing of the logic circuit. In addition to determining one or more timing differences necessary for verification of output as the output of the active.

As described above, according to the present invention, multiple types of timing verification can be realized according to one check primitive, so that tie verification processing in logic simulation can be processed quickly and efficiently. It will become.

〔Example〕

Hereinafter, the present invention will be explained in detail according to examples.

FIG. 2 shows the system architecture of the ξ simulation engine that implements the present invention. In the figure, l is a simulation engine, 2 is a workstation provided to start the simulation engine 1, and 3 is a bus that connects the simulation engine l and the workstation 2. ξ Selection engine l includes a control processor IQI and an input processor 102
, gate processors 103 - 106 , output processor 107 and internal bus 108 .

This control processor 101 executes interface control such as external events set from the workstation 2, and also controls the input processor 102.
, the gate processors 103 to 106 and the output processor 107, and the input processor 102 has a time management function for simulation processing, and controls internal events (events registered in the time wheel) and external events at the current time. The gate processor 103 executes the successive processing of ξ according to all the events read by the input processor 102.
The gate processor 104 executes fan-out expansion, the gate processor 105 executes fan-in extraction, and the gate processor 106 updates the net value of the logic circuit to be evaluated. The output processor 107 executes a logical operation of the gate from the number and the net value, and executes discipline processing of the event data. In the present invention, as explained in FIG. 1, a check primitive is defined as one of the primitives which is the basic unit of the simulation calculation, and a check primitive that performs timing verification processing for multiple inspection items is defined. The timing check model circuit is controlled by incorporating the defined check primitive into the logic circuit to be simulated, and the timing of the logic circuit is verified by running a logic simulation on the generated timing check model circuit. It is designed to ensure efficient execution. From now on, the tie approval verification process will be executed by the gate processor 106 as one of the simulation calculation processes.

Figure 3 shows check primitives defined for a two-circuit latch system, and Figure 4 shows check primitives defined for a two-circuit latch system, latch circuit A and latch circuit B. A timing check model circuit created by incorporating the circuit is illustrated. As shown in this figure, check primitives are prepared corresponding to the logic circuit units that require timing verification, take the input/output net of the logic circuit unit to be incorporated as input, and are not connected to other logic circuit units. The verification terminal is used as an output, and the arithmetic function for timing verification processing defined according to the function of the incorporated logic circuit unit is assigned. Hereinafter, for convenience of explanation, the check primitive shown in FIG. 3 defined for the latch system of these two circuits will be identified as check primitive 4. According to the assigned calculation function of the verification process, the checkbrit 4 determines the setup time, hold time, pulse width, etc. that the two-circuit latch system requires verification.
Timing verification processing such as racing and delay over is performed using one check primitive 4. Figure 5 illustrates the determination of normality/abnormality regarding setup time, hold time, pulse width, racing, and delay over.
In the figure, for example, CLKI-DI indicates "'CLK1" of check primitive 4 at the current time.
This indicates that when an event occurs on the net, the time difference between the current time and the event occurrence time that occurred closest to the current time on the "D1" net of check primitive 4 is calculated, and ""CLKI (H)” indicates the rising event of the “CLKI” net of check primitive 4, and “C L K l (L)” indicates the falling event of the “CLKI” net of check primitive 4.Next Next, an embodiment for realizing the arithmetic function of the timing verification process assigned to the check primitive 4 in FIG. 3 will be described in detail.

The structure of this embodiment is shown in FIGS. 6 and 7. Here, the purpose of the embodiment shown in FIG. 6 is to realize the verification process regarding the setup time, hold time, and pulse width, the criteria of which are shown in (1) to (3) of FIG. This is an example, and the example shown in FIG. 7 is an example for realizing the verification process regarding racing, delay over, and setup time whose judgment criteria are shown in (4) to (6) of FIG. .

First, the embodiment shown in FIG. 6 will be described. In the figure, l5
1 is the event memory explained in FIG. 1, l6 is the input event flag memory explained in FIG. 1, and 17a is a timing check table corresponding to the search table l7 explained in FIG. As shown in FIG. 8, the event memory 15 manages T, which is the occurrence time of the event that occurred closest to the current time, for each net of, for example, 500,000 gates of the timing check model circuit. Further, this event memory l5 is stored in the T. In addition to C.c., it also manages the settling event time, transition event time, etc. required for logic simulation processing. As shown in FIG. 9, the input event flag memory l6 manages whether or not an event has occurred in each input net at the current time, together with the type of event (rising, rising, falling). In the embodiment shown in FIG. 9, it is assumed that the timing check model circuit is configured according to a logic circuit based on, for example, four inputs.

As shown in FIG.
5 to which input net rpc of the check primitive 4 should be read.

Here, in the figure, the current time is indicated by Tc. To explain specifically, “CL K l ” at the current time
When an event occurs on the net, the event memory 15 is stored according to this timing check table 17a.
TI, c of the "CLKI" net and T, c of the "DI" net are read out from this. To explain in more detail, this timing check table 17a is as shown in FIG. It also manages what kind of timing verification processing the read T■ relates to.In other words, when an event occurs in the "CLKI" net at the current time, the TI,c of the "CLK 1" net is When it is read, it means that the pulse width verification of the “CLK 1” net will be performed, and the occurrence of an event on the “CLK 1” net at the current time causes the “Dl” net to be verified. T p
It will also be managed that when C is read, it means that verification of the setup time of latch circuit A is to be performed. As can be seen from the management contents of the timing check table 17a explained above, the processing target is determined by whether or not a flag is set in the corresponding part of the timing check table 17a in FIG. The verification items for the tie ξ with respect to the check brit 4 will be determined. From now on, the workstation 2 displays a setting screen as shown in FIG. 12 on the display screen that displays, for example, setup time, hold time, etc., and processes the operator to set timing verification items. It turns out.

? Returning to FIG. 6, reference numeral 30 is an input net address memory, and r p c information regarding the person network of each check result type 4 is stored in the event memory 15.
The one that manages which address is stored in the
31 is an input net address register consisting of four registers, which stores the address information of the input net of the check primitive 4 to be processed, which is read from the input net address memory 30; 32 is a multiplexer; 33 is a timing check control unit which selects one of the net address registers 3l and reads T■ information from the event memory 15, and 33 is a timing check control unit that controls the multiplexer 32 according to the tie checking table 17a to read out the T■ information from the event memory 15. 34 is T, which executes control of rpc information read from l5,
35 is a register that stores the current time T, 35 is a Tpc register that stores T, which is the time of occurrence of the event read from the event memory 15, and 36 is a subtracter that stores TC. A transition time difference is obtained by calculating the difference value between Tc in registers 3 and 4 and Tpc in a Tpc register 35. 37 is a transition time difference register which calculates the transition time difference obtained by a subtracter 36. 38 is a timing reference value memory,
A system that manages the reference values of setup time, hold time, and pulse width required for timing verification processing for each net of the timing check model circuit.
39 is a comparator, and transition time difference register 37
A timing verification process is performed by comparing the transition time difference with the corresponding reference value read from the timing reference value memory 38, and 40 is a judgment register that stores the judgment result of the comparator 39. It is something to do.

By executing the T/) logic simulation on the timing check model circuit, the r p c information at the current time is stored in the event memory 15, and
When the event occurrence information at the current time is stored in the input event flag memory 16, the timing check control unit 33 first stores the information in the input event flag memory 16.
By referring to , check primitives 4 in which an event has occurred on the input net at the current time are detected and one of them is identified, and this identified check primitive 4 is notified to the input net address register 31. , the address information regarding the input net of the specified check primitive 4 is stored in the input net address register 31.

Next, the timing check control unit 33 refers to the timing check table 17a using the input net in which the event of the identified check primitive 4 has occurred as a key, and selects one or more of the input nets related to the input net in which the event has occurred. Search multiple input nets. Through this search process, to explain using the example of FIG. 10, when an event occurs in the "CLKI" net at the current time, the "CLKI" net and the "D1" net will be searched. Next, the timing check control section 3
3 is the input net address register corresponding to this searched one or more input nets? By controlling the multiplexer 32 to select event memory l5
Read the corresponding T information from T pc register 3
5 is sequentially stored.

When the Tpc information is stored in the TI,c register 35 in this way, the subtracter 36 sequentially reads out the Tpc information.
At each time, the transition time difference is calculated by calculating Tc-T,c and stored in the transition time difference register 37, and the comparator 39 stores the transition time difference in the transition time difference register 37 and the tie reference value memory. Timing verification processing is performed by comparing the timing with the corresponding reference value read from 38. With this process,
Verification processing regarding the setup time, hold time, and pulse width, the criteria of which are shown in (1) to (3) of FIG. 5, will be executed.

Next, a description will be given of the embodiment shown in FIG. 7 for realizing the verification process regarding racing, delay over, and setup time, the criteria of which are shown in (4) to (6) of FIG. 5.

In the figure, 37a is a SKEW value register, and the subtracter 3
37b for storing the SKEW value determined by 6.
is a DELAY value register which stores the DB'LAY value obtained by the subtracter 36. Here, SKEW and DELAY are defined as DELAY=D2-CLKI SKEW=CLK2-CLKI, as shown in FIG. 38a is a hold time reference value memory that constitutes the timing reference value memory 38 and stores the hold time reference value for latch B; 38b is a setup time reference value memory that constitutes the timing reference value memory 38; 4l, which stores the reference value of the setup time for latch B;
is a subtracter, and DE of the DELAY value register 37b
DF value is determined by calculating the difference between the LAY value and the SKEW value register 37a (7) SKEW value, 42
43 is a DF value register that stores the DF value obtained by the subtracter 41, and 43 is a reference value register for latch B read out from the hold time reference value memory 38a and the setup time reference value memory 38b. 44 is a comparator which compares the DF value of the DF4 direct register 42 with the reference value of the hold time regarding latch B read from the reference value register 43. 45 is a comparison result register which stores the comparison result of the comparator 44; 46 is a comparator which stores the DF value of the DF value register 42 and the setup time for latch B read from the reference value register 43; 47 is a comparison result register that stores the comparison result of the comparator 46; 48 is a racing abnormality determination processing unit that determines whether there is a racing abnormality based on the data stored in the comparison result register 45; 49 is a delay over determination processing unit that determines whether or not there is a delay over based on the DF value of the DF value register 42 and the data stored in the comparison result register 47; 50 is a set amplifier; The time abnormality determination processing section determines whether or not the setup time is abnormal based on the DF value of the DF value register 42 and the data stored in the comparison result register 47.

SKEW value register 31a according to subtractor 36 in FIG.
When the SKEW value is stored in the DELAY value register 37b and the DELAY value is stored in the DELAY value register 37b, the subtracter 4l
calculates the DF value by calculating the difference between the stored DELAY value and SKEW value, and stores it in the DF value register 42. On the other hand, at this time, the reference value register 43 is configured to store the reference value of the hold time and the reference value of the setup time regarding the latch B related to the check primitive 4 being processed. .

In this way, when the necessary data is stored in the DF value register 42 and the reference value register 43, the converter 44
compares the DF value with the reference value of the hold time for latch B, and stores the comparison result in the comparison result register 45, and the racing abnormality determination processing section 48 determines whether or not there is a racing abnormality according to the comparison result. Determine whether Then, the comparator 46 compares the DF value with the reference value of the setup time for the rack B, and stores the comparison result in the comparison result register 47, and the delay over determination processing section 49 compares the comparison result with the
Using the positive and negative values of the F value, it is determined whether or not it is a delay overflow according to the criterion (5) in FIG. Then, it is determined whether or not there is a setup abnormality regarding latch circuit B according to the determination criterion (6) in FIG. Through these processes, verification processes regarding racing, delay over, and setup time, the criteria of which are shown in (4) to (6) of FIG. 5, are executed.

As described above, according to the present invention, it becomes possible to verify timings such as setup time, hold time, pulse width, racing, delay over, etc. regarding a two-circuit latch system according to one check primitive 4.

Although the illustrated embodiment has been described, the present invention is not limited thereto. For example, the application is not limited to a two-circuit latch system.

〔Effect of the invention〕

As explained above, according to the present invention, multiple types of timing verification can be realized according to one check primitive ξ, so timing verification processing in a logical system can be performed quickly and efficiently. It will be possible to process

[Brief explanation of the drawing]

Figure 1 is a diagram of the principle structure of the present invention, Figure 2 is a system diagram of the simulation engine, Figure 3 is an explanatory diagram of the check prefix defined for a two-circuit latch system, and Figure 4. is an explanatory diagram of a timing check model circuit created for a two-circuit launch system, Figure 5 is an explanatory diagram of the judgment content of the tying verification process for a two-circuit latch system, and Figures 6 and 7 are 8 is an explanatory diagram of the data structure of the event memory. FIG. 9 is an explanatory diagram of the data structure of the input event flag memory. The figure is an explanatory diagram of the data structure of a timing check table, and FIG. 12 is an explanatory diagram of a list displayed for timing check table setting processing. In the figure, 1 is a simulation engine, 2 is a workstation, 10 is a simulation execution means, l1 is a model circuit management means, 12 is a time wheel, l3 is an input pattern management means, 14 is a timing check execution means, l5 is an event memory, 16 is a human event flag memory, 17 is a search table, 18 is a previous event occurrence time specifying means, 19 is a subtracting means, 20 is a latch means, and 21 is a timing determining means. An explanatory diagram of the judgment contents of the timing verification process of the latch system of two circuits. Figure 5. Figure 7. An explanatory diagram of the data structure of the event memory.
) Figure 10 SECO-1 0 SECI - 1 0 SEC2 - 1 0 SEC3 - 1 0 SEC4 - 1 0 SEC5 - 1 0 SEC6 - 1 0 SEC7 - 1 0 Fan Fan Fa Family Fan Fan Fan Fan Fa / Fan Fan Fan Fan Fan Fan Fa〉 Fan In O In O In ○ In 0 In 1 In 1 In 1 In 2 In 2 In 2 In 2 In 3 In 3 In 3 In 3 Rise Fa LL [Vent Event Rise Fa LL Event E vent Rise FatL Event E vent Rise FaLI E vent Event Specified identification flag generated Ill-defined identification flag generated Sneaking flag generated, innocent flag generated Ill-defined identification flag determined Identification flag Naradai identification flag Yasei Arisanbetsu flag Occurrence Untranslated flag Definition Deception flag
Figure: Explanatory diagram of the data structure of the timing check table (I
I) Figure 11: Explanatory diagram of the list displayed for timing check table setting processing Figure 12

Claims (1)

[Claims] A device is prepared corresponding to a logic circuit unit that requires timing verification, and the input/output net of the logic circuit unit is used as an input, and the verification terminal that is not connected to other logic circuit units is used as an output. By defining check primitives, creating a timing check model circuit by incorporating the check primitives into the designed logic circuit, and executing logic simulation processing on the timing check model circuit, the designed logic In the timing verification processing method for verifying the timing of a circuit, each net of the timing check model circuit has an event memory (15) that manages the occurrence time of the event that occurred closest to the current time, and an event memory (15) that manages the occurrence time of the event that occurred closest to the current time, and For each input net of a primitive, a search table (1
7) When an event occurs in the input net of the check primitive at the current time according to the logic simulation process, one or more corresponding event occurrence times are identified by searching the event memory according to the search table. Previous event occurrence time identification means (
18), a subtraction means (19) for calculating a transition time difference between the specified event occurrence time and the current time, and one or more subtraction means necessary for timing verification from the calculated transition time difference. a timing determination means (21) which determines the timing difference between the two and compares the timing difference with a corresponding reference value to detect the presence or absence of a timing abnormality, and outputs the result from the verification terminal of the check primitive. A timing verification processing method that is characterized by: