JPH03189872A - Logical verification method - Google Patents

Abstract

PURPOSE:To save a memory area used in logical verification and to accelerate the logical verification by handling wiring elements which comprise an electrical circuit and an electronic circuit as one active element, and permitting the wiring element to provide with the same delay value as that of the active element. CONSTITUTION:In a wiring delay input procedure, delay time is permitted to supply to the wiring to which delay is desired to supply, and at this time, the delay value is permitted to supply with the combination of the wiring element from terminal to terminal. For example, the delay time from a terminal 5 to a terminal 6, the delay time from the terminal 5 to a terminal 7, and the delay time from the terminal 5 to a terminal 8 are supplied. After that, a logical simulation program recognizes the wiring element to which the delay is supplied as the active element, and performs simulation, and displays a verification result. Thereby, it is possible to perform the logical verification handling the delay of the wiring element without changing a net list before inserting a delay element.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to logic verification in the design of electric circuits and electronic circuits, and particularly relates to a logic verification method that can handle wiring delays.

[Conventional technology]

FIG. 3 is a flowchart showing the steps in a conventional logic verification method that deals with wiring delays. Conventional logic verification methods involve creating a netlist (step 1), which creates a description of the connection relationships between each element of the circuit to be verified (hereinafter referred to as a "netlist"), and creating a delay time for wiring elements. The process consists of the following steps: insertion of a delay element (step 2), execution of a logic simulation program for logic verification (step 3), and display of verification results to display the results of logic verification (step 4).

The conventional logic verification method will be explained in more detail. When performing logic verification, first, in the netlist creation procedure of step 1, a netlist of the circuit to be subjected to logic verification is created. Thereafter, in the delay element insertion procedure of step 2, a delay element is inserted by changing the netlist l- created in step 1 for the wiring element for which it is desired to have a delay time.

For example, in the circuit shown in Figure 2, if the wiring elements from terminal 5 to terminal 6, from terminal 5 to terminal 7, and from terminal 5 to terminal 8 are to have delay times, delay elements 9 to 11 as shown in Figure 4 are connected to the network. Insert by changing list. Then, by assigning the delay time of each wiring element to the inserted element, it is possible to give the wiring element a pseudo delay time. After inserting the delay time, perform logic verification using a logic simulation program (Step 3)
) and display the verification results (step 4). In addition, in Figures 3 and 4, 12 to 15 are non-gates (NO
T GATE).

[Problem to be solved by the invention]

Since the conventional logic verification method is configured as described above, the netlist must be changed in order to insert the delay element, which causes the problem that the number of signals and the number of elements increase.

The present invention has been made in view of these points, and its purpose is to provide a delay time for each wiring element without changing the netlist before inserting a delay element. The object of the present invention is to obtain a logic verification method that can perform logic verification that deals with delays.

[Means for Solving the Problems] In order to achieve such an object, the present invention includes an electric circuit,
As a simulation model when digitally verifying electronic circuits, the wiring elements that make up electric and electronic circuits are treated as one active element, and the wiring elements are allowed to have the same delay value as the active elements. It is something.

[Operation] In the ethical verification method according to the present invention, logic verification with a delay value can be performed using terminal-to-terminal combinations.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a flowchart showing the steps in one embodiment of the logic verification method according to the present invention. In this figure, the same or equivalent parts as in FIG. 3 are given the same reference numerals. The logic verification method shown in Figure 1 consists of a procedure for creating a netlist of the circuit to be verified (step 1), a procedure for inputting wiring delays to give the delay time of wiring elements (step 16), and performing logic verification. Logic simulation program execution procedure (
Step 3) and a verification result display procedure for displaying the results of logic verification.

This example will be explained in more detail. First, in step 1, a netlist creation procedure, a netlist of a circuit to be subjected to logic verification is created.

After that, in the wiring delay input procedure of step 16, a delay time is given to the wiring to which a delay is to be given. On this occasion,
Allows a delay value to be given by a terminal-to-terminal combination of wiring elements. For example, in the case of the circuit shown in FIG. 2, a delay time from terminal 5 to terminal 6, a delay time from terminal 5 to terminal 7, and a delay time from terminal 5 to terminal 8 can be given.

After that, the logic simulation program recognizes the wiring element given the delay as an active element, executes the simulation (step 3), and displays the verification result (
Step 4).

In the above embodiment, an example of logic verification of a logic circuit is shown, but a similar effect can be obtained in logic verification that takes into account wiring delays on a printed circuit board of an electric circuit.

〔Effect of the invention〕

As explained above, the present invention treats the wiring elements constituting an electric circuit or an electronic circuit as one active element, and allows the wiring element to have the same delay value as the active element. It is possible to prevent a change in the netlist and an increase in the number of nets and elements due to the insertion of , thereby saving the storage area used in logic verification and speeding up logic verification.

[Brief explanation of drawings]

FIG. 1 is a flowchart showing the procedure in an embodiment of the logic verification method according to the present invention, FIG. 2 is a logic circuit diagram showing an example of a circuit for performing logic verification, and FIG. 3 is a flowchart showing the procedure in a conventional logic verification method. The flowchart, FIG. 4, is a logic circuit diagram showing changes in the circuit when dealing with wiring delays in the conventional method.

Claims (1)

[Claims] As a simulation model for digitally verifying electric circuits and electronic circuits, the wiring elements that make up the electric circuit and electronic circuit are treated as one active element, and the wiring element is assumed to have the same delay value as the active element. A logical verification method that allows.