JPH05189513A - Logical simulation method taking delay into consideration - Google Patents

Abstract

PURPOSE:To provide an invalid event deleting method which can suppress the increase of the processing time end the memory capacity for the logical simulation. CONSTITUTION:The propagation expected output value and the propagation expected time are added to the information on a logical element. When an event is propagated, the propagation expected time of the logical element is compared with the present time. Then the event is propagated only when the coincidence is secured between both times (13), and the output value of the element connected to the output of the element propagated by the event is obtained (14). When a new event is registered, the propagation expected output value is rewritten into the new output value. Then the event registering time and the propagation expected time are rewritten into the value obtained by adding the element delay to the present time when the propagation expected time is equal to or smaller than the present time or when the new output value is different from the element output value. Otherwise no event is registered and only the propagation expected time is rewritten into the present time (15).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of logic simulation in which the delay time of a signal value is taken into consideration in a logic simulation for simulating the operation of a logic circuit on a computer. The method of excluding the event related to this pulse.

[0002]

2. Description of the Related Art In logic design of electronic circuits, logic simulation is a general method for verifying the design at the design stage. Although there are various methods for the logic simulation, several logic simulation methods have been proposed in consideration of physical characteristics such as delay of logic elements. These methods are shown, for example, in Iwanami Course Microelectronics 4, VLSI Design II, pages 191 to 220.

The event method, which is widely used as a method of logic simulation, is a method of tracing a portion where a signal value changes in a circuit in order. In this event method, the delay of the logic element can be handled by evaluating the event, that is, the information about the change in the signal value in the order of the time when the signal propagates.

Also, some models of delay of logic elements are known. Among them, the model called inertial delay is a model in which an element does not operate unless the same input value is applied for a specified delay time or longer. Furthermore, when performing an accurate simulation, the simulation is performed by setting the rising and falling delays for each element.

[0005]

When dealing with inertial delay,
Each time the output of the logic element is evaluated, the presence or absence of an event relating to the output value of the element is checked, and if it exists, it is invalidated, and the output change at that time is not registered as an event. Therefore, in the process of inertial delay, it is necessary to efficiently perform the method of checking the existence of an event and the method of deleting an event. As a method of invalidating registered events, conventionally, the purpose is to search the table that stores events each time the output of a logic element is evaluated, or to hold the storage location of the corresponding event for each element. A method has been used to easily find the event and delete it. However, the former method requires a great deal of time to search for an event, the latter method requires extra memory, and the table structure becomes complicated.

It is an object of the present invention to provide a method for judging invalidity of an event while preventing an increase in processing time and memory.

[0007]

In order to solve the above-mentioned problems, the present invention provides an area for storing the scheduled time of event propagation, that is, a scheduled propagation time, in a table storing information of each logic element. .. Then, when the output value of the logic element is evaluated, the propagation scheduled time is rewritten, and when the event is extracted and propagated to the output value of the logic element, if the scheduled propagation time and the current simulation time do not match, the event is Invalidate.

[0008]

[Operation] When the output value of the logic element is evaluated, the scheduled propagation time is simply rewritten, the event is extracted, and the scheduled propagation time is checked at the stage of propagating to the output value of the logical element, thereby performing processing by searching for the event. Increased time,
It is possible to prevent an increase in memory usage and complication of processing by configuring a complicated table.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a diagram showing an operation flow of a logic simulation according to the present invention. In FIG. 1, first, at 11, a table required for simulation is created, an initial event is registered, and a current time (simulation time) is initialized. Then, the processes 12 to 17 are performed for each time.
That is, 12 is a process of creating a list of events propagated at the current time from a table holding events that have not yet propagated. In 13, in the list created in 12, the change in the output value due to the event is propagated to the element whose scheduled propagation time of each element matches the current time. At 14, a list of elements connected to the output of the element to which the event propagates is created. In 15, the new output value is obtained for each element on the list created in 14, and the event is registered according to the relationship between the new output value and the current output value, the planned propagation output value, and the relationship between the current time and the planned propagation time. To do. At this time, the scheduled propagation time is also updated. At 16, the current time is advanced, and at 17 the end of the simulation is determined.

Of the above processes, the processes 13 and 15 which are characteristic processes of the present invention will be described in detail with reference to FIGS. 2 and 3 and FIGS. 4 and 5.

First, the table used for processing is shown in FIG.
Will be explained. There are five types of tables used for processing. The unprocessed event pointer UEP51 is a list holding the storage position of the unpropagated event held in the event table ET53 as an element. The number of elements is NUEP511. Evaluation target event pointer C
EP52 is a list holding the storage position of the event propagating at the current time as an element, and the number of elements is NCEP5.
21. The event table ET53 is a table for holding events, and each event has a logical element identifier LI.
D531, event propagation time PT532, propagation signal value PV533.

The logic element identifier LID531 of the element to which each event propagates is an identifier indicating the position in the logic element table. The propagation time PT532 shows the time when the event propagates, and the propagation signal value PV533 shows the value at which the output value of the logic element LID changes at the time PT.

For example, the first element of the event table ET, (LID = L2, PT = 5, PV = 0), is an event meaning that the output value of the logic element L2 changes to 0 at time 5. In the example of FIG.
An event is registered which means that the output value of 3 changes to 1 at time 5. Fan-out pointer F
OP54 is a table holding the identifier of the logic element connected to the output of the logic element to which the event has propagated, and the number of elements is NFOP541.

With respect to the element whose output value has changed in the processing of 13 of FIG. 1, the identifier of the element connected to the output is stored in this table in the processing of 14 of FIG.

The logic element table LT55 is a table for holding information of logic elements, and is composed of an output value V551, a planned propagation value PEV552, a planned propagation time PET553, a device type FN554, a fan-in FI555, a fan-out FO556 and a delay table DTBL557. .. Each row of this table corresponds to the logic elements L1 to L6 shown in FIG.

The output value V represents the output signal value of each logic element. The planned propagation signal value PEV and the planned propagation time PET indicate that the output value of the logic element is planned to change to the planned propagation signal value PEV at the planned propagation time PET. The element type FN is used to identify the function of the logic element. The fan-in FI is a list holding the identifier of the logic element connected to the input of that logic element. The fanout FO is a list holding the identifiers of the logic elements connected to the output of that logic element. The delay table DTBL is a table that holds the delay of the logic element, that is, the delay time of the element, and can handle different delay values depending on the change of the output value. For example, a delay value 5571 is shown when the output value changes from 0 to 1.

The logic element table LT55 shown in FIG. 5 represents the logic circuit shown in FIG. Logic element BUF of FIG.
(L1) is the first row L of the logic element table LT55 of FIG.
Equivalent to 1. The element type (FN) field 554 of the logical element table LT55 stores the type of the logical element, that is, BUF. Logic element BUF (L
The logical element AND (L
5) is connected. This information is the logic element table L
It is stored in the field of fan-out FO556 of T55. On the other hand, the logic element BUF (L1) and the logic element NOR (L4) are connected to the input (fan-in) of the logic element L5. As for this information, the identifier (L1 and L4) of the element is stored in the field of the fan-in FI555 of the fifth row L5 of the logic element table LT55. Similarly, the outputs of BUF (L2) and BUF (L3) are NOR (L
4), the output of NOR (L4) goes to AND (L5), A
The output of ND (L5) is connected to BUF (L6) respectively, and conversely, BUF (L2) and BUF (L3) are input to NOR (L4) and AND (L5) is input to BUF (L6).
Are connected in the fields of the fan-out FO 556 and the fan-in FI 555 of the logic element table LT55.

FIG. 2 is a flow of processing for deleting an invalid event and propagating a valid event. Here, processing is performed for the event indicated by each element of the evaluation target event pointer CEP. First, at 21 the counters C1 and C2 are initialized. The counter C1 is a counter used for sequentially referring to events. C2 is a counter used when re-registering valid events in order. 22 to 26 are processed for each event. At 22, it is determined whether the scheduled propagation time of the logic element identified by the logic element identifier LID of the event (ep) pointed to by the C1th element of the processing target event pointer CEP is equal to the current time Xt. If they are equal, 23 and subsequent steps are performed. If they are not equal, 25 and subsequent steps are performed.

Reference numerals 23 and 24 denote processes for propagating an event as a valid event. At 23, the propagation signal value PV of the event is written in the output value of the logic element. In 24, C is located at the C-th position of the processing-target event pointer CEP.
Write the first element and increment the value of C2. With this processing, only valid events are sequentially CEP
Held in. At 25, C1 is incremented. Two
At 6, the number of elements NCEP of C1 and CEP are compared to determine the end of the loop. When the processing is completed for all the elements of CEP, 27 is performed. At 27, C2 is set as the number of valid events and is set as the value of NCEP.

FIG. 3 shows a process of obtaining a new output value of the logic element and registering a new event. Here, the processes from 32 to 39 are performed for each element of the fan-out pointer FOP. First, at 31, the loop counter i is initialized. In 32, the new output value Vnew of the logic element pointed to by the i-th element (fp) of the fan-out pointer FOP, that is, the logic element pointed to by fp in the logic element table LT.
Is calculated from the type FN in the logic element table LT, the output value of the element connected to the fan-in FI of the element, the current output value V of the element, and the like. In 33, the expected output value PEV of the logic element is compared with the new output value Vnew. If they do not match, 34 or later is performed. If they match, that is, if they are not events, 38 or later is performed. At 34, the delay value d of the logic element is obtained by referring to the delay table DTBL,
The planned propagation output value is rewritten to the new output value PEV. At 35, it is determined whether the expected propagation time PET of the logic element is smaller than or equal to the current time Xt, or whether the current output value V and the new output value Vnew are different.

If the condition is met, 36 is carried out, and if not, 37 is carried out. 36 is a process for registering a new event, where fp is the logical element identifier LID, propagation time PT is the sum of the current time Xt and the delay value d, and the propagation signal value PV is the new output value Vnew, the event table ET and the unprocessed event pointer UEP. Register with. The expected propagation time PET in the logic element table is the sum of the current time Xt and the delay value d. In 37, the expected propagation time PET of the logic element table
Is rewritten to the current time Xt and no event is registered. In 38, the counter i is incremented, and in 39, the counter value i and the number N of elements of the fan-out pointer FOP.
The end of the loop is determined by comparing with FOP.

FIG. 12 is a block diagram of a system for executing this embodiment. This system inputs a circuit description file 121 and an input pattern file 122 and outputs a simulation result file and a simulation result list. The circuit description file 121 is a file in which information of a logic circuit is described, and stores information such as the connection relation of each logic element and the delay of each logic element. Input pattern file 1
22 stores information describing in time series the input signal given to the logic circuit for performing the simulation.

The processing unit 123 is composed of a CPU 1231 and a main storage unit 1232. The main storage unit includes a logic compiler 1241 for creating a logic element table 1242 from a circuit description file and a logic simulator 1243 for performing the logic simulation shown in this embodiment. It stores two programs. The logic element table 1242 and the event table 1244 are also held in the main memory. These tables are created by the logic compiler 1241 and the logic simulator 1243. A simulation result file 125 and a simulation result list 126, which are the processing results of the logic simulator 1243, are a file in which each signal output value of the logic circuit at the time of simulation is recorded and a print output list.

Next, regarding the logic circuit shown in FIG.
~ The progress of the processing of this embodiment will be described step by step with reference to Fig. 11.

FIG. 6 is a diagram showing the timing chart 61 at time 0 (Xt = 0) and the state of each table (62 to 65). L1 in the timing chart 61
To L5 correspond to the output values of the logic elements L1 to L5 in FIG. Before time 0, L1 and L2 are 1, and L3 to L5 are 0. At time 0, L2 changes from 1 to 0 (611). The event table ET64 holds two events. The event in the first row of these has a propagation time of 0, which is the change in L2 (61
It corresponds to 1). This event is fetched by the evaluation target event pointer CEP63 by the processing of 12 in FIG. Therefore, the first element of the evaluation target event pointer CEP63 becomes 1. Unprocessed event pointer UEP
62 holds the remaining event, that is, 2. After propagating this event, when the processing of 14 of FIG. 1 is performed, the element connected to the output of L2, that is, L4 is taken out to the fan-out pointer FOP65. The fan-out pointer FOP is created by referring to the fan-out FO field of the logic element table.

FIG. 7 is a diagram showing a state after performing the process 15 of FIG. 1 at time 0. Change in L2 at time 0 as shown in the timing chart 71 (711)
Causes the value of L4 to change to 1 at time 4 (712). This change is recorded as an event in the third line of the event table ET74, and the unprocessed event pointer UEP72 is added with a value of 3 indicating the third line of the event table ET. The planned propagation output value PEV752 and the planned propagation time PET753 of L4 of the logic element table LT75 are 1 and 4 at the same time as the new event. This time is obtained by the sum of the delay value obtained by referring to the delay table DTBL (557 in FIG. 5) existing for each element of the logic element table ET and the current time.

FIG. 8 shows the state at time 4. At time 4, the event 811 of L4 generated at time 0 propagates, and a new event 812 occurs in the element L5 connected to L4. In the process of 13 in FIG. 1, the scheduled propagation time of the logic element table is compared with the current time, and if they match, the event is propagated. The event 811 corresponds to the third row of the event table ET83, and the scheduled propagation time of the logic element table is 4, which propagates because it matches the current time. Then, the output value of the logic element L5 connected to the fan-out of the logic element L4 is obtained by the processing of 15 in FIG. 1, and this is registered as a new event in the fourth row of the event table ET83 and the evaluation target event pointer CEP82. Also, the expected propagation value PEV of L5 of the logic element table LT84
842 and the scheduled propagation time PET 843 have the same value 1 and the same time 11 as the new event.

FIG. 9 shows the state at time 5. At time 5, as shown in the timing chart 91, the event propagates to the output of the element L3 (911), which causes a new event 912 to occur in the element L4 connected to the output of the element L3. The event 911 corresponds to the event in the second row of the event table ET92, and the output value V931 of the element L3 of the logic element table LT93 changes to 1 by this event. Then, a new event occurs in the element L4 connected to L3. This event is event table ET92
Registered in the 5th line of. Also, the logic element table LT93
The planned propagation output value PEV 932 and the planned propagation time PET 933 in the L4 row of the same are 0 and 10 at the same time as the new event.

FIG. 10 shows the state at time 10. Time 10
Then, as shown in the timing chart 101, the event propagates to L4 (1011). However, no new event occurs in the element L5 connected to the element L4. This is because the interval between changes in the signal value of L4 is shorter than the element delay of L5, that is, L4 changes again before the event due to the change in L4 at time 4 propagates to L5, and thus the model of inertial delay The reason is that the change in signal value does not propagate. Event 1011 is event table ET1
Corresponds to the event in the fifth row of 02. Due to this event, the output value V of the element L4 of the logic element table LT103 changes to 0. Then, according to the flow of FIG. 3, a new output value of the element L5 connected to L4 is obtained. At this time, the logical product AN
Since the input of the logic element L5 which is D is 1 for L1 and 0 for L4, the new output value Vnew becomes 0. Since this value is different from the expected propagation output value PEV of 1 (see 932 in FIG. 9), the value in FIG.
33 is satisfied, and the process of 34 in FIG. 3 is performed. 34
Then, the delay value d is obtained by referring to the delay table DTBL. The expected propagation value PEV is the value of Vnew, that is, 0.
Be rewritten. And the scheduled propagation time 11 (933 in FIG. 9)
The current time is 10 and the output values V and Vn
Since both ew are 0 and equal, and the condition of 35 in FIG. 3 is not satisfied, 37 in FIG. 3 is executed, and the estimated propagation time PET (10
34) is rewritten to 10 which is the current time, and the process ends. Therefore, new events will not be registered.

FIG. 11 shows the state at time 11. At this time, as shown in the timing chart 111, there is an event 1111 scheduled to be propagated to L5, but this event is an event that was invalidated by the processing at time 10 and therefore does not propagate. Event 1111 is event table ET11
Corresponds to the event in the 4th row of 2. This event is also shown in Figure 2.
Propagation processing is performed according to the flow. However, according to the condition determination of 22 in FIG. 2, the estimated propagation time PET1134 (value is 10) of the logic element table LT113 is the current time,
That is, since it is different from 11, it is not a target of propagation.

As described above, a field for holding a scheduled propagation time is provided in the logic element table, this field is appropriately rewritten at the time of event registration, and an invalid event is detected by comparing this value with the current time at the time of event propagation. It becomes possible to delete this.

[0032]

According to the present invention, since it is not necessary to search for an invalid event from the already registered events at the time of event registration, it is possible to perform the logic simulation process according to the inertial delay model at high speed. Become.

[Brief description of drawings]

FIG. 1 is a flowchart showing a process of a logic simulation using the present invention.

FIG. 2 is a flowchart showing a process of propagating an event in the process of the logic simulation according to the present invention.

FIG. 3 is a flowchart showing a process of registering a new event in the process of the logic simulation according to the present invention.

FIG. 4 is a logic circuit diagram used to explain the operation of the present invention.

FIG. 5 is an explanatory diagram showing a table required for logic simulation according to the present invention.

FIG. 6 is a timing chart (a) at time 0 and an explanatory diagram (b) showing states of main tables.

FIG. 7 is a timing chart (a) at the stage when the processing at time 0 is completed and an explanatory diagram (b) showing the states of main tables.

FIG. 8 is an explanatory diagram showing a timing chart (a) at time 4 and states of main tables.

FIG. 9 is a timing chart (a) at time 5 and an explanatory diagram (b) showing states of main tables.

FIG. 10 is a timing chart at time 10 (a).
An explanatory view showing the states of the main tables.

FIG. 11 is a timing chart at time 11 (a).
And (b) an explanatory view showing states of main tables.

FIG. 12 is an explanatory diagram showing the configuration of a system for carrying out an embodiment of the present invention.

[Explanation of symbols]

11 ... Simulation initialization processing, 12 ... Creation processing of list of events to be processed at the current time, 13 ... Removal of invalid event and event propagation processing, 14 ... Creation of list of elements connected to output of element where event propagated Processing, 15 ... Registration processing of new event, 16 ... Advance current time, 17 ... Judgment of simulation end.

Claims (1)

[Claims] 1. A logic simulation in which a delay time of a signal value is taken into consideration, wherein an output value of the logic element, a planned propagation output value, and a planned propagation time are provided as information of the logic element, and the output value of the logic element The change information has a logic element identifier, a propagation time, and a propagation signal value.When a new output value to be propagated in the future is obtained for a certain logic element, the planned propagation output value and the new output value are different from each other. For example, rewriting the planned propagation output value to the new output value, and further, if the planned propagation time is equal to or smaller than the current simulation time, or if the new output value and the output value are different, the simulation time and the logic A value obtained by adding the delay time of the element is written as a new expected propagation time, and the identifier of the logic element, the new expected propagation time, the When a new event having a new output value as the logic element identifier, the event evaluation time, and the propagation signal value is registered, the scheduled propagation time is larger than the simulation time, and the new output value and the output value are equal. When the propagation scheduled time is rewritten to a time before the simulation time, and then when the content of the event is propagated to the output value,
Delay consideration characterized by rewriting the output value to the propagation signal value when the scheduled propagation time of the logic element through which the event propagates to the output value is equal to the current simulation time, and invalidating other events Logical simulation method.