JPS6270971A - Histogram calculator - Google Patents

Abstract

PURPOSE:To perform the histogram calculation at high speed even with the use of a memory element and the logic element of the ordinary access and arithmetic speeds, by using a means which processes the input data in terms of a pipeline. CONSTITUTION:Address registers 12-15 are provided to hold the data on the frequency and the address of each step as necessary for the pipeline operation. Then a coincidence detecting circuit 28 and a selection circuit 29 are added. In such a constitution, the circuit 28 detects the coincidence between registers 13 and 16. Then the circuit 29 receives a selection signal when said coincidence is detected by the circuit 28 and selects the 1-step preceding frequency data on a feedback line 30. Therefore the latest frequency data can be directly used with no intervention of a histogram memory even in case the input data of the same value are used continuously. Thus the frequency calculation is carried out normally.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention is used in cases where it is necessary to quickly calculate the frequency distribution of data in online data analysis, real-time video processing, etc. This invention relates to a histogram calculation device.

(Application as defense equipment) Most of the equipment is mainly operated outdoors, such as various image-guided missiles, various fire control devices that input and process images (for example, fire control devices for tanks), In order to respond quickly to battlefield monitoring equipment, it is necessary to process and respond to changes in the outside world in real time. The processing required here is video processing in which the content of the image frame changes from moment to moment, and it can be used to process objects that go up in flames due to being hit by bullets, the effects of various firearms, the effects of chaff decoys, and movement of position. The brightness of the entire input image (pixel density value) changes dynamically due to changes in sunlight.

Therefore, in order to accurately extract a target object, there is a need for a device that quickly calculates a histogram (distribution of pixel intensity values) of image data. The present invention speeds up the calculation of histograms, and has a high possibility of contributing to higher performance of future equipment.

(Prior art) The conventional method for calculating the frequency distribution of data is (1
(2) A method of calculating using a general-purpose computer; (2) A method of using a calculation device consisting of a dedicated memory and arithmetic unit.
There is a way.

In the method (1) of calculating using a general-purpose computer, processing is performed using a normal computer called a Neumann type computer. The configuration of a typical device using this method is shown in FIG. In this figure, an input device 40, an output device 41, a central processing unit 42, and a memory device (having the function of storing programs and data) 43 are interconnected by a data bus 44. The input data given to the input device 40 is sent to the central processing unit 40 according to a predetermined program.
and the memory device 43, and the histogram output thereof is outputted from the output device 41.

This method is highly flexible, as it can be used in combination with other processing, and is commonly used when processing time is not strictly constrained or when no special input/output format is required.

The method (2) using a dedicated computing device consisting of a dedicated memory and arithmetic unit is a method used when processing time is limited and extremely high-speed processing is required, such as when processing online or in real time. be.

The subject of the present invention is the method (2), and hereinafter a conventional histogram calculation method for this method will be described.

Assuming a general assumption that a plurality of pieces of data to be calculated are sequentially input to a histogram calculation device, the basic process flow regarding histogram calculation is as follows.

5step 1: Read the input data value,
Using this value as an address, the current frequency corresponding to the input data is read from the memory storing the histogram (histogram memory).

5tep 2: Add the value 1 to the read frequency.

5tep 3: Write the frequency to the read position (address) of the histogram memory.

However, operations such as initializing the histogram memory and outputting the histogram are omitted here. By repeating the above processing on the target data, a final histogram, that is, a frequency distribution can be calculated.

Conventionally, there is a histogram calculation device as shown in FIG. 3, which implements this processing flow using dedicated hardware. In FIG. 3, 4 is a memory (histogram memory) for storing intermediate results of the histogram. All processing operates based on this histogram memory 4. First, before starting the histogram calculation, it is necessary to initialize the contents of the histogram memory 4 to zero. In this case, the selection circuit 3 sends the addresses of the continuous address generation means 2h, etc. to the histogram memory 4, and the selection circuit 6
selects the initial frequency value (value zero) 7, and as a result, the histogram memory 4 is initialized.

Next, the operation during histogram calculation will be explained. First, the input data 1 selected by the selection circuit 3 becomes an address signal indicating the corresponding current frequency data in the histogram memory 4.

For example, if the input data value is 10, address 10 is specified, and the current frequency of the value 10 is stored at address 10. The frequency data read from the histogram memory 4 is passed through an arithmetic unit 5, incremented by 1, and then passed through a selection circuit 6 and written to the same address read out from the histogram memory 4. By sequentially repeating these operations (histogram updating) for input data, a histogram is calculated in the histogram memory 4 as a result.

Next, in the case of outputting a histogram, the selection circuit 3 selects the address from the continuous address generation means 2, and supplies this to the histogram memory 4 as a read address. As a result, each frequency of the histogram is sequentially output to the output line 9.

The read/write signal generating means 8 performs the initialization shown above,
A signal is provided for appropriately driving the update of the histogram and read/write operations for the histogram memory 4 performed on the output of the histogram.

(Problems to be Solved by the Invention) By the way, in the block diagram of Pt53 according to the conventional method, operations of reading and writing data to the histogram memory are performed in one histogram update process. Particularly when processing a huge amount of data, such as in image processing, the speed of access to the histogram memory becomes an issue. For the histogram memory, it is necessary to employ a memory element with extremely fast access speed, including the delay time when propagating to other components (selection circuit, +1 arithmetic unit). In order to increase the processing speed, high-speed memory elements and logic elements are required, and the device itself becomes expensive.

(Means for Solving the Problems) In view of the above points, the present invention provides a histogram that can perform histogram calculations at high speed even when using memory elements and logic elements with general access speeds and calculation speeds. The aim is to provide a computing device.

Generally, there are two concepts for speeding up processing: parallelization and pipelining. The present invention uses the latter concept of pipelining to speed up the processing of histogram calculations and solve the problem.

Hereinafter, a method for pipelining histogram calculation will be explained.

First, the histogram memory has two access paths so that read and write operations can be performed simultaneously.
Port RAM (2-vote random access memory) is used as histogram memory. Furthermore, to avoid contention, another 2-port RAM is used for histogram output. Furthermore, pipeline registers are arranged to hold the frequency and address data of each stage as necessary for pipeline operation.

Figure 4 shows a total of two 2-port RAMs, one for updating the histogram and one for outputting the histogram.
This is a reference example in which a three-stage vibration line operation of ep 1.5 tep 2.5 tep 3 is attempted (the reference example in FIG. 4 operates in a vibration line manner, but an accurate histogram cannot be obtained).

In the operation of 5 tepl in the ttS4 diagram, the current frequency corresponding to the input data 10 is stored in the frequency register 12, and the input data is stored in the address register 13.

In step ρ2, the output from the frequency register 12 passes through the +1 arithmetic unit 14, a value of 1 is added thereto, and is stored in the frequency register 15, and the contents of the address register 13 are transferred to the address register 16 as they are.

At 5tep 3, the selection circuits 19 and 20 select the contents of the renostas 15 and 16, respectively, and these are stored in the histogram memos 1jll and 2 which are composed of two-bottom RAMs.
1 and the write address, and the contents of the histogram are updated.

The initialization of the histogram memory in Fig. 4 is performed by selection circuit 1.
At 9.20, the initial frequency value 18 and the output from the continuous address generating means 17 are selected and executed. Further, the calculated histogram is stored in the histogram reading means 22.
is read out from the histogram memory 21 and output to the output line 23.

However, an accurate histogram cannot be obtained from the block diagram of the tIS4 diagram. The reason for this is that when input data of the same value continues, 5step 1 is written before new frequency data is written to the histogram memory in 5step 3. *5 steps
This is because 2 contains data based on old frequency data. It is naturally possible that input data with the same value continues. In this case, the calculation is performed using old frequency data for that data, and the correct frequency cannot be obtained.

FIG. 1 is a solution to the problem of the block diagram in FIG. 14, and is a complete implementation of the present invention.

(Example) Hereinafter, an example of the histogram calculation device according to the present invention will be described.
This will be explained according to the diagram S1. In order to solve the problem of the reference example shown in FIG. 4, a coincidence detection circuit 28 and a selection circuit 29 are added in FIG. 1 to the configuration shown in FIG. 4. A case where the address register 13 and the address register 16 are the same is detected by the coincidence detection circuit 28, and the selection circuit 29 which receives the selection signal when the coincidence is detected selects the frequency data of the feedback line 30 15 tep earlier. As a result, input data 10 with the same value
Even if this continues, it can be processed directly using the latest frequency data without going through the histogram memory, and the frequency calculation will work correctly.

Furthermore, it is assumed that the two-port RAM used in FIG. 1 satisfies the following specifications.

(1) In the case of a combination of reading and writing, simultaneous access is possible without the need for arbitration.

(2) When reading and writing are performed simultaneously to the same address, the written data is read out as is.

As explained above, the processing device shown in the embodiment of the present invention can correctly perform pipeline processing on histogram calculation.

(Effects of the Invention) As explained above, since the histogram calculation device of the present invention performs processing in a vibrating manner, it is possible to perform histogram calculations at high speed. Further, the problem of processing time can be solved by using a configuration using memory elements and logic elements that are inexpensive in access speed and operation speed and are commonly used. Since it uses a 2-port RAM, the circuit configuration is relatively simple. Since a 2-bot RAM is also used to output the histogram, there is flexibility in connection with other processing devices.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of a histogram calculation device according to the present invention, Fig. 2 is a block diagram of a histogram calculation device using a general-purpose computer, and Fig. 3 is composed of Tachikawa's memory and arithmetic unit. 4 is a block diagram illustrating a processing device dedicated to histogram calculation according to a conventional method.
The figure is a block diagram of a reference example in which three-stage pipeline processing is attempted. 1.10...Input data, 2,17...Continuous address generation means, 3,6,19,20.29...Selection circuit, 4゜11.21...Histogram memory, 5,1
4... +1 computing unit, 7, 18... Frequency initial value, 8
... Read/write signal generation means, 9, 23... Output line, 12° 13. 15, 16... Register, 22.
. . . Histogram reading means, 28 . . . - number configuration circuit.

Claims (1)

[Claims] (1) In a histogram calculation device that calculates the frequency distribution of data in data analysis, image processing, etc., there is a 2-port RAM for storing the intermediate result histogram of input data, and a 2-port R for outputting the calculated histogram.
A histogram calculation device comprising an AM and means for processing the input data in a pipeline manner.