JPH03218059A - Semiconductor device - Google Patents

Abstract

PURPOSE:To contrive the expansion of a function and characteristics, which is difficult in a signal semiconductor device, by a method wherein die pads for providing a plurality of semiconductor chips and the terminals of the chips are relayed by relay leads and are wire bonded. CONSTITUTION:This semiconductor device has a die pad 12 for providing a CMOS chip 11 and a die pad 14 for providing an MNO chip 13 and can withstand a stress to be applied from a resin, which is generated at the time of resin sealing. Then, the two die pads 12 and 14 are not put in a state that they are electrically connected to each other. Accordingly, even if substrate potentials of the respective chips 11 and 13 are different from each other, no problem is caused. Moreover, it is possible to connect a terminal 23 within the chip 11 with a terminal 24 within the chip 13 by wires 25 and 26 via a lead 21 having characteristics in form. By this connection, the device can be treated as one apparent functional block wherein the chip 11 comprises the NMOS chip 13.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a resin-sealed semiconductor device in which a plurality of semiconductor chips are housed in the same container.

2. Description of the Related Art In a conventional resin-sealed semiconductor device, one semiconductor chip is housed in one container.

A conventional resin-sealed semiconductor device will be described below.

Figure 3 is a plan view of a conventional resin-sealed semiconductor device.
is the semiconductor chip, 2 is the Guipad of semiconductor chip 1, 3 is the semiconductor chip
, 4 is a support lead called push tail (hereinafter abbreviated as fish tail) that supports the Guipad, 5
is the lead.

FIG. 4 is an external view of a conventional resin-molded semiconductor device, in which 6 is a sealing resin and 7 is a lead.

A conventional resin-sealed semiconductor device configured as described above will be explained.

A conventional example has one Gui pad 2 to house one semiconductor chip 1, and this Gui pad 2 is supported by fishtails 3 and 4 so as to withstand the stress generated during resin sealing. It is being

Problems to be Solved by the Invention In the conventional technology described above, only one semiconductor chip is sealed with resin, so the functions and characteristics that a semiconductor device containing one semiconductor chip can have are built-in. What can be achieved is limited by the semiconductor chip manufacturing process.

or. In order to overcome the above drawbacks, the Hive-Jet assembly technology has been considered, but in this case, a ceramic package is used, which has drawbacks such as high cost and low productivity. .

The present invention solves the above-mentioned conventional problems, and is a resin-sealed semiconductor device that makes it possible to expand the functions and characteristics that were difficult because it is a single semiconductor chip, and to reduce costs by using a resin-sealing method. is intended to provide.

Means for Solving the Problems In order to achieve this object, the resin-sealed semiconductor device of the present invention is provided with a plurality of die pads so that a plurality of semiconductor chips can be mounted thereon. has a structure that allows connection with wires via leads.

Function: With this configuration, it is possible to easily provide the functions and characteristics of multiple chips, which were difficult to provide in the past, in a single resin-sealed semiconductor device.

EXAMPLE An example of the present invention will be described below with reference to the drawings. In this embodiment, the plurality of semiconductor chips refers to two chips: a CMOS type one-chip microcomputer (hereinafter abbreviated as a CMOS chip) and an MNOS type non-luminescent memory (hereinafter abbreviated as an MNOS chip).

FIG. 1 is a plan view of a resin-sealed semiconductor device according to a first embodiment of the present invention. In FIG. 1, 11 is a CMOS chip, 12 is a die pad of the CMOS chip 11, and 13 is an M
NOS chip, l4 is a die pad of the MNOS chip 13, 15.16 is a lead that supports the guide pad 12 of the CMOS chip 11, 17.18 is a lead that supports the die pad 14 of the MNOS chip 13, and 19 is a lead that supports the die pad 14 of the MNOS chip 13. A support lead called an ish tail (hereinafter abbreviated as MNOS fish tail), 20 is a CMOS fish tail similar to 19, 21 is a lead with a characteristic shape, 22
Leads 23 are terminals in the CMOS chip 11, 24 are terminals in the MNOS chip 13, and 25 and 26 are wires, as in the conventional case.

FIG. 4 is an example of an external view of a conventional resin-sealed semiconductor device, and a similar external view of a resin-sealed semiconductor device according to an embodiment of the present invention.

The present embodiment configured as described above will be explained.

The first feature of this embodiment is that the die pad 12 of the CMOS chip 11 and the die pad 14 of the MNOS chip 13
It has two die pads.

In addition, these two die pads are attached to the CMOS chip 11 in order to withstand stress from the resin that occurs during resin sealing.
The die pad 12 of the MNOS chip 13 is supported by the leads 15 and 16 that support the CMOS chip 11 and the fishtail 20 on the CMOS side, and the die pad 14 of the MNOS chip 13 is supported by the leads 17 and 18 that support the die pad 14 of the MNOS chip 13 and the MNOS side. It is supported by the fishtail 19 of.

The second feature of this embodiment is that the two die pads 12.14 are not electrically connected, so even if the potentials of the substrates of the respective semiconductor chips 11.13 are different. no problem. Therefore, there is no problem even if the respective semiconductor chips 11 and 13 are manufactured in completely different semiconductor manufacturing processes.

The third feature of this embodiment is that the terminals 13 in the CMOS chip 11 are
and connect the terminal 24 in the MNOS chip 13 to the wire 25.2
6 can be connected.

This connection allows the CMOS chip 11 to be treated as one functional block in the same way as if the CMOS chip 11 had an MNOS chip 13.

Considering the above three features of this embodiment, a semiconductor chip made of, for example, a silicon substrate and a GaA
It is also possible to combine semiconductor chips made of compound semiconductor substrates such as s.

The shape of the leads is shown in FIG. 2, which is a plan view of a resin-sealed semiconductor device according to a second embodiment of the present invention. FIG. 2 shows the leads 15 and 16 supporting the die pad 12 of the CMOS chip 11 explained in FIG.
Leads 17.1 supporting die pad 14 of chip 13
8 is separated from each of the die pads 12.14 to create leads 27.28, 29.30 that can be handled in the same way as before. It has a durable structure by attaching a film-like support 31 to the back surface.

Effects of the Invention According to the present invention, by providing die pads for installing a plurality of semiconductor chips in the same resin sealing container, it is easy to share functions and characteristics that are difficult to achieve with a single semiconductor chip. It also makes it possible to reduce costs by resin sealing.

[Brief explanation of drawings]

FIG. 1 is a plan view of a resin-sealed semiconductor device according to a first embodiment of the present invention, FIG. 2 is a plan view of a resin-sealed semiconductor device according to a second embodiment of the present invention, and FIG. A plan view of a conventional resin-sealed semiconductor device, and FIG. 4 is an external view of the conventional resin-sealed semiconductor device.

Claims (1)

[Claims] A lead frame including a plurality of die pads on which a plurality of semiconductor chips are mounted and a relay lead for relaying and wire bonding between terminals of the plurality of semiconductor chips is used, and the plurality of chips are sealed with resin. Semiconductor equipment.