JPH03217944A - Enecking system for chip duplex system - Google Patents

Abstract

PURPOSE:To enable data check when it is outputted to a bus at a master side to be performed even when a fault occurs in an enable generation circuit at a slave side by checking the output of a data check circuit with the timing of an enable signal at the master side. CONSTITUTION:The data check circuit 12 which checks the output data of a master function chip 1a and a slave function chip 1b, and a timing circuit 13 which outputs the output of the data check circuit 12 which the timing of a master enable signal to control the sending timing of the output data of the master chip 1a to the bus 4 are provided. In words, since check is performed with the timing of the enable signal at the master side, a check timing is set at a time when the data is outputted from the master side to the bus 4 actually.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art (Figure 3) Means for Solving the Problems to be Solved by the Invention (1st Working Example (a) One Example Explanation (Figure 2) (b) Explanation of other embodiments Effect diagram of the invention) [Summary] A chip-duplex system in which chips with the same function are provided in duplicate, perform the same operation, and output data from one of them. Regarding the check method for checking the operation between chips, the purpose is to check the data at the time of bus output on the master side even if the enable generation circuit on the slave side fails, and it has the same function. In a chip duplication system in which multiple functional chips are provided, one is a master and the other is a slave, and the output data of the master functional chip is output on the bus by performing the same operation, the output of the master functional chip and the slave functional chip is It has a data check circuit that checks data, and a timing circuit that outputs the output of the data check circuit at the timing of a master enable signal that controls the timing of sending the output data of the master function chip to the bus.

[Industrial application field]

The present invention relates to a check method for checking operations between chips in a chip duplication system in which chips with the same function are provided in duplicate, perform the same operation, and output data from one of the chips.

In order to improve the reliability of equipment, error checking was actively performed.

For the purpose of improving reliability, a redundant system has been proposed in which chips with the same function are installed in duplicate, operate in the same way, and output data from one of them, and check the output data of both. has been done.

In this redundant system, it is required to perform error checking efficiently.

[Prior Art] FIG. 3 is an explanatory diagram of the prior art, in which FIG. 3(A) is an explanatory diagram of a chip duplication system, and FIG. 3(B) is an explanatory diagram of a conventional check method.

As shown in Figure 3 (A), the Chisop duplex system is
Two arithmetic chips Ia and 1b having the same arithmetic function are provided.

The figure shows a CPU (Central Processing Unit) and a bus (
Data bus A, data bus B) 4, control
, a memory control chip 3 and two arithmetic modules 1a and 1b are connected.

One of the calculation chips is a master chip 1a, and the other is a slave chip 1b, which have the same circuit configuration.

The calculation chips 1a and 1b take in data from the data bus B to the control device of the control chip 2 and execute the same calculations.

The calculation result of master chisub 1a is output to bus B,
The control chip 2 is notified, and the slave chip 1
Check circuit C of slave chip 1b
At H, it is checked with the calculation result of slave chip 1b,
The check result is notified to the control chip 2.

In this type of chip duplication system, in which the calculation chips Ia and 1b are duplicated, the same calculation is performed, and the calculation results of both are checked, the parity check and ECC check that are performed in one CPU are not required. It is attracting attention as

That is, the parity check and the ECC check provide redundancy to data and detect the occurrence of an error. For example, the parity check requires one additional bit.

Therefore, this additional bit requires an additional configuration on the circuit or bus, and requires a parity generator and a parity check, which increases the amount of material by about 20% compared to the one without the additional bit, resulting in cost. It becomes an amplifier.

However, if you duplicate the chips and stop the parity check, the cost will increase by the amount of chips, but the chimbu is L.
Since it is made by SI, the more you make it, the cheaper it becomes.

For this reason, duplicating chips is cheaper than adding parity.

In such a chip duplication system, data checking is essential, and conventionally this was done as shown in FIG. 3(B).

The master chip 1a outputs the calculation result from the dryer lOa to the bus 4 in response to the master pull signal MST-ENABLE.

The slave chip 1b takes in the master's output from the bus 4 with the receiver I1b, and EXOR (exclusive)
A data check circuit 12 consisting of an OR) circuit compares the slave output and the master output, and the comparison result is output as an AN at the timing of the slave enable signal SLVENABLE.
Timing circuit 13 composed of D (AND) gates
is output by

Note that lla is a bus receiver on the master side, and 10b is a pass driver on the slave side.

This makes it possible to check the computation outputs of the master and slave.

[Problem to be solved by the invention]

However, in the prior art, since the check is performed at the timing of the enable signal on the slave side, or only the data is checked, there are the following problems.

■ Since the timing of the enable signal on the slave side is checked, if the enable generation circuit on the slave side fails and the slave enable signal is not generated, both the master and slave will output. However, no data check is performed.

■ Since it only checks the data, if the enable generation circuit on the master side breaks down and issues a master enable signal without permission, the master chip la will appear on bus 4.
Data is erroneously output from the chip, causing a bus fight with other chips (memory control chip 3, etc.), but this cannot be detected.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a check method for a chip duplex system that allows data to be checked at the time of bus output on the master side even if the enable generation circuit on the slave side fails.

Another object of the present invention is to provide a check method for a chip duplex system that can detect a failure in the enable generation circuit on the master side.

[Means to solve the problem] The first layer 1 is a diagram of the principle of the present invention.

Claim (1) of the present invention, as shown in FIG. 1(A),
In a chip duplication system in which a plurality of function chips 1a and 1b having the same function are provided, one is a master and the other is a slave, the same operation is performed, and the output data of the master function chip 1a is output on path 4. A data check circuit 12 that checks the output data of the master function chip 1a and the slave function chip 1b, and sends the output of the data check circuit 12 to the output data path 4 of the master function chip la. It has a timing circuit 13 that outputs an output at the timing of a master enable signal that controls timing.

In addition, claim (2) of the present invention provides, as shown in FIG. 1(B), a plurality of functional chips la and 1b having the same function are provided, one is a master and the other is a slave, and they perform the same operation. In a chip duplex system that outputs output data of a master function chip 1a onto a bus 4, a data check circuit 12 checks the output data of the master function chip la and the slave function chip 1b, and a data check circuit 12 that checks the output data of the master function chip la and the slave function chip 1b, and a data check circuit 12 that checks the output data of the master function chip la and the slave function chip 1b, Send timing @? a master enable signal of the master function chip 1a to all;
The slave function chip 1b has an enable check circuit 14 that checks the slave disable signal of the slave function chip 1b.

[Operation] According to claim (1) of the present invention, since the check is performed at the timing of the enable signal on the master side, the check timing is when the output is actually output from the master side to the bus 4.

Therefore, even if the enable generation circuit on the slave side fails, the data is checked when the output data is output from the master to path 4, and the checkless state can be eliminated.

Note that there may be a failure in which the enable signal on the master side is not output, but in this case, the mask data is not output to the bus 4, so the data check is meaningless.

In addition, in claim (2) of the present invention, since the enable signals of the master and slave are checked, if the enable generation circuit on the master side fails, it can be detected immediately.
Never leave a bus fight unattended.

Furthermore, failures in the enable signal generation circuit on the slave side can also be detected.

〔Example〕

(a) Description of one embodiment FIG. 2 is a configuration diagram of an embodiment of the present invention.

In the figure, the same things as shown in Figures 1 and 3 are:
They are indicated by the same symbols.

The enable check circuit 14 is configured with an EX-OR circuit, and receives the input master enable signal MST-EN.
ABLE and slave enable signal SLV-ENABL
Matching or mismatching with E is detected, and when there is a mismatch, an enable error ENABLEERROR is output.

15 is an OR gate which performs an OR operation between the data error of the AND gate 13 and the enable error of the enable check circuit 14, and outputs an error -ERROR.

Reference numerals 16a and 16b each indicate enable permission gates, each of which is composed of an output inversion type AND gate, in which a high level master chip instruction +MASTER C H I P and a master enable signal are respectively set as a low level slave chip instruction SLA. V E C H IP and slave enable signal are input to the dryers 10a and 10b, respectively.
This is what is output to.

40 is an enable signal transmission line;
This is for transmitting a master enable signal from the slave chip 1b to the slave chip 1b.

When the master chip 1a and slave chip 1b are determined, a high level master chip instruction +MASTER-CH I P is input to the master chip la, the enable permission gate 16a is opened, and the driver 10a receives the master enable signal MST-. It is in a state where it is driven according to ENABLE.

On the other hand, a low-level slave chip instruction SLAVE-CH I P is input to the slave chip 1b, the ant' gate 16b is closed, and driving by the slave enable SLV-ENABLE of the driver 10b is prohibited.

Therefore, data output from the slave tip 1b to the bus 4 is prohibited.

Since the master block 1a and the slave chip 1b have the same configuration, when human data is given from the bus 4 and an operation is instructed, they execute the same operation, and when outputting the operation result, the master enable signal and the slave chip 1b are connected. -The enable signal goes up.

In the master chip la, the driver 10a is driven by the master enable signal and outputs the calculation result to the bus 4.

This calculation result is inputted to the slave chip 1b via the bus 4, and the master enable signal is inputted to the slave chip 1b via the transmission line 40.

In the slave chip 1b, the master operation result on the bus 4 is received by the receiver l1b and inputted to the data check circuit 12.

Since the data check circuit 12 is manually inputted with the slave operation results, it detects whether or not it matches the master operation results.If they do not match, it outputs a high-level disagreement output, and the timing circuit 13 outputs a high-level disagreement output at the timing of the master enable signal. Output as a data error.

The mask enable signal input to the slave chip 1b is checked with the slave enable signal by the enable check circuit 14, and if they do not match, a high level enable error is generated.

The outputs of the timing circuit 13 and the enable check circuit 14 are notified to the control chip 2 of FIG. 3A through the OR gate 15 as an error ERROR, for example.

In this way, data is checked at the timing of master enable, so when the master side outputs data to bus 4, the data is always checked. link is performed.

Furthermore, since the enable signals of the master and slave are checked, failure of the enable generation circuit on the master side can be immediately detected, and a bus fight condition will not be left unattended.

(1)) Description of other embodiments In the above-described embodiments, the duplication chip was described as an arithmetic chip, but other chips may be used.

Although the present invention has been described above using examples, the present invention can be modified in various ways according to the gist of the present invention, and these are not excluded from the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, the following effects are achieved.

■ In claim (1), since the data is checked at the master enable timing, the data check is always performed when the master side outputs data to the bus, and the data check is not performed due to a failure in the slave enable generation circuit. This will prevent you from being left behind.

■ In claim (2), since both the master and slave enable signals are checked, failure of the enable generation circuit on the mask side can be immediately detected, and bus fights are not left unattended. play.

[Brief explanation of drawings]

Figure 1 is a diagram of the principle of the present invention. FIG. 2 is a configuration diagram of an embodiment of the present invention. FIG. 3 is an explanatory diagram of the prior art. In the figure, 1a, 1b - functional chips, 4 Hass, 12-data check circuit; 13-timing circuit, 14=-enable check circuit.

Claims (2)

[Claims] (1) A plurality of functional chips (1a, 1b) having the same function are provided, one is a master and the other is a slave, and the master functional chip (1a, 1b) is connected to the bus (4) by performing the same operation.
In the chip duplication system that outputs the output data of a), a data check circuit (12) that checks the output data of the master function chip (1a) and the slave function chip (1b); A timing circuit (13) that outputs an output at the timing of a master enable signal that controls the timing of sending the output data of the master function chip (1a) to the bus (4). Check method. (2) A plurality of functional chips (1a, 1b) having the same function are provided, one is a master and the other is a slave, and the master functional chip (1a, 1b) is connected to the bus (4) by performing the same operation.
In the chip duplex system that outputs the output data of a), a data check circuit (12) that checks the output data of the master function chip (1a) and the slave function chip (1b), and a bus (4) for each output data. An enable check circuit (1) checks the master enable signal of the master function chip (1a) that controls the timing of sending data to
4) A check method for a chip duplication system, comprising: