JPH03215949A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH03215949A
JPH03215949A JP2011576A JP1157690A JPH03215949A JP H03215949 A JPH03215949 A JP H03215949A JP 2011576 A JP2011576 A JP 2011576A JP 1157690 A JP1157690 A JP 1157690A JP H03215949 A JPH03215949 A JP H03215949A
Authority
JP
Japan
Prior art keywords
semiconductor device
film carrier
insulating substrate
semiconductor chip
internal circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2011576A
Other languages
Japanese (ja)
Inventor
Fumio Miyagawa
文雄 宮川
Katsuya Fukase
克哉 深瀬
Toshiichi Takenouchi
竹之内 敏一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2011576A priority Critical patent/JPH03215949A/en
Publication of JPH03215949A publication Critical patent/JPH03215949A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Abstract

PURPOSE:To make it possible to modify easily the internal circuits of a semiconductor chip which is sealed, the number of leads, which are linked to the internal circuits, and the arrangement of the leads conforming to the number of the electrodes of the chip and the arrangement of the electrodes by a method wherein a film carrier comprising the chip is sealed in the interior of a resin along with the surface part, on which the carrier and the chip are mounted, of a substrate. CONSTITUTION:A film carrier 20 constituted by connecting electrodes 12 of a semiconductor chip 10 to internal circuits 30 is mounted on the surface of an insulating substrate 50 along with the chip 10, pads 32 are connected to lead 60 heads, which project on the surface of the substrate 50, of leads 60 provided in such a way as to penetrate the substrate 50 and at the same time, the carrier 20 comprising the chip 10 is sealed in the interior of a resin 80 along with the surface part of the substrate 50 to constitute a device. Thereby, the circuits 30 of the chip, the number of the leads, which are linked to the circuits 30, and the arrangement of the leads can be easily modified conforming to the number of the electrodes of the chip, which is sealed, and the arrangement of the electrodes.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、半導体装置、特に、半導体チップを樹脂内部
に封止した、汎用性のある半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a versatile semiconductor device in which a semiconductor chip is sealed inside a resin.

[従来の技術] 上記装置に類似する半導体装置として、従来、樹脂製の
PGA (ピングリッドアレイ)パッケージに半導体チ
ップを封入した装置がある。
[Prior Art] As a semiconductor device similar to the above-mentioned device, there is conventionally a device in which a semiconductor chip is enclosed in a resin-made PGA (pin grid array) package.

この装置では、その外部装置接続用のリードと半導体チ
ップの電極とを接続する内部回路を、パッケージ本体を
形成する樹脂基板表面に被着した銅箔をエッチング加工
して形成したり、またはポリイミドフィルム表面に被着
した銅箔をエッチング加工により内部回路に形成した後
、その内部回路をポリイミドフィルム表面から剥離させ
て、パッケージ本体を形成する樹脂内部に離脱不可能に
埋め込んだりして、パッケージ本体に容易に離脱不可能
に備えている。
In this device, the internal circuit that connects the external device connection leads and the electrodes of the semiconductor chip is formed by etching the copper foil adhered to the surface of the resin substrate that forms the package body, or by using polyimide film. After forming an internal circuit on the copper foil adhered to the surface by etching, the internal circuit is peeled off from the surface of the polyimide film and is irremovably embedded inside the resin that forms the package body. They are preparing for the possibility that they will not be able to leave easily.

また、外部装置接続用のリードを、その一部をパッケー
ジ本体を形成する樹脂内部に埋め込んで、パッケージ本
体に容易に離脱不可能に備えている。
Further, a lead for connecting an external device is partially embedded in the resin forming the package body so that it cannot be easily removed from the package body.

[発明が解決しようとする課題] ところで、近時の半導体ツプの種類の増加、即ち電極数
や電極の配列の異なる半導体チップの数の増加に伴って
、それに合わせて半導体装置の内部回路とそれに連なる
リードの数やその配列を容易に変更可能な汎用性のある
半導体装置の出現が望まれるようになった。
[Problems to be Solved by the Invention] Incidentally, with the recent increase in the types of semiconductor chips, that is, the increase in the number of semiconductor chips with different numbers of electrodes and electrode arrangements, the internal circuits of semiconductor devices have changed accordingly. It has become desirable to have a versatile semiconductor device in which the number and arrangement of leads connected thereto can be easily changed.

しかしながら、」二記半導体装置では、上述のように、
その内部回路やリードをパッケージ本体に容易に離脱不
可能に備えていて、その内部に封入する半導体チップの
電極数や電極の配列合わせて、その内部回路とそれに連
なるリードの数やその配列を容易に変更することができ
なかった。
However, in the semiconductor device described in Section 2, as mentioned above,
The internal circuit and leads are provided in the package body so that they cannot be easily removed, and by matching the number and arrangement of electrodes of the semiconductor chip sealed inside, the number and arrangement of the internal circuit and leads connected to it can be easily adjusted. could not be changed to .

本発明は、このような課題に鑑みてなされたもので、半
導体装置に封入する半導体チップの電極数や電極の配列
に合わせて、その内部回路とそれ3 に連なるリードの数やその配列を容易に変更可能な汎用
性のある半導体装置を提供することを目的としている。
The present invention has been made in view of these problems, and it is possible to easily adjust the number and arrangement of internal circuits and leads connected to the internal circuits according to the number and arrangement of electrodes of a semiconductor chip enclosed in a semiconductor device. The purpose of the present invention is to provide a versatile semiconductor device that can be changed.

[課題を解決するための手段l 上記目的のために、本発明の半導体装置は、絶縁フィル
ムに内部回路とそれに連なるパッドとを備えたフィルム
キャリアであって、その内部回路に半導体チップの電極
を接続してなるフィルムキャリアを、半導体チップと共
に絶縁基板表面に搭載して、前記パッドを、前記基板を
貫通させて備えたリードの基板表面に突出するリード頭
部に接続すると共に、前記半導体チップを含むフィルム
キャリアを、前記基板表面部分と共に樹脂内部に封止し
てなることを特徴としている。
[Means for Solving the Problems] For the above purpose, the semiconductor device of the present invention is a film carrier comprising an internal circuit and a pad connected to the insulating film, and an electrode of a semiconductor chip is attached to the internal circuit. A film carrier formed by the connection is mounted on the surface of an insulating substrate together with the semiconductor chip, the pad is connected to a lead head portion of a lead provided by penetrating the substrate and protruding from the substrate surface, and the semiconductor chip is It is characterized in that the film carrier containing the substrate is sealed inside the resin together with the surface portion of the substrate.

また、上記構成の本発明の半導体装置においては、内部
回路下方にあたるフィルムキャリアの絶縁フィルムまた
は絶縁基板に、グランド層を備えることを好適としてい
る。またそれと共に、絶縁基板裏面に突出するリード足
部を短丈に形成して、そのリード足部周囲にはんだバン
ブを形成するか、4 または絶縁基板裏面に突出するリード足部を長丈に形成
することを好適としている。
Further, in the semiconductor device of the present invention having the above structure, it is preferable that the insulating film or the insulating substrate of the film carrier below the internal circuit is provided with a ground layer. At the same time, the lead feet protruding from the back surface of the insulating substrate are formed short, and solder bumps are formed around the lead feet, or the lead feet protruding from the back surface of the insulating substrate are formed long. This is preferred.

[作用] ]二記構成の半導体装置においては、半導体チップの電
極を接続する内部回路とそれに連なるバンドとを備えた
フィルムキャリアと、そのフィルムキャリアの内部回路
に連なるパッドを接続するリードを備えた絶縁基板とを
、それぞれ別体に形成している。
[Function] ] The semiconductor device having the above two configurations includes a film carrier having an internal circuit connecting the electrodes of the semiconductor chip and a band connected thereto, and a lead connecting the pad connected to the internal circuit of the film carrier. The insulating substrate and the insulating substrate are each formed separately.

そのため、種々の数の内部回路とそれに連なるパッドと
を種々の配列で備えた大小の複数のフィルムキャリアと
、多数のリードを格子状などに備えた絶縁基板とを設け
ておき、上記フィルムキャリアから半導体装置に封入す
る半導体チップの電極数と電極の配列に合ったフィルム
キャリアを選択して、そのフィルムキャリアの内部回路
に半導体チップの電極を接続すると共に、そのフィルム
キャリアを半導体チップと共に上記絶縁基板表面に搭載
して、フィルムキャリアの内部回路に連なる複数のパッ
ドを、絶縁基板表面に突出する多数のリード頭部の全部
またはその一部にそれぞれ接続し、」二記半導体チップ
を含むフィルムキャリアを絶縁基板表面部分と共に樹脂
内部に封止することにより、種々の電極数と電極の配列
を持った半導体チップを封入してなる半導体装置を形成
できる。
Therefore, a plurality of large and small film carriers are provided with various numbers of internal circuits and pads connected to them in various arrangements, and an insulating substrate is provided with a large number of leads in a lattice shape. Select a film carrier that matches the number and arrangement of electrodes of a semiconductor chip to be encapsulated in a semiconductor device, connect the electrodes of the semiconductor chip to the internal circuit of the film carrier, and attach the film carrier together with the semiconductor chip to the insulating substrate. A film carrier containing a semiconductor chip as described in 2 above is mounted on the surface and a plurality of pads connected to the internal circuit of the film carrier are respectively connected to all or part of a number of lead heads protruding from the surface of the insulating substrate. By encapsulating the insulating substrate together with the surface portion inside the resin, it is possible to form a semiconductor device in which semiconductor chips having various numbers of electrodes and electrode arrangements are encapsulated.

あるいは、種々の数の内部回路とそれに連なるパッドと
を種々の配列で備えた複数のフィルムキャリアと、種々
の数のリードを種々の配列で備えた複数の絶縁基板とを
設けておき、そのフィルムキャリアと絶縁基板とから半
導体装置に封入する半導体チップの電極数や電極の配列
に合ったフィルムキャリアと絶縁基板とをそれぞれ選択
して、その選択したフィルムキャリアの内部回路に半導
体チップの電極を接続すると共に、そのフィルムキャリ
アを半導体チップと共に」二記選択した絶縁基板表面に
搭載して、そのフィルムキャリアの内部回路に連なる複
数のパッドを絶縁基板表面に突出する複数のリード頭部
の全部またはその一部にそれぞれ接続し、上記半導体チ
ップを含むフィルムキャリアを絶縁基板表面部分と共に
樹脂内部に封止することにより、種々の電極数と電極の
配列を持った半導体チップを封入してなる半導体装置を
形成できる。
Alternatively, a plurality of film carriers having various numbers of internal circuits and pads connected thereto in various arrangements, and a plurality of insulating substrates having various numbers of leads in various arrangements are provided, and the film Select a film carrier and an insulating substrate that match the number and arrangement of electrodes of a semiconductor chip to be enclosed in a semiconductor device from the carrier and insulating substrate, and connect the electrodes of the semiconductor chip to the internal circuit of the selected film carrier. At the same time, the film carrier is mounted together with the semiconductor chip on the surface of the selected insulating substrate, and the plurality of pads connected to the internal circuit of the film carrier are mounted on all or all of the plurality of lead heads protruding from the surface of the insulating substrate. By connecting the film carrier containing the semiconductor chip to the inside of the resin together with the surface portion of the insulating substrate, it is possible to create a semiconductor device in which semiconductor chips having various numbers of electrodes and electrode arrangements are encapsulated. Can be formed.

また、内部回路下方にあたるフィルムキャリアの絶縁フ
ィルムまたは絶縁基板にグランド層を備えた半導体装置
にあっては、内部回路をマイクロストリップ線路に形成
して、その内部回路を高周波信号を効率良く伝えること
ができる。
In addition, in semiconductor devices that have a ground layer on the insulating film or insulating substrate of the film carrier below the internal circuit, it is possible to form the internal circuit on a microstrip line to efficiently transmit high-frequency signals. can.

[実施例] 次に、本発明の実施例を図面に従い説明する。[Example] Next, embodiments of the present invention will be described with reference to the drawings.

第1図と第2図は多数の電極を持つ半導体チップを封入
してなる本発明の半導体装置の好適な実施例を示し、第
1図はその一部破断乎面図、第2図は第1図のA−A端
面図を示している。以下、この図中の実施例を説明する
1 and 2 show a preferred embodiment of the semiconductor device of the present invention, which encapsulates a semiconductor chip having a large number of electrodes. FIG. 1 shows an end view taken along line A-A in FIG. 1; The embodiment shown in this figure will be described below.

図において、10は、多数の電極12を所定の配列で持
つ半導体チップであって、その内部に所定の電子回路(
図示せず)を備えている。
In the figure, 10 is a semiconductor chip having a large number of electrodes 12 in a predetermined arrangement, and a predetermined electronic circuit (
(not shown).

20は、絶縁フィルム22に、多数の込み入っ7 た内部回路30とそれに連なるパッド32とを、上記電
極数の多い半導体チップ10に合わせて所定の配列で備
えたフィルムキャリアである。このフィルムキャリア2
0は、例えば第3図と第4図に示したように、ポリイミ
ドフィルムなどの絶縁フィルム22と、該フィルム表面
に被着した銅箔をエッチング加工して形成した内部回路
30とそれに連なるバッド32とであって、その表面に
金めつき等のめっきを施した内部回路30とそれに連な
るパッド32とからなっている。
Reference numeral 20 denotes a film carrier in which an insulating film 22 is provided with a large number of intricate internal circuits 30 and pads 32 connected thereto in a predetermined arrangement according to the semiconductor chip 10 having a large number of electrodes. This film carrier 2
0, as shown in FIGS. 3 and 4, for example, an insulating film 22 such as a polyimide film, an internal circuit 30 formed by etching copper foil adhered to the surface of the film, and a pad 32 connected thereto. It consists of an internal circuit 30 whose surface is plated with gold or the like, and a pad 32 connected thereto.

このフィルムキャリア20には、第4図に示したように
、その内部回路30下方にあたる絶縁フィルム22裏面
またはその内部(図では裏面としている)に、銅箔など
からなるグランド層34を備えていて、内部回路30を
高周波信号を効率良く伝達可能なマイクロストリップ線
路に形成している。なお、内部回路30に周波数の低い
信号を伝える等の場合は、上記グランド層34は備えな
《でも良い。また、第4図に示したように、バッド32
直下にあたるグランド層部分34aを円形8 状などに削除していて、パッド32に接続する後述のリ
ードがグランド層34に接しないようにしている。
As shown in FIG. 4, this film carrier 20 is provided with a ground layer 34 made of copper foil or the like on the back surface of the insulating film 22 below the internal circuit 30 or inside it (the back surface is shown in the figure). , the internal circuit 30 is formed into a microstrip line that can efficiently transmit high frequency signals. Note that in the case of transmitting a low frequency signal to the internal circuit 30, the ground layer 34 may not be provided. In addition, as shown in FIG.
The ground layer portion 34a immediately below is removed in a circular 8-shape or the like so that a lead, which will be described later and is connected to the pad 32, does not come into contact with the ground layer 34.

また、このフィルムキャリア20には、第3図と第4図
に示したように、前記バッド32およびその直下の絶縁
フィルム22を貫通する貫通孔40を設けていると共に
、その中央に方形状等をした窓42を透設していて、そ
の窓42内側に内部回路30先端が突出している。そし
て、その内部回路30先端に、それに対応する前記半導
体チップ10の表面周囲やその表面中央(図では表面周
囲としている)の電極12を、熱圧着などにより、接続
している。
Further, as shown in FIGS. 3 and 4, this film carrier 20 is provided with a through hole 40 that penetrates the pad 32 and the insulating film 22 directly below it, and has a rectangular or similar shape in the center. A transparent window 42 is provided, and the tip of the internal circuit 30 protrudes inside the window 42. Then, the electrodes 12 around the surface of the corresponding semiconductor chip 10 or at the center of the surface (in the figure, it is shown as the surface periphery) are connected to the tip of the internal circuit 30 by thermocompression bonding or the like.

50は、方形平板状をした、ガラスエポキシ樹脂やセラ
ミックなどからなる絶縁基板である。この絶縁基板50
には、第5図と第6図に示したように、その半導体チッ
プ10を搭載する中央部50aを除く四方周囲に多数の
金属製のリード60を所定ピッチで格子状に基板50を
貫通させて備えていて、基板50の表裏面にリード頭部
60aとその足部60bとがそれぞれ突出している。
50 is a rectangular flat insulating substrate made of glass epoxy resin, ceramic, or the like. This insulating substrate 50
As shown in FIGS. 5 and 6, a large number of metal leads 60 are passed through the substrate 50 in a lattice pattern at a predetermined pitch on all sides except for the central portion 50a where the semiconductor chip 10 is mounted. A lead head 60a and its foot 60b protrude from the front and back surfaces of the board 50, respectively.

この絶縁基板50表面に、内部回路30先端に半導体チ
ップの電極12を接続してなる前記フィルムキャリア2
0を、半導体チップ10と共に搭載している。
The film carrier 2 is formed by connecting the electrode 12 of the semiconductor chip to the tip of the internal circuit 30 on the surface of the insulating substrate 50.
0 is mounted together with the semiconductor chip 10.

なお、第1図と第2図では、半導体チップ10を、その
電極12を接続した内部回路30下方に位置させて、絶
縁基板50表面に搭載して、半導体チップ10を絶縁基
板50表面に密着させ、作動中の半導体チップ10が発
する熱を絶縁基板50を通してその外部に効率良く放散
させることができるようにしているが、場合によっては
逆に、第7図に示したように、半導体チップ10を、上
記内部回路20」二方に位置させて、絶縁基板50表面
に搭載しても良い。また、前記のように、半導体チップ
IOを絶縁基板50表面に密着させて搭載した場合は、
その半導体チップ10を搭載する絶縁基板50部分に金
属製などのヒートシンク(図示せず)を埋め込んで、そ
の絶縁基板50部分の熱放散性を高めても良い。
In FIGS. 1 and 2, the semiconductor chip 10 is positioned below the internal circuit 30 to which the electrodes 12 are connected, and is mounted on the surface of the insulating substrate 50, so that the semiconductor chip 10 is tightly attached to the surface of the insulating substrate 50. This allows the heat generated by the semiconductor chip 10 during operation to be efficiently dissipated to the outside through the insulating substrate 50. However, in some cases, on the contrary, as shown in FIG. may be mounted on the surface of the insulating substrate 50 so as to be located on both sides of the internal circuit 20. Furthermore, as described above, when the semiconductor chip IO is mounted in close contact with the surface of the insulating substrate 50,
A heat sink (not shown) made of metal or the like may be embedded in the insulating substrate 50 portion on which the semiconductor chip 10 is mounted to improve the heat dissipation performance of the insulating substrate 50 portion.

またそれと共に、前記フィルムキャリアの複数の貫通孔
40に、絶縁基板50表面に突出する多数のリード頭部
60aの全部をそれぞれ挿通している。そして、そのリ
ード頭部60aを、はんだ70を用いて、フィルムキャ
リアの内部回路30に連なるパッド32にはんだ付けし
ている。
At the same time, a large number of lead heads 60a protruding from the surface of the insulating substrate 50 are all inserted into the plurality of through holes 40 of the film carrier, respectively. Then, the lead head 60a is soldered using solder 70 to a pad 32 connected to the internal circuit 30 of the film carrier.

なお、」−記リード頭部60aとバッド32とは、導電
性のある接着剤等を用いて接続したり、またはリード頭
部60aをパッド32に設けた貫通孔40に圧入するこ
とにより接続したりしても良い。
Note that the lead head 60a and the pad 32 may be connected using a conductive adhesive or the like, or by press-fitting the lead head 60a into a through hole 40 provided in the pad 32. You can also

また、貫通孔40を設ける代わりに、パッドをフィルム
キャリアの絶縁フィルム22表面でなくその裏面に設け
て、そのパッドにリード頭部60aをはんだ付け等する
ことにより、リード60を、上記パッドを介して、該パ
ッドに絶縁フィルム22を貫通して連なるフィルムキャ
リア20の内部回路30に接続しても良い。
Alternatively, instead of providing the through hole 40, a pad is provided on the back surface of the insulating film 22 of the film carrier instead of on the surface, and the lead head 60a is soldered to the pad, so that the lead 60 can be inserted through the pad. Then, the pad may be connected to the internal circuit 30 of the film carrier 20 that extends through the insulating film 22.

さらに、フィルムキャリアの絶縁フィルム22裏而等に
備えたグランド層34を、絶縁基板50のグランド端子
を構成するリード頭部60aに直接にはんだ付け等によ
り接続したり、またはフィルムキャリア20のグランド
回路を構成する内部回路30を介して間接的に上記グラ
ンド端子を構成するリード頭部60aに接続したり、ま
たはフィルムキャリア20に内部回路30と別個に備え
たグランド回路(図示せず)を介して」―記グランド端
子を構成するリード頭部60aに接続したりしている。
Furthermore, the ground layer 34 provided on the insulating film 22 of the film carrier may be directly connected to the lead head 60a constituting the ground terminal of the insulating substrate 50 by soldering or the like, or the ground layer 34 of the film carrier 20 may be or indirectly connected to the lead head 60a forming the ground terminal through the internal circuit 30 forming the ground terminal, or via a ground circuit (not shown) provided in the film carrier 20 separately from the internal circuit 30. "-" is connected to the lead head 60a that constitutes the ground terminal.

なお、フィルムキャリア20にグランド層34を備えて
いない場合は、その必要がないことは言うまでもない。
Note that if the film carrier 20 is not provided with the ground layer 34, it goes without saying that it is not necessary.

またここで、フィルムキャリア20にグランド層34を
備えていない場合は、内部回路30下方にあたる前記絶
縁基板50表面またはその内部等に、内部回路30をマ
イクロストリップ線路に形成する銅箔などからなるグラ
ンド層(図示せず)を備えても良い。そして、そのグラ
ンド層を絶縁基板50のグランド端子を構成するり一ド
60に接続しても良い。
Here, if the film carrier 20 is not provided with the ground layer 34, a ground layer made of copper foil or the like for forming the internal circuit 30 in the form of a microstrip line is provided on the surface or inside of the insulating substrate 50 below the internal circuit 30. A layer (not shown) may also be provided. Then, the ground layer may be connected to the lead 60 that constitutes the ground terminal of the insulating substrate 50.

また、絶縁基板50表面に搭載した半導体チップ10を
含むフィルムキャリア20周囲を合成樹脂等の樹脂80
で覆っていて、その半導体チップ10とフィルムキャリ
ア20とを基板50表面部分と共に樹脂80内部に封止
している。
Further, the periphery of the film carrier 20 containing the semiconductor chip 10 mounted on the surface of the insulating substrate 50 is covered with a resin 80 such as a synthetic resin.
The semiconductor chip 10 and film carrier 20 are sealed inside the resin 80 along with the surface portion of the substrate 50.

なお、半導体チップ10を樹脂80内部により気密に封
止するために、絶縁基板50側部等も併せて樹脂80で
覆っても良い。
Note that in order to more airtightly seal the semiconductor chip 10 inside the resin 80, the sides of the insulating substrate 50 and the like may also be covered with the resin 80.

さらに、図の実施例では、第8図にその拡大端面図を示
したように、前記絶縁基板50裏面に突出するリード足
部60bを短丈に形成して、そのリード足部60b周囲
に、はんだ70をほぼ半球状に付着させてなるはんだバ
ンプ72を形成している。そして、上記リード足部60
bを、半導体装置実装用の基板(図示せず)表面の基板
の回路に連なるパッド(図示せず)に、」二記はんだバ
ンブ72を用いてはんだ付けして、半導体装置を基板に
表面実装できるようにしている。
Further, in the illustrated embodiment, as shown in an enlarged end view in FIG. 8, the lead foot portions 60b protruding from the back surface of the insulating substrate 50 are formed in short lengths, and around the lead foot portions 60b, Solder bumps 72 are formed by depositing solder 70 in a substantially hemispherical shape. Then, the lead leg portion 60
b is soldered to a pad (not shown) connected to a circuit on the board (not shown) on the surface of a board for mounting a semiconductor device (not shown) using solder bumps 72, and the semiconductor device is surface mounted on the board. I'm trying to make it possible.

なお、第7図に示したように、前記絶縁基板50真面に
突出するリード足部60bを長丈に形成して、そのリー
ド足部60bを、半導体装置実装用の基板(図示せず)
表面の基板の回路に連なる穴のあいたパッドやソケット
(図示せず)にはんだ付けしたり挿入したりして、半導
体装置を基板に実装できるようにしても良い。
As shown in FIG. 7, the lead foot portions 60b protruding directly from the insulating substrate 50 are formed to have a long length, and the lead foot portions 60b are attached to a substrate for mounting a semiconductor device (not shown).
The semiconductor device may be mounted on the board by soldering or inserting it into a pad or socket (not shown) with a hole connected to the circuit on the front board.

第1図と第2図に示した半導体装置は、以−1二のよう
に構成している。
The semiconductor device shown in FIGS. 1 and 2 is constructed as follows.

第9図は少数の電極を持つ半導体チップを封入してなる
本発明の半導体装置の好適な実施例を示し、詳しくはそ
の一部破断乎面図を示している。
FIG. 9 shows a preferred embodiment of the semiconductor device of the present invention, which is formed by enclosing a semiconductor chip having a small number of electrodes, and specifically shows a partially cutaway view of the semiconductor device.

以下、この図中の実施例を説明する。The embodiment shown in this figure will be described below.

図の半導体装置では、その内部に封入する電極数の少な
い半導体チップ10に合わせて、フィルムキャリア20
を絶縁基板50表面に比べて一回り小さく形成している
と共に、そのフィルムキャリア20に少数の内部回路3
0とそれに連なるパッド32とを所定の配列で備えてい
る。そして、その内部回路30先端に半導体チップの電
極12を接続していると共に、フィルムキャリアの内部
回路30に連なる複数のバッド32を絶縁基板50表面
に突出する多数のリード頭部60aの一部(図では絶縁
基板表面内側に突出するリード頭部)にそれぞれ接続し
ている。
In the semiconductor device shown in the figure, the film carrier 20 is
is formed one size smaller than the surface of the insulating substrate 50, and a small number of internal circuits 3 are formed on the film carrier 20.
0 and pads 32 connected thereto in a predetermined arrangement. The electrodes 12 of the semiconductor chip are connected to the tips of the internal circuits 30, and a plurality of pads 32 connected to the internal circuits 30 of the film carrier are connected to a portion of a large number of lead heads 60a protruding from the surface of the insulating substrate 50 ( In the figure, they are connected to the lead heads (in the figure) that protrude inside the surface of the insulating substrate.

その他は、第1図と第2図に示した既述半導体装置と同
様に構成している。
The rest of the structure is the same as the previously described semiconductor device shown in FIGS. 1 and 2.

第10図は同じく少数の電極を持つ半導体チップを封入
してなる本発明の半導体装置の他の好適な実施例を示し
、詳しくはその一部破断平面図を示している。以下、こ
の図中の実施例を説明する。
FIG. 10 shows another preferred embodiment of the semiconductor device of the present invention, which similarly includes a semiconductor chip having a small number of electrodes, and specifically shows a partially cutaway plan view thereof. The embodiment shown in this figure will be described below.

図の半導体装置では、フィルムキャリア20を絶縁基板
50表面と同じ大きさに形成していると共に、電極数の
少ない半導体チップ10に合わぜて、フィルムキャリア
20に少数の内部回路30とそれに連なるパッド32と
を所定の配列で備えている。そして、その内部回路30
先端に半導体チップの電極12を接続していると共に、
フィルムキャリアの内部回路に30に連なる複数のパッ
ド32を絶縁基板50表面に突出する多数のリード頭部
60aの一部(図では絶縁基板表面外側に突出するリー
ド頭部)にそれぞれ接続している。
In the semiconductor device shown in the figure, the film carrier 20 is formed to have the same size as the surface of the insulating substrate 50, and in order to accommodate the semiconductor chip 10 having a small number of electrodes, the film carrier 20 has a small number of internal circuits 30 and pads connected thereto. 32 in a predetermined arrangement. And its internal circuit 30
The electrode 12 of the semiconductor chip is connected to the tip, and
A plurality of pads 32 connected to 30 in the internal circuit of the film carrier are each connected to a part of a large number of lead heads 60a protruding from the surface of the insulating substrate 50 (in the figure, the lead heads protruding to the outside of the surface of the insulating substrate). .

さらに、上記リード頭部60aの一部をフィルムキャリ
アの内部回路30に連なるパッド32に的確に接続可能
なように、第10図に示したように、パソド32に接続
しないリード頭部60aを挿通する挿通孔40aをフィ
ルムキャリアの絶縁フィルム22表面に設けて、その挿
通孔/loaにパッド32に接続しないリード頭部60
aを挿通している。
Further, as shown in FIG. 10, the lead head 60a that is not connected to the pad 32 is inserted through the pad 32 so that a part of the lead head 60a can be accurately connected to the pad 32 connected to the internal circuit 30 of the film carrier. An insertion hole 40a is provided on the surface of the insulating film 22 of the film carrier, and a lead head 60 that is not connected to the pad 32 is provided in the insertion hole/loa.
A is inserted.

その他は、第1図と第2図に示した既述半導体装置と同
様に形成している。
The other parts are formed in the same manner as the previously described semiconductor device shown in FIGS. 1 and 2.

なお、上述半導体装置において、フィルムキャリア20
に」−記挿通孔40aを設ける代わりに、バッド32に
接続しないリード頭部60aを切除しても良い。ただし
、フィルムキャリアの絶縁フィルム22裏而にパッドを
備えて、該パッドにリード頭部60aを接続するように
した既述フィルムキャリアにあっては、その絶縁フィル
ム22表面に−L記挿通孔40aを設けたり、リード頭
部60aを切除したりする必要がないことは言うまでも
ない。
Note that in the above semiconductor device, the film carrier 20
Instead of providing the insertion hole 40a, the lead head 60a that is not connected to the pad 32 may be cut out. However, in the case of the above-mentioned film carrier in which a pad is provided behind the insulating film 22 of the film carrier and the lead head 60a is connected to the pad, the -L marking insertion hole 40a is formed on the surface of the insulating film 22. It goes without saying that there is no need to provide a lead head 60a or to cut out the lead head 60a.

第11図と第12図は電極数の少ない半導体チップを封
入してなる本発明の半導体装置のもう−っの好適な実施
例を示し、第11図はその一部破断乎面図、第12図は
第11図のD−D端面図を示している。以下、この図中
の実施例を説明する。
11 and 12 show another preferred embodiment of the semiconductor device of the present invention, which encapsulates a semiconductor chip with a small number of electrodes. The figure shows a DD end view of FIG. The embodiment shown in this figure will be described below.

図の半導体装置では、第5図と第6図に示したような、
多数のリード60を備えた既述絶縁基板50に代えて、
第13図と第14図に示したような、四方周囲に少数の
リード60を一列に備えた絶縁基板500を用いている
。そして、その絶縁基板500表面に、電極数の少ない
半導体チップ10に合わせて、少数の内部回路30とそ
れに連なるパッド32とを備えたフィルムキャリア20
であって、その内部回路30先端に半導体チップの電極
12を接続してなる上記基板500表面と同じ大きさの
フィルムキャリア20を半導体チップ10と共に搭載し
て、フィルムキャリアの内部回路30に連なる複数のパ
ッド32を絶縁基板500表面に突出する複数のリード
頭部60aの全部にそれぞれ接続している。
In the semiconductor device shown in the figure, as shown in FIGS. 5 and 6,
Instead of the previously described insulating substrate 50 equipped with a large number of leads 60,
An insulating substrate 500 as shown in FIGS. 13 and 14 is used, which has a small number of leads 60 arranged in a row around the four sides. Then, on the surface of the insulating substrate 500, a film carrier 20 is provided with a small number of internal circuits 30 and pads 32 connected thereto in accordance with the semiconductor chip 10 having a small number of electrodes.
A film carrier 20 having the same size as the surface of the substrate 500 with the electrode 12 of the semiconductor chip connected to the tip of the internal circuit 30 is mounted together with the semiconductor chip 10, and a plurality of film carriers connected to the internal circuit 30 of the film carrier are mounted. The pads 32 are respectively connected to all of the plurality of lead heads 60a protruding from the surface of the insulating substrate 500.

その他は、第1図と第2図に示した既述半導体装置と同
様に構成している。
The rest of the structure is the same as the previously described semiconductor device shown in FIGS. 1 and 2.

この半導体装置では、少数の内部回路3oを備えたフィ
ルムキャリア20に合わせて、絶縁基板に少数のり一ド
60を備えた絶縁基板500を用いているので、前述半
導体装置のように、バッド32に接続しないリード頭部
60aを挿通する挿通孔40aをフィルムキャリア20
に設けたり、バッド32に接続しないリード頭部60a
を切除したりする必要がない。
In this semiconductor device, an insulating substrate 500 having a small number of bonds 60 is used in conjunction with a film carrier 20 having a small number of internal circuits 3o. The film carrier 20 has an insertion hole 40a through which the unconnected lead head 60a is inserted.
Lead head 60a that is not connected to the pad 32 or connected to the pad 32
There is no need to remove it.

[発明の効果] 以上説明したように、本発明の半導体装置によれば、半
導体装置に封入する半導体チップの電極数や電極の配列
に合わせて、多数のリードを備えた絶縁基板表面に搭載
するフィルムキャリアを、所定数の内部回路とそれに連
なるパッドとを所定の配列で備えた大小のフィルムキャ
リアに変更したり、あるいは半導体装置に封入する半導
体チップの電極数や電極の配列に合わせて、フィルムキ
ャリアを所定数の内部回路とそれに連なるパッドとを所
定の配列で備えたフィルムキャリアに変更すると共に、
絶縁基板をそのフィルムキャリアに合った所定数のリー
ドを所定の配列で備えた絶縁基板に変更したりすること
により、種々の電極数や電極の配列を持った半導体チッ
プを封入してなる半導体装置を容易に形成できる。
[Effects of the Invention] As explained above, according to the semiconductor device of the present invention, the semiconductor chip can be mounted on the surface of an insulating substrate having a large number of leads in accordance with the number of electrodes and the arrangement of the electrodes of the semiconductor chip enclosed in the semiconductor device. You can change the film carrier to a large or small film carrier that has a predetermined number of internal circuits and pads connected to them in a predetermined arrangement, or change the film carrier to match the number and arrangement of electrodes of a semiconductor chip to be encapsulated in a semiconductor device. Changing the carrier to a film carrier equipped with a predetermined number of internal circuits and pads connected thereto in a predetermined arrangement,
Semiconductor devices in which semiconductor chips with various numbers of electrodes and electrode arrangements are encapsulated by changing the insulating substrate to an insulating substrate equipped with a predetermined number of leads in a predetermined arrangement that matches the film carrier. can be easily formed.

そのため、本発明の半導体装置を用いれば、多種少量生
産用の種々の半導体チップを封入してなる半導体装置、
即ち汎用性のある半導体装置を容易かつ迅速に提供する
ことが可能となる。
Therefore, by using the semiconductor device of the present invention, it is possible to produce a semiconductor device that is encapsulated with various semiconductor chips for high-variety, low-volume production.
That is, it becomes possible to provide a versatile semiconductor device easily and quickly.

また、本発明の半導体装置によれば、その製造に際して
、内部回路の先端等をフィルムキャリアの窓内側等に突
出させて、その突出させた内部回路に半導体チップの電
極を、ワイヤを介さずに、直接に接続できる。
Further, according to the semiconductor device of the present invention, when manufacturing the semiconductor device, the tip of the internal circuit is made to protrude to the inside of the window of the film carrier, and the electrodes of the semiconductor chip are connected to the protruded internal circuit without using wires. , can be connected directly.

そのため、半導体装置製造時におけるその内部回路と半
導体チップの電極との接続作業の大幅な容易化、迅速化
が図れる。
Therefore, the work of connecting the internal circuits of the semiconductor device and the electrodes of the semiconductor chip during manufacture of the semiconductor device can be greatly facilitated and speeded up.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は電極数の多い半導体チップを封入してなる本発
明の半導体装置の一部破断乎面図、第2図は第1図のA
−A端面図、第3図は第1図の半導体装置のフィルムキ
ャリアの一部省略平面図、第4図は第3図のB−B端面
図、第5図は第1図の半導体装置の絶縁基板の平面図、
第6図は第5図のC−C端面図、第7図は本発明の半導
体装置の他の実施例を示す正面端而図、第8図は第1図
の半導体装置の一部拡大端面図、第9図は電極数の少な
い半導体チップを封入してなる本発明の半導体装置の一
部破断乎而図、第10図は電極数の少ない半導体チップ
を封入してなる本発明の他の半導体装置の一部破断平面
図、第11図は電極数の少ない半導体チップを封入して
なる本発明のもう一つの半導体装置の一部破断乎面図、
第12図は第11図のD−D端而図、第13図は第11
図の半導体装置の絶縁基板の平面図、第]/l図は第1
3図のE−E端面図である。 10・・・半導体チップ、12・・・電極、20・・・
フィルムキャリア、30・・・内部回路、32・・パッ
ド、34・・・グランド層、40・・・貫通孔、50,
500・・・絶縁基板、60・・・リード、70・・・
はんだ、72・・はんだバンブ、80・・樹脂。 <J −295− 第 7 図 第 8 図 第 9 図 何ジ U 凶 第 11 図 第 13 図 第 12 図 第 14 図
FIG. 1 is a partially cutaway view of a semiconductor device of the present invention, which encapsulates a semiconductor chip with a large number of electrodes, and FIG.
-A end view, FIG. 3 is a partially omitted plan view of the film carrier of the semiconductor device in FIG. 1, FIG. 4 is a B-B end view of the semiconductor device in FIG. Top view of the insulating substrate,
6 is a CC end view of FIG. 5, FIG. 7 is a front end view showing another embodiment of the semiconductor device of the present invention, and FIG. 8 is a partially enlarged end view of the semiconductor device of FIG. 9 is a partially broken view of a semiconductor device of the present invention in which a semiconductor chip with a small number of electrodes is encapsulated, and FIG. 10 is a partially broken view of a semiconductor device of the present invention in which a semiconductor chip with a small number of electrodes is encapsulated. A partially cutaway plan view of a semiconductor device; FIG. 11 is a partially cutaway top view of another semiconductor device of the present invention in which a semiconductor chip with a small number of electrodes is enclosed;
Figure 12 is a D-D diagram of Figure 11, Figure 13 is a diagram of Figure 11.
Figure 1 is a plan view of the insulating substrate of the semiconductor device shown in Figure 1.
FIG. 3 is an end view taken along line E-E in FIG. 3; 10... Semiconductor chip, 12... Electrode, 20...
Film carrier, 30... Internal circuit, 32... Pad, 34... Ground layer, 40... Through hole, 50,
500... Insulating substrate, 60... Lead, 70...
Solder, 72...Solder bump, 80...Resin. <J -295- Fig. 7 Fig. 8 Fig. 9 Fig. 11 Fig. 13 Fig. 12 Fig. 14

Claims (1)

【特許請求の範囲】 1、絶縁フィルムに内部回路とそれに連なるパッドとを
備えたフィルムキャリアであって、その内部回路に半導
体チップの電極を接続してなるフィルムキャリアを、半
導体チップと共に絶縁基板表面に搭載して、前記パッド
を、前記基板を貫通させて備えたリードの基板表面に突
出するリード頭部に接続すると共に、前記半導体チップ
を含むフィルムキャリアを、それらを搭載した前記基板
表面部分と共に樹脂内部に封止してなる半導体装置。 2、内部回路下方にあたるフィルムキャリアの絶縁フィ
ルムまたは絶縁基板に、グランド層を備えた請求項1記
載の半導体装置。 3、絶縁基板裏面に突出するリード足部を短丈に形成し
て、そのリード足部周囲にはんだバンプを形成した請求
項1または2記載の半導体装置。 4、絶縁基板裏面に突出するリード足部を長丈に形成し
た請求項1または2記載の半導体装置。
[Claims] 1. A film carrier comprising an insulating film, an internal circuit, and a pad connected to the internal circuit, in which an electrode of a semiconductor chip is connected to the internal circuit. the pads are connected to the lead heads protruding from the substrate surface of the leads provided by penetrating the substrate, and the film carrier containing the semiconductor chips is mounted together with the surface portion of the substrate on which the semiconductor chips are mounted. A semiconductor device sealed inside a resin. 2. The semiconductor device according to claim 1, further comprising a ground layer on the insulating film or the insulating substrate of the film carrier below the internal circuit. 3. The semiconductor device according to claim 1 or 2, wherein the lead foot portions protruding from the back surface of the insulating substrate are formed short, and solder bumps are formed around the lead foot portions. 4. The semiconductor device according to claim 1 or 2, wherein the lead foot portions protruding from the back surface of the insulating substrate are formed in a long length.
JP2011576A 1990-01-19 1990-01-19 Semiconductor device Pending JPH03215949A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2011576A JPH03215949A (en) 1990-01-19 1990-01-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011576A JPH03215949A (en) 1990-01-19 1990-01-19 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH03215949A true JPH03215949A (en) 1991-09-20

Family

ID=11781742

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011576A Pending JPH03215949A (en) 1990-01-19 1990-01-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH03215949A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03293739A (en) * 1990-04-12 1991-12-25 Toshiba Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03293739A (en) * 1990-04-12 1991-12-25 Toshiba Corp Semiconductor device

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